IT1241520B - "dispositivo di memoria a semiconduttori". - Google Patents
"dispositivo di memoria a semiconduttori".Info
- Publication number
- IT1241520B IT1241520B IT48185A IT4818590A IT1241520B IT 1241520 B IT1241520 B IT 1241520B IT 48185 A IT48185 A IT 48185A IT 4818590 A IT4818590 A IT 4818590A IT 1241520 B IT1241520 B IT 1241520B
- Authority
- IT
- Italy
- Prior art keywords
- memory device
- semiconductor memory
- semiconductor
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890020108A KR920010344B1 (ko) | 1989-12-29 | 1989-12-29 | 반도체 메모리 어레이의 구성방법 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| IT9048185A0 IT9048185A0 (it) | 1990-07-31 |
| IT9048185A1 IT9048185A1 (it) | 1992-01-31 |
| IT1241520B true IT1241520B (it) | 1994-01-17 |
Family
ID=19294149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT48185A IT1241520B (it) | 1989-12-29 | 1990-07-31 | "dispositivo di memoria a semiconduttori". |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5097441A (it) |
| JP (1) | JPH0792998B2 (it) |
| KR (1) | KR920010344B1 (it) |
| CN (1) | CN1021996C (it) |
| DE (1) | DE4009836C2 (it) |
| FR (1) | FR2656725B1 (it) |
| GB (1) | GB2239558B (it) |
| IT (1) | IT1241520B (it) |
Families Citing this family (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0713864B2 (ja) * | 1989-09-27 | 1995-02-15 | 東芝マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
| GB2246001B (en) * | 1990-04-11 | 1994-06-15 | Digital Equipment Corp | Array architecture for high speed cache memory |
| JPH04271086A (ja) * | 1991-02-27 | 1992-09-28 | Nec Corp | 半導体集積回路 |
| KR940008722B1 (ko) * | 1991-12-04 | 1994-09-26 | 삼성전자 주식회사 | 반도체 메모리 장치의 워드라인 드라이버 배열방법 |
| DE69526006T2 (de) * | 1994-08-15 | 2003-01-02 | Ibm | Anordnung mit einem einzigen Verdrillungsgebiet und Verfahren für gepaarte linienförmige Leiter in integrierten Schaltungen |
| KR0172376B1 (ko) * | 1995-12-06 | 1999-03-30 | 김광호 | 서브워드라인 드라이버 구조를 가지는 반도체 메모리장치 |
| US5793383A (en) * | 1996-05-31 | 1998-08-11 | Townsend And Townsend And Crew Llp | Shared bootstrap circuit |
| US6034879A (en) * | 1998-02-19 | 2000-03-07 | University Of Pittsburgh | Twisted line techniques for multi-gigabit dynamic random access memories |
| JP2000340766A (ja) * | 1999-05-31 | 2000-12-08 | Fujitsu Ltd | 半導体記憶装置 |
| US7259464B1 (en) * | 2000-05-09 | 2007-08-21 | Micron Technology, Inc. | Vertical twist scheme for high-density DRAMs |
| CA2342496A1 (en) | 2001-03-30 | 2002-09-30 | Atmos Corporation | Twisted wordline straps |
| US6567329B2 (en) * | 2001-08-28 | 2003-05-20 | Intel Corporation | Multiple word-line accessing and accessor |
| KR100541818B1 (ko) * | 2003-12-18 | 2006-01-10 | 삼성전자주식회사 | 반도체 메모리 장치의 라인 배치구조 |
| JP4564299B2 (ja) | 2004-07-28 | 2010-10-20 | 株式会社東芝 | 半導体集積回路装置 |
| KR100825525B1 (ko) * | 2004-07-28 | 2008-04-25 | 가부시끼가이샤 도시바 | 반도체 집적 회로 장치 |
| US7110319B2 (en) * | 2004-08-27 | 2006-09-19 | Micron Technology, Inc. | Memory devices having reduced coupling noise between wordlines |
| JP4058045B2 (ja) * | 2005-01-05 | 2008-03-05 | 株式会社東芝 | 半導体記憶装置 |
| US20090154215A1 (en) * | 2007-12-14 | 2009-06-18 | Spansion Llc | Reducing noise and disturbance between memory storage elements using angled wordlines |
| JP5612803B2 (ja) * | 2007-12-25 | 2014-10-22 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | 半導体記憶装置 |
| US7830221B2 (en) * | 2008-01-25 | 2010-11-09 | Micron Technology, Inc. | Coupling cancellation scheme |
| KR102182583B1 (ko) | 2016-05-17 | 2020-11-24 | 실리콘 스토리지 테크놀로지 인크 | 비휘발성 메모리 어레이를 사용하는 딥러닝 신경망 분류기 |
| CN106097960B (zh) * | 2016-06-16 | 2018-09-14 | 武汉华星光电技术有限公司 | 一种双边驱动装置及平板显示器 |
| CN107622779B (zh) * | 2017-10-30 | 2024-03-26 | 长鑫存储技术有限公司 | 一种存储阵列块及半导体存储器 |
| US11087207B2 (en) | 2018-03-14 | 2021-08-10 | Silicon Storage Technology, Inc. | Decoders for analog neural memory in deep learning artificial neural network |
| US10803943B2 (en) | 2017-11-29 | 2020-10-13 | Silicon Storage Technology, Inc. | Neural network classifier using array of four-gate non-volatile memory cells |
| US10699779B2 (en) | 2017-11-29 | 2020-06-30 | Silicon Storage Technology, Inc. | Neural network classifier using array of two-gate non-volatile memory cells |
| US10748630B2 (en) | 2017-11-29 | 2020-08-18 | Silicon Storage Technology, Inc. | High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks |
| US10438636B2 (en) * | 2017-12-07 | 2019-10-08 | Advanced Micro Devices, Inc. | Capacitive structure for memory write assist |
| US11409352B2 (en) | 2019-01-18 | 2022-08-09 | Silicon Storage Technology, Inc. | Power management for an analog neural memory in a deep learning artificial neural network |
| US11893478B2 (en) | 2019-01-18 | 2024-02-06 | Silicon Storage Technology, Inc. | Programmable output blocks for analog neural memory in a deep learning artificial neural network |
| US11023559B2 (en) | 2019-01-25 | 2021-06-01 | Microsemi Soc Corp. | Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit |
| US11270771B2 (en) | 2019-01-29 | 2022-03-08 | Silicon Storage Technology, Inc. | Neural network classifier using array of stacked gate non-volatile memory cells |
| US11423979B2 (en) | 2019-04-29 | 2022-08-23 | Silicon Storage Technology, Inc. | Decoding system and physical layout for analog neural memory in deep learning artificial neural network |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57208691A (en) * | 1981-06-15 | 1982-12-21 | Mitsubishi Electric Corp | Semiconductor memory |
| JPS6059677B2 (ja) * | 1981-08-19 | 1985-12-26 | 富士通株式会社 | 半導体記憶装置 |
| JPS59124092A (ja) * | 1982-12-29 | 1984-07-18 | Fujitsu Ltd | メモリ装置 |
| US4729119A (en) * | 1984-05-21 | 1988-03-01 | General Computer Corporation | Apparatus and methods for processing data through a random access memory system |
| US4733374A (en) * | 1985-03-30 | 1988-03-22 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device |
| CA1305255C (en) * | 1986-08-25 | 1992-07-14 | Joseph Lebowitz | Marching interconnecting lines in semiconductor integrated circuits |
| JPS63153792A (ja) * | 1986-12-17 | 1988-06-27 | Sharp Corp | 半導体メモリ装置 |
| JPS63255898A (ja) * | 1987-04-14 | 1988-10-24 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH06105550B2 (ja) * | 1987-07-08 | 1994-12-21 | 三菱電機株式会社 | 半導体記憶装置 |
| JP2547615B2 (ja) * | 1988-06-16 | 1996-10-23 | 三菱電機株式会社 | 読出専用半導体記憶装置および半導体記憶装置 |
| JPH0713858B2 (ja) * | 1988-08-30 | 1995-02-15 | 三菱電機株式会社 | 半導体記憶装置 |
| JPH0713864B2 (ja) * | 1989-09-27 | 1995-02-15 | 東芝マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
-
1989
- 1989-12-29 KR KR1019890020108A patent/KR920010344B1/ko not_active IP Right Cessation
-
1990
- 1990-03-22 JP JP2069926A patent/JPH0792998B2/ja not_active Expired - Fee Related
- 1990-03-27 GB GB9006756A patent/GB2239558B/en not_active Expired - Lifetime
- 1990-03-27 DE DE4009836A patent/DE4009836C2/de not_active Expired - Lifetime
- 1990-03-29 FR FR9004026A patent/FR2656725B1/fr not_active Expired - Lifetime
- 1990-03-30 US US07/501,758 patent/US5097441A/en not_active Expired - Lifetime
- 1990-07-31 IT IT48185A patent/IT1241520B/it active IP Right Grant
- 1990-07-31 CN CN90106625A patent/CN1021996C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| FR2656725A1 (it) | 1991-07-05 |
| DE4009836A1 (de) | 1991-07-11 |
| CN1052966A (zh) | 1991-07-10 |
| DE4009836C2 (de) | 1994-01-27 |
| KR910013266A (ko) | 1991-08-08 |
| JPH0792998B2 (ja) | 1995-10-09 |
| JPH03203085A (ja) | 1991-09-04 |
| IT9048185A1 (it) | 1992-01-31 |
| GB2239558B (en) | 1993-08-18 |
| KR920010344B1 (ko) | 1992-11-27 |
| IT9048185A0 (it) | 1990-07-31 |
| US5097441A (en) | 1992-03-17 |
| GB9006756D0 (en) | 1990-05-23 |
| FR2656725B1 (it) | 1994-11-04 |
| GB2239558A (en) | 1991-07-03 |
| CN1021996C (zh) | 1993-09-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970528 |