KR880012004A - 반도체회로 - Google Patents
반도체회로 Download PDFInfo
- Publication number
- KR880012004A KR880012004A KR1019880003257A KR880003257A KR880012004A KR 880012004 A KR880012004 A KR 880012004A KR 1019880003257 A KR1019880003257 A KR 1019880003257A KR 880003257 A KR880003257 A KR 880003257A KR 880012004 A KR880012004 A KR 880012004A
- Authority
- KR
- South Korea
- Prior art keywords
- circuit
- predetermined value
- threshold voltage
- bistable
- semiconductor circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/2893—Bistables with hysteresis, e.g. Schmitt trigger
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 관한 반도체회로를 설명하는 회로도.
제2도는 제1도에 도시된 반도체회로의 동작을 설명하는 도면.
제3도는 본 발명의 다른 실시예에 관한 반도체회로를 설명하는 회로도.
Claims (2)
- 제1소정치로 설정되는 회로 임계치 전압을 갖는 쌍안정회로(Q1,Q2,I1,I2)와, 상기 제1소정치보다도 낮게 설정되는 제2회로임계치 전압 및 상기 제1소정치 보다도 높게 설정되는 제3도회로 임계치 전압을 갖으면서 상기 쌍안정회로로부터의 출력전위에 대응하는 전위를 출력하게 되는 쉬미트트리거회로(Q11,Q12,Q13,Q14,I3)를 구비하여 구성되는 것을 특징으로 하는 반도체회로.
- 제1항에 있어서, 상기 쌍안정회로는 셋트 신호(SET) 입력 단자와 리셋트 신호(RESET) 입력 단자를 갖추고 있는 R-S 플립플롭회로인 것을 특징으로하는 반도체회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-72103 | 1987-03-26 | ||
JP62072103A JP2549109B2 (ja) | 1987-03-26 | 1987-03-26 | 半導体回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880012004A true KR880012004A (ko) | 1988-10-31 |
KR910005372B1 KR910005372B1 (ko) | 1991-07-29 |
Family
ID=13479731
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880003257A KR910005372B1 (ko) | 1987-03-26 | 1988-03-25 | 반도체회로 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4849653A (ko) |
EP (1) | EP0283915B1 (ko) |
JP (1) | JP2549109B2 (ko) |
KR (1) | KR910005372B1 (ko) |
DE (1) | DE3889570T2 (ko) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4914318A (en) * | 1988-12-30 | 1990-04-03 | Intel Corporation | Latch circuit for a programmable logic device using dual n-type transistors |
US4958088A (en) * | 1989-06-19 | 1990-09-18 | Micron Technology, Inc. | Low power three-stage CMOS input buffer with controlled switching |
JP2621993B2 (ja) * | 1989-09-05 | 1997-06-18 | 株式会社東芝 | フリップフロップ回路 |
US5034623A (en) * | 1989-12-28 | 1991-07-23 | Texas Instruments Incorporated | Low power, TTL level CMOS input buffer with hysteresis |
US5365122A (en) * | 1990-11-09 | 1994-11-15 | Vlsi Technology, Inc. | Meta stable resistant signal detector |
JP3225528B2 (ja) * | 1991-03-26 | 2001-11-05 | 日本電気株式会社 | レジスタ回路 |
US5280203A (en) * | 1992-05-15 | 1994-01-18 | Altera Corporation | Look-ahead asynchronous register set/reset in programmable logic device |
US5319254A (en) * | 1992-07-23 | 1994-06-07 | Xilinx, Inc. | Logic cell which can be configured as a latch without static one's problem |
US5365125A (en) * | 1992-07-23 | 1994-11-15 | Xilinx, Inc. | Logic cell for field programmable gate array having optional internal feedback and optional cascade |
US5646547A (en) * | 1994-04-28 | 1997-07-08 | Xilinx, Inc. | Logic cell which can be configured as a latch without static one's problem |
US5287394A (en) * | 1993-03-22 | 1994-02-15 | Advanced Micro Devices, Inc. | Fast counter with uniform delay structures |
US5489866A (en) * | 1994-04-19 | 1996-02-06 | Xilinx, Inc. | High speed and low noise margin schmitt trigger with controllable trip point |
US6369630B1 (en) * | 1999-11-24 | 2002-04-09 | Bae Systems Information And Electronic Systems Integration Inc. | Single-event upset hardened reconfigurable bi-stable CMOS latch |
JP2005151170A (ja) * | 2003-11-14 | 2005-06-09 | Renesas Technology Corp | 半導体集積回路 |
JP5440038B2 (ja) * | 2009-09-02 | 2014-03-12 | 日本電気株式会社 | 電源インタフェース、受信回路、集積回路、及び信号伝送方法 |
US8508276B2 (en) * | 2010-08-25 | 2013-08-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including latch circuit |
JP5396543B2 (ja) * | 2010-09-02 | 2014-01-22 | シャープ株式会社 | 信号処理回路、ドライバ回路、表示装置 |
KR102487109B1 (ko) * | 2015-12-15 | 2023-01-09 | 엘지디스플레이 주식회사 | 게이트 구동회로 및 이를 포함하는 표시 장치 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4735751U (ko) * | 1971-05-07 | 1972-12-20 | ||
JPS4995550A (ko) * | 1973-01-12 | 1974-09-10 | ||
JPS5779726A (en) * | 1980-11-04 | 1982-05-19 | Nec Corp | Highly reliable logical circuit |
US4687954A (en) * | 1984-03-06 | 1987-08-18 | Kabushiki Kaisha Toshiba | CMOS hysteresis circuit with enable switch or natural transistor |
JPS61128621A (ja) * | 1984-11-27 | 1986-06-16 | Rohm Co Ltd | フリツプフロツプ回路 |
JPS61283092A (ja) * | 1985-06-06 | 1986-12-13 | Mitsubishi Electric Corp | リセツトあるいはセツト付記憶回路を有した半導体集積回路 |
-
1987
- 1987-03-26 JP JP62072103A patent/JP2549109B2/ja not_active Expired - Fee Related
-
1988
- 1988-03-08 US US07/165,706 patent/US4849653A/en not_active Expired - Lifetime
- 1988-03-16 DE DE3889570T patent/DE3889570T2/de not_active Expired - Fee Related
- 1988-03-16 EP EP88104172A patent/EP0283915B1/en not_active Expired - Lifetime
- 1988-03-25 KR KR1019880003257A patent/KR910005372B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE3889570D1 (de) | 1994-06-23 |
JP2549109B2 (ja) | 1996-10-30 |
DE3889570T2 (de) | 1994-09-29 |
JPS63237608A (ja) | 1988-10-04 |
US4849653A (en) | 1989-07-18 |
KR910005372B1 (ko) | 1991-07-29 |
EP0283915B1 (en) | 1994-05-18 |
EP0283915A2 (en) | 1988-09-28 |
EP0283915A3 (en) | 1990-07-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR880012004A (ko) | 반도체회로 | |
KR940010530A (ko) | 에미터 결합 로직(ECL)-바이폴라 상보형 금속 산화물 반도체(BiCMOS)/상보형금속 산화물 반도체(CMOS) 트랜슬레이터 | |
KR890012385A (ko) | 반도체 집적회로 | |
KR840002176A (ko) | 반도체 집적회로 장치 | |
KR860006837A (ko) | 내부회로 검사용 검사회로를 갖는 반도체 집적회로 | |
KR890017875A (ko) | 마스터-슬레이브 플립플롭회로 | |
KR960036332A (ko) | 논리회로 | |
KR870009528A (ko) | 버퍼회로 | |
KR840000114A (ko) | 위상 비교기 | |
KR910016077A (ko) | 반도체집적회로 | |
KR890010922A (ko) | Dc 테스트 기능을 갖춘 반도체 집적회로 | |
KR910017734A (ko) | 전자기기장치 | |
ATE68646T1 (de) | Emittergekoppelte logische schaltungen. | |
US5045718A (en) | Circuit for detecting power supply voltage variation | |
KR830008565A (ko) | 에미터 기능논리래로된 카운터 회로 | |
KR920008758A (ko) | 파워-온 리세트회로 | |
KR890003130A (ko) | 전압 레벨 변환기 | |
KR840003165A (ko) | 게이트 다이오드 스위치용 제어회로 | |
KR910001977A (ko) | 동기화된 비교기 회로를 구비한 반도체 집적 회로 | |
KR900000767A (ko) | 순서 선택 우선의 임의/순서 선택회로 | |
KR880004398A (ko) | 비교회로 | |
KR840002174A (ko) | 스위치 회로 | |
US3205372A (en) | Schmitt trigger circuit characterized by noise insensitivity | |
KR910021027A (ko) | 차동 ecl 삼-상태 검출 수신기 | |
KR920011078A (ko) | 래치 회로 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030701 Year of fee payment: 13 |
|
LAPS | Lapse due to unpaid annual fee |