DE3850855D1 - Halbleitervorrichtung. - Google Patents

Halbleitervorrichtung.

Info

Publication number
DE3850855D1
DE3850855D1 DE3850855T DE3850855T DE3850855D1 DE 3850855 D1 DE3850855 D1 DE 3850855D1 DE 3850855 T DE3850855 T DE 3850855T DE 3850855 T DE3850855 T DE 3850855T DE 3850855 D1 DE3850855 D1 DE 3850855D1
Authority
DE
Germany
Prior art keywords
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850855T
Other languages
English (en)
Other versions
DE3850855T2 (de
Inventor
Yoshio Komiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62285473A external-priority patent/JPH0821675B2/ja
Priority claimed from JP62287394A external-priority patent/JPH0817177B2/ja
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Publication of DE3850855D1 publication Critical patent/DE3850855D1/de
Application granted granted Critical
Publication of DE3850855T2 publication Critical patent/DE3850855T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221Three dimensional integrated circuits stacked in different levels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/764Air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
DE3850855T 1987-11-13 1988-11-11 Halbleitervorrichtung. Expired - Fee Related DE3850855T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62285473A JPH0821675B2 (ja) 1987-11-13 1987-11-13 半導体装置
JP62287394A JPH0817177B2 (ja) 1987-11-16 1987-11-16 半導体装置

Publications (2)

Publication Number Publication Date
DE3850855D1 true DE3850855D1 (de) 1994-09-01
DE3850855T2 DE3850855T2 (de) 1994-11-10

Family

ID=26555903

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850855T Expired - Fee Related DE3850855T2 (de) 1987-11-13 1988-11-11 Halbleitervorrichtung.

Country Status (3)

Country Link
US (1) US5122856A (de)
EP (1) EP0316799B1 (de)
DE (1) DE3850855T2 (de)

Families Citing this family (84)

* Cited by examiner, † Cited by third party
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JPH02257643A (ja) * 1989-03-29 1990-10-18 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH03190281A (ja) * 1989-12-18 1991-08-20 Honeywell Inc 半導体デバイス及びピエゾ抵抗型トランスデューサとその形成方法
JPH04103138A (ja) * 1990-08-22 1992-04-06 Mitsubishi Electric Corp 半導体集積回路
US6627953B1 (en) 1990-12-31 2003-09-30 Kopin Corporation High density electronic circuit modules
US6143582A (en) 1990-12-31 2000-11-07 Kopin Corporation High density electronic circuit modules
US5376561A (en) * 1990-12-31 1994-12-27 Kopin Corporation High density electronic circuit modules
JP2914798B2 (ja) * 1991-10-09 1999-07-05 株式会社東芝 半導体装置
JPH05129423A (ja) * 1991-10-30 1993-05-25 Rohm Co Ltd 半導体装置及びその製造方法
DE4204004A1 (de) * 1992-02-12 1993-08-19 Daimler Benz Ag Verfahren zur herstellung einer halbleiterstruktur mit vertikalen und lateralen halbleiterbauelementen und nach dem verfahren hergestellte halbleiterstruktur
US5489554A (en) * 1992-07-21 1996-02-06 Hughes Aircraft Company Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer
US5343071A (en) * 1993-04-28 1994-08-30 Raytheon Company Semiconductor structures having dual surface via holes
JPH09503622A (ja) 1993-09-30 1997-04-08 コピン・コーポレーシヨン 転写薄膜回路を使用した3次元プロセッサー
US5683919A (en) * 1994-11-14 1997-11-04 Texas Instruments Incorporated Transistor and circuit incorporating same
US5825092A (en) * 1996-05-20 1998-10-20 Harris Corporation Integrated circuit with an air bridge having a lid
US5949144A (en) * 1996-05-20 1999-09-07 Harris Corporation Pre-bond cavity air bridge
US5965933A (en) * 1996-05-28 1999-10-12 Young; William R. Semiconductor packaging apparatus
US5834810A (en) * 1996-10-17 1998-11-10 Mitsubishi Semiconductor America, Inc. Asymmetrical vertical lightly doped drain transistor and method of forming the same
DE19716102C2 (de) * 1997-04-17 2003-09-25 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Bauelementen und Verfahren zu deren Herstellung
US6057600A (en) * 1997-11-27 2000-05-02 Kyocera Corporation Structure for mounting a high-frequency package
IL123207A0 (en) 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
WO1999063596A1 (de) 1998-06-04 1999-12-09 GFD-Gesellschaft für Diamantprodukte mbH Diamantbauelement mit rückseitenkontaktierung und verfahren zu seiner herstellung
US6093623A (en) * 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
DE19846232A1 (de) * 1998-09-03 2000-03-09 Fraunhofer Ges Forschung Verfahren zur Herstellung eines Halbleiterbauelements mit Rückseitenkontaktierung
US6423613B1 (en) 1998-11-10 2002-07-23 Micron Technology, Inc. Low temperature silicon wafer bond process with bulk material bond strength
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US6300670B1 (en) 1999-07-26 2001-10-09 Stmicroelectronics, Inc. Backside bus vias
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DE10008386A1 (de) * 2000-02-23 2001-08-30 Giesecke & Devrient Gmbh Verfahren zum Verbinden von Substraten einer vertikal integrierten Schaltungsstruktur
US6693358B2 (en) * 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
US6852167B2 (en) 2001-03-01 2005-02-08 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US6835974B2 (en) * 2002-03-14 2004-12-28 Jeng-Jye Shau Three dimensional integrated circuits using sub-micron thin-film diodes
US7589029B2 (en) 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
JP4216634B2 (ja) * 2003-04-23 2009-01-28 株式会社日立製作所 半導体装置
JP4529493B2 (ja) * 2004-03-12 2010-08-25 株式会社日立製作所 半導体装置
TWI273682B (en) * 2004-10-08 2007-02-11 Epworks Co Ltd Method for manufacturing wafer level chip scale package using redistribution substrate
JP4873517B2 (ja) * 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US7560395B2 (en) 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
DE102005002023B4 (de) * 2005-01-15 2007-08-16 Atmel Germany Gmbh Halbleiterstruktur mit vertikalem JFET
KR101029215B1 (ko) 2005-02-16 2011-04-12 가부시키가이샤 히타치세이사쿠쇼 전자 태그용 반도체 장치 및 rfid 태크
US7485967B2 (en) * 2005-03-10 2009-02-03 Sanyo Electric Co., Ltd. Semiconductor device with via hole for electric connection
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
DE102006012739B3 (de) * 2006-03-17 2007-11-08 Infineon Technologies Ag Leistungstransistor und Leistungshalbleiterbauteil
JP5168819B2 (ja) * 2006-06-02 2013-03-27 日産自動車株式会社 半導体パッケージおよびその製造方法
US7605030B2 (en) 2006-08-31 2009-10-20 Micron Technology, Inc. Hafnium tantalum oxynitride high-k dielectric and metal gates
US7759747B2 (en) 2006-08-31 2010-07-20 Micron Technology, Inc. Tantalum aluminum oxynitride high-κ dielectric
US7776765B2 (en) 2006-08-31 2010-08-17 Micron Technology, Inc. Tantalum silicon oxynitride high-k dielectrics and metal gates
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
KR101460141B1 (ko) 2007-03-05 2014-12-02 인벤사스 코포레이션 관통 비아에 의해 전면 컨택트에 연결되는 배면 컨택트를 갖는 칩
DE102007019638A1 (de) 2007-04-26 2008-10-30 Robert Bosch Gmbh Verfahren zur Herstellung eines mikromechanischen Bauelements mit Trenchstruktur zur Rückseitenkontaktierung
DE102007034306B3 (de) * 2007-07-24 2009-04-02 Austriamicrosystems Ag Halbleitersubstrat mit Durchkontaktierung und Verfahren zur Herstellung eines Halbleitersubstrates mit Durchkontaktierung
WO2009017835A2 (en) 2007-07-31 2009-02-05 Tessera, Inc. Semiconductor packaging process using through silicon vias
US8420530B2 (en) 2007-08-10 2013-04-16 Agency For Science, Technology And Research Nano-interconnects for atomic and molecular scale circuits
EP2031653B1 (de) * 2007-08-27 2014-03-05 Denso Corporation Herstellungsverfahren für ein Halbleiterbbauelement mit mehreren Elementbildungsbereichen
US8710568B2 (en) * 2007-10-24 2014-04-29 Denso Corporation Semiconductor device having a plurality of elements on one semiconductor substrate and method of manufacturing the same
US8823179B2 (en) * 2008-05-21 2014-09-02 Chia-Lun Tsai Electronic device package and method for fabricating the same
DE102008033395B3 (de) * 2008-07-16 2010-02-04 Austriamicrosystems Ag Verfahren zur Herstellung eines Halbleiterbauelementes und Halbleiterbauelement
JP2010103300A (ja) * 2008-10-23 2010-05-06 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2010272737A (ja) * 2009-05-22 2010-12-02 Elpida Memory Inc 半導体装置の製造方法
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US9159825B2 (en) 2010-10-12 2015-10-13 Silanna Semiconductor U.S.A., Inc. Double-sided vertical semiconductor device with thinned substrate
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US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
CN102592982B (zh) * 2011-01-17 2017-05-03 精材科技股份有限公司 晶片封装体的形成方法
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US9466536B2 (en) 2013-03-27 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator integrated circuit with back side gate
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US9893058B2 (en) * 2015-09-17 2018-02-13 Semiconductor Components Industries, Llc Method of manufacturing a semiconductor device having reduced on-state resistance and structure
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DE102020210937A1 (de) 2020-08-31 2022-03-03 Robert Bosch Gesellschaft mit beschränkter Haftung Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements
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US4835589A (en) * 1987-09-28 1989-05-30 Motorola, Inc. Ram cell having trench sidewall load

Also Published As

Publication number Publication date
US5122856A (en) 1992-06-16
EP0316799B1 (de) 1994-07-27
DE3850855T2 (de) 1994-11-10
EP0316799A1 (de) 1989-05-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee