DE3850629D1 - Adaptierbarer Schaltkreis. - Google Patents

Adaptierbarer Schaltkreis.

Info

Publication number
DE3850629D1
DE3850629D1 DE3850629T DE3850629T DE3850629D1 DE 3850629 D1 DE3850629 D1 DE 3850629D1 DE 3850629 T DE3850629 T DE 3850629T DE 3850629 T DE3850629 T DE 3850629T DE 3850629 D1 DE3850629 D1 DE 3850629D1
Authority
DE
Germany
Prior art keywords
adaptable circuit
adaptable
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850629T
Other languages
English (en)
Other versions
DE3850629T2 (de
Inventor
David H Carey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microelectronics and Computer Technology Corp
Original Assignee
Microelectronics and Computer Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microelectronics and Computer Technology Corp filed Critical Microelectronics and Computer Technology Corp
Publication of DE3850629D1 publication Critical patent/DE3850629D1/de
Application granted granted Critical
Publication of DE3850629T2 publication Critical patent/DE3850629T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382Adaptable interconnections, e.g. for engineering changes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/0287Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Wire Bonding (AREA)
DE3850629T 1987-09-29 1988-09-28 Adaptierbarer Schaltkreis. Expired - Fee Related DE3850629T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10217287A 1987-09-29 1987-09-29

Publications (2)

Publication Number Publication Date
DE3850629D1 true DE3850629D1 (de) 1994-08-18
DE3850629T2 DE3850629T2 (de) 1995-01-05

Family

ID=22288486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850629T Expired - Fee Related DE3850629T2 (de) 1987-09-29 1988-09-28 Adaptierbarer Schaltkreis.

Country Status (6)

Country Link
US (1) US5132878A (de)
EP (1) EP0310357B1 (de)
JP (1) JPH01165134A (de)
AU (1) AU610249B2 (de)
CA (1) CA1310099C (de)
DE (1) DE3850629T2 (de)

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US5224022A (en) * 1990-05-15 1993-06-29 Microelectronics And Computer Technology Corporation Reroute strategy for high density substrates
US5142828A (en) * 1990-06-25 1992-09-01 Microelectronics And Computer Technology Corporation Correcting a defective metallization layer on an electronic component by polishing
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US5220490A (en) * 1990-10-25 1993-06-15 Microelectronics And Computer Technology Corporation Substrate interconnect allowing personalization using spot surface links
US5382315A (en) * 1991-02-11 1995-01-17 Microelectronics And Computer Technology Corporation Method of forming etch mask using particle beam deposition
US5379191A (en) * 1991-02-26 1995-01-03 Microelectronics And Computer Technology Corporation Compact adapter package providing peripheral to area translation for an integrated circuit chip
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US5440805A (en) * 1992-03-09 1995-08-15 Rogers Corporation Method of manufacturing a multilayer circuit
US5544018A (en) * 1994-04-13 1996-08-06 Microelectronics And Computer Technology Corporation Electrical interconnect device with customizeable surface layer and interwoven signal lines
US5844297A (en) * 1995-09-26 1998-12-01 Symbios, Inc. Antifuse device for use on a field programmable interconnect chip
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US6255602B1 (en) * 1999-03-15 2001-07-03 Wentworth Laboratories, Inc. Multiple layer electrical interface
US6354000B1 (en) * 1999-05-12 2002-03-12 Microconnex Corp. Method of creating an electrical interconnect device bearing an array of electrical contact pads
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US7525890B2 (en) * 2001-09-29 2009-04-28 Samsung Electronics Co., Ltd. Method of and apparatus for recording data on optical recording medium
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US6753482B1 (en) * 2002-05-06 2004-06-22 Micron Technology, Inc. Semiconductor component with adjustment circuitry
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JP3908148B2 (ja) * 2002-10-28 2007-04-25 シャープ株式会社 積層型半導体装置
US20050161814A1 (en) * 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
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US7181837B2 (en) * 2004-06-04 2007-02-27 Micron Technology, Inc. Plating buss and a method of use thereof
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Also Published As

Publication number Publication date
JPH01165134A (ja) 1989-06-29
EP0310357B1 (de) 1994-07-13
AU2283588A (en) 1989-04-06
EP0310357A2 (de) 1989-04-05
CA1310099C (en) 1992-11-10
AU610249B2 (en) 1991-05-16
EP0310357A3 (de) 1991-01-09
DE3850629T2 (de) 1995-01-05
US5132878A (en) 1992-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee