DE3820800A1 - Datenuebertragungsschaltung - Google Patents

Datenuebertragungsschaltung

Info

Publication number
DE3820800A1
DE3820800A1 DE3820800A DE3820800A DE3820800A1 DE 3820800 A1 DE3820800 A1 DE 3820800A1 DE 3820800 A DE3820800 A DE 3820800A DE 3820800 A DE3820800 A DE 3820800A DE 3820800 A1 DE3820800 A1 DE 3820800A1
Authority
DE
Germany
Prior art keywords
data
line
circuit
output
data bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3820800A
Other languages
German (de)
English (en)
Inventor
Yong Eue Park
Soo In Cho
Dong Soo Jun
Seung Mo Seo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Semiconductor and Telecomunications Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Semiconductor and Telecomunications Co Ltd filed Critical Samsung Semiconductor and Telecomunications Co Ltd
Publication of DE3820800A1 publication Critical patent/DE3820800A1/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE3820800A 1987-06-20 1988-06-20 Datenuebertragungsschaltung Granted DE3820800A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870006287A KR900006293B1 (ko) 1987-06-20 1987-06-20 씨모오스 디램의 데이터 전송회로

Publications (1)

Publication Number Publication Date
DE3820800A1 true DE3820800A1 (de) 1988-12-29

Family

ID=19262251

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3820800A Granted DE3820800A1 (de) 1987-06-20 1988-06-20 Datenuebertragungsschaltung

Country Status (6)

Country Link
US (1) US5153459A (ja)
JP (1) JPS6419588A (ja)
KR (1) KR900006293B1 (ja)
DE (1) DE3820800A1 (ja)
FR (1) FR2616934B1 (ja)
NL (1) NL192155C (ja)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920001082B1 (ko) * 1989-06-13 1992-02-01 삼성전자 주식회사 반도체 메모리장치에 있어서 메모리 테스트용 멀티바이트 광역 병렬 라이트회로
JP2545481B2 (ja) * 1990-03-09 1996-10-16 富士通株式会社 半導体記憶装置
JP2745251B2 (ja) * 1991-06-12 1998-04-28 三菱電機株式会社 半導体メモリ装置
US5243572A (en) * 1992-01-15 1993-09-07 Motorola, Inc. Deselect circuit
KR930020442A (ko) * 1992-03-13 1993-10-19 김광호 데이타의 고속 액세스가 이루어지는 비트라인 제어회로
US5682110A (en) * 1992-03-23 1997-10-28 Texas Instruments Incorporated Low capacitance bus driver
US6028796A (en) * 1992-04-02 2000-02-22 Sony Corporation Read-out circuit for semiconductor memory device
US5289415A (en) * 1992-04-17 1994-02-22 Motorola, Inc. Sense amplifier and latching circuit for an SRAM
KR0127263B1 (ko) * 1993-02-23 1997-12-29 사토 후미오 반도체 집적회로
DE69426845T2 (de) * 1993-06-30 2001-09-13 St Microelectronics Inc Verfahren und Einrichtung zur Parallelprüfung von Speichern
US5721875A (en) * 1993-11-12 1998-02-24 Intel Corporation I/O transceiver having a pulsed latch receiver circuit
JP4197755B2 (ja) 1997-11-19 2008-12-17 富士通株式会社 信号伝送システム、該信号伝送システムのレシーバ回路、および、該信号伝送システムが適用される半導体記憶装置
US6347350B1 (en) 1998-12-22 2002-02-12 Intel Corporation Driving the last inbound signal on a line in a bus with a termination
US6738844B2 (en) * 1998-12-23 2004-05-18 Intel Corporation Implementing termination with a default signal on a bus line
US7269212B1 (en) 2000-09-05 2007-09-11 Rambus Inc. Low-latency equalization in multi-level, multi-line communication systems
US7161513B2 (en) 1999-10-19 2007-01-09 Rambus Inc. Apparatus and method for improving resolution of a current mode driver
US7124221B1 (en) 1999-10-19 2006-10-17 Rambus Inc. Low latency multi-level communication interface
US6396329B1 (en) 1999-10-19 2002-05-28 Rambus, Inc Method and apparatus for receiving high speed signals with low latency
US6603817B1 (en) * 2000-03-21 2003-08-05 Mitsubisihi Denki Kabushiki Kaisha Buffer circuit capable of correctly transferring small amplitude signal in synchronization with high speed clock signal
US8861667B1 (en) 2002-07-12 2014-10-14 Rambus Inc. Clock data recovery circuit with equalizer clock calibration
US7362800B1 (en) 2002-07-12 2008-04-22 Rambus Inc. Auto-configured equalizer
US7292629B2 (en) * 2002-07-12 2007-11-06 Rambus Inc. Selectable-tap equalizer
US7903477B2 (en) 2008-02-29 2011-03-08 Mosaid Technologies Incorporated Pre-charge voltage generation and power saving modes
CN114255793A (zh) 2020-11-20 2022-03-29 台湾积体电路制造股份有限公司 存储器器件的写入电路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4402066A (en) * 1980-02-16 1983-08-30 Fujitsu Limited Semiconductor memory circuit
EP0170286A2 (en) * 1984-08-03 1986-02-05 Kabushiki Kaisha Toshiba Semiconductor memory device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592996B2 (ja) * 1976-05-24 1984-01-21 株式会社日立製作所 半導体記憶回路
US4202045A (en) * 1979-03-05 1980-05-06 Motorola, Inc. Write circuit for a read/write memory
JPS5851354B2 (ja) * 1980-10-15 1983-11-16 富士通株式会社 半導体記憶装置
JPS57127989A (en) * 1981-02-02 1982-08-09 Hitachi Ltd Mos static type ram
JPS58203694A (ja) * 1982-05-21 1983-11-28 Nec Corp メモリ回路
US4665508A (en) * 1985-05-23 1987-05-12 Texas Instruments Incorporated Gallium arsenide MESFET memory
US4686396A (en) * 1985-08-26 1987-08-11 Xerox Corporation Minimum delay high speed bus driver
JPS62165785A (ja) * 1986-01-17 1987-07-22 Mitsubishi Electric Corp 半導体記憶装置
US4763303A (en) * 1986-02-24 1988-08-09 Motorola, Inc. Write-drive data controller
KR890003488B1 (ko) * 1986-06-30 1989-09-22 삼성전자 주식회사 데이터 전송회로
JPH0831275B2 (ja) * 1986-09-09 1996-03-27 日本電気株式会社 メモリ回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4402066A (en) * 1980-02-16 1983-08-30 Fujitsu Limited Semiconductor memory circuit
EP0170286A2 (en) * 1984-08-03 1986-02-05 Kabushiki Kaisha Toshiba Semiconductor memory device

Also Published As

Publication number Publication date
KR890001304A (ko) 1989-03-20
NL192155C (nl) 1997-02-04
FR2616934B1 (fr) 1993-07-02
NL8801541A (nl) 1989-01-16
JPH0583999B2 (ja) 1993-11-30
US5153459A (en) 1992-10-06
NL192155B (nl) 1996-10-01
FR2616934A1 (fr) 1988-12-23
JPS6419588A (en) 1989-01-23
KR900006293B1 (ko) 1990-08-27

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: SAMSUNG ELECTRONICS CO., LTD., SUWON, KYONGGI, KR

D2 Grant after examination
8364 No opposition during term of opposition