DE102006059396A1 - Speichersystem - Google Patents

Speichersystem Download PDF

Info

Publication number
DE102006059396A1
DE102006059396A1 DE102006059396A DE102006059396A DE102006059396A1 DE 102006059396 A1 DE102006059396 A1 DE 102006059396A1 DE 102006059396 A DE102006059396 A DE 102006059396A DE 102006059396 A DE102006059396 A DE 102006059396A DE 102006059396 A1 DE102006059396 A1 DE 102006059396A1
Authority
DE
Germany
Prior art keywords
memory
primary
memories
signals
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE102006059396A
Other languages
German (de)
English (en)
Inventor
Jae-jun Seongnam Lee
Joo-Sun Yongin Choi
Kyu-hyoun Suwon Kim
Kwang-Soo Suwon Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020050120882A external-priority patent/KR101131919B1/ko
Priority claimed from KR1020060005103A external-priority patent/KR100735026B1/ko
Priority claimed from US11/603,648 external-priority patent/US7405949B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102006059396A1 publication Critical patent/DE102006059396A1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array

Landscapes

  • Memory System (AREA)
DE102006059396A 2005-12-09 2006-12-08 Speichersystem Ceased DE102006059396A1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR10-2005-0120882 2005-12-09
KR1020050120882A KR101131919B1 (ko) 2005-12-09 2005-12-09 메모리 시스템 및 이 시스템의 신호 송수신 방법
KR10-2006-0005103 2006-01-17
KR1020060005103A KR100735026B1 (ko) 2006-01-17 2006-01-17 메모리 시스템
US11/603,648 2006-11-22
US11/603,648 US7405949B2 (en) 2005-12-09 2006-11-22 Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices

Publications (1)

Publication Number Publication Date
DE102006059396A1 true DE102006059396A1 (de) 2007-06-28

Family

ID=38109057

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102006059396A Ceased DE102006059396A1 (de) 2005-12-09 2006-12-08 Speichersystem

Country Status (2)

Country Link
JP (1) JP5165233B2 (ja)
DE (1) DE102006059396A1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7990737B2 (en) * 2005-12-23 2011-08-02 Intel Corporation Memory systems with memory chips down and up
JP5430880B2 (ja) 2008-06-04 2014-03-05 ピーエスフォー ルクスコ エスエイアールエル メモリモジュール及びその使用方法、並びにメモリシステム
JP6348234B2 (ja) * 2015-09-18 2018-06-27 株式会社日立製作所 メモリコントローラ、メモリ制御方法および半導体記憶装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3865790B2 (ja) * 1997-06-27 2007-01-10 株式会社ルネサステクノロジ メモリモジュール
JP3973337B2 (ja) * 2000-02-08 2007-09-12 株式会社日立製作所 記憶素子及びそれを用いた記憶装置
US6493250B2 (en) * 2000-12-28 2002-12-10 Intel Corporation Multi-tier point-to-point buffered memory interface
JP4410676B2 (ja) * 2002-07-01 2010-02-03 株式会社日立製作所 方向性結合式バスシステム
JP4082519B2 (ja) * 2002-07-22 2008-04-30 株式会社ルネサステクノロジ 半導体集積回路装置、データ処理システム及びメモリシステム
JP4094370B2 (ja) * 2002-07-31 2008-06-04 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
JP4159415B2 (ja) * 2002-08-23 2008-10-01 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
KR100468761B1 (ko) * 2002-08-23 2005-01-29 삼성전자주식회사 분할된 시스템 데이터 버스에 연결되는 메모리 모듈을구비하는 반도체 메모리 시스템
JP3742051B2 (ja) * 2002-10-31 2006-02-01 エルピーダメモリ株式会社 メモリモジュール、メモリチップ、及びメモリシステム
JP4430343B2 (ja) * 2003-06-26 2010-03-10 株式会社日立製作所 メモリモジュールおよびバスシステム
US20060036826A1 (en) * 2004-07-30 2006-02-16 International Business Machines Corporation System, method and storage medium for providing a bus speed multiplier
US7966446B2 (en) * 2005-09-12 2011-06-21 Samsung Electronics Co., Ltd. Memory system and method having point-to-point link

Also Published As

Publication number Publication date
JP2007164787A (ja) 2007-06-28
JP5165233B2 (ja) 2013-03-21

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
R016 Response to examination communication
R002 Refusal decision in examination/registration proceedings
R003 Refusal decision now final
R003 Refusal decision now final

Effective date: 20150103