CN204834058U - Falling edge triggers delay counter - Google Patents

Abstract

The utility model relates to a falling edge triggers delay counter, including delta fb feedback delay circuit, input counter, output counter and FIFO, the input counter is used for counting the the input/output pointer to the clk_fb's of delta fb feedback delay circuit output falling edge. For the limited technical problem of antinoise ability who solves current DRAM memory, the utility model discloses utilize clk_fb's the inside read instruction of falling edge sampling, ts=Th=0.5Tck so, its size changes and changes along with the system clock to realize antinoise ability maximize.

Description

Negative edge trigger delay counter

Technical field

The utility model and relate to semiconductor DRAM memory design field, is specifically related to a kind of negative edge trigger delay counter.

Background technology

Computing machine and various electronic equipment are widely used in the various aspects of the modern life, increasing to memory article (DRAM storer) demand.People are more and more faster to rate request, and the clock of storer is just more and more less.So the impact of noise on properties of product is increasing.The delay counter that the negative edge that the utility model proposes triggers can the impact of maximum stress release treatment.

Computing machine and various electronic equipment are widely used in the various aspects of the modern life, increasing to memory article (DRAM storer) demand.People are more and more faster to rate request, and the clock of storer is just more and more less.So the impact of noise on properties of product is increasing.

The delay counter of storer is used to realize the instruction of reading of storer.Whenever one is read instruction, the rising edge clock after user is desirably in a fixed delay period (user can configure) obtains the data expected, as shown in Figure 1, the user configured prolongation cycle is 6.

In order to realize read operation, DRAM storer generally divides 3 steps to complete:

StepA: storer accepts outside and reads instruction, produce internal clocking (clk_rcv), the delay of internal clocking and external clock clk rising edge is δ 0;

StepB: utilize internal clock rising edge to count

StepC: terminate to export data at counter is δ 1 from edge internal clocking to the data effective time

As shown in Figure 2,2 apparent problems are had:

1, export data to align with external clock;

2, along with the clock period is more and more less, internal latency (δ 0+ δ 1) is likely greater than a clock period, as Fig. 2 data likely occur 5/6/7... clock period

In order to solve the problem, digital delay phase-locked loop DLL introduced by DRAM storer, produce a delayed clock clk_dll of clk_rcv rising edge, along shifting to an earlier date δ 1 than the phase place of external clock clk on delayed clock clk_dll, as shown in Figure 3, if the delay δ dll=N*Tck-(δ 0+ δ 1) of the delayed clock clk_dll that digital delay phase-locked loop DLL produces and internal clocking clk_rcv, the data exported by edge on delayed clock clk_dll like this and external clock just can complete matchings.

As shown in Figure 4, if fb=δ 0+ δ 1, so clk_fb and clk_rcv phase place is with regard to complete matching.

DRAM delay counter utilizes δ fb delay circuit to produce a hold signal and is used for ensureing the sequential relationship of output pointer to input pointer.After user sets DRAM delay period, hold signal periodically will occur ensureing that the change output pointer (outputpointer) along with voltage/temperature/technique can not mistake to the phase relation of input pointer (inputpointer), as shown in Figure 5.

Traditional delay counter uses a fixed delay on the upper edge of clk_fb (output of clk_dll after δ fb delay circuit) to go sampling to read instruction.As shown in Figure 6.

Clk_fb_ δ is that the fixed delay of clk_fb is used for sampling internal and reads instruction (after DRAM receptacle read instruction).In order to correctly sample clk_fb_ δ and inner read instruction and must ensure Ts and retention time Th, Ts+Th=clock period enough Times Created.So the delay of clk_fb_ δ and clk_fb determines Ts.The size of Ts can not change along with clock frequency, and DRAM storer is in order to reach high frequency requirements, and the value of Ts is determined by the highest design frequency, generally equals 0.5* minimum clock cycle.

Like this when low frequency applications, due to Time Created, the constant noise of system that causes of size of Ts can not be excessive.If reservoir designs minimum clock cycle is 1ns, so in low frequency applications such as 10ns occasion, maximum noise still must be less than 0.5*1ns, thus causes the noise resisting ability of DRAM storer to be restricted greatly.

Summary of the invention

In order to the technical matters that the noise resisting ability solving existing DRAM storer is limited, the utility model provides a kind of negative edge trigger delay counter.

Technical solution of the present utility model:

A kind of negative edge trigger delay counter, comprise δ fb feedback delay circuit, enter counter, output counter and FIFO, its special character is: described enter counter is used for counting the negative edge of the clk_fb that δ fb feedback delay circuit exports, export input pointer to FIFO, the input termination delayed clock clk_dll of described output counter, the output terminal of described output counter is connected with FIFO.

Above-mentioned δ fb feedback delay circuit is used for carrying out process to delayed clock clk_dll and produces hold signal.

The advantage that the utility model has:

The utility model utilizes the negative edge sampling internal of clk_fb to read instruction, so Ts=Th=0.5*Tck, and its size changes along with system clock change, thus realizes noise resisting ability maximization.

Accompanying drawing explanation

Fig. 1 is DRAM memory read instructions operation chart;

Fig. 2 is for reading Command Resolution schematic diagram;

Fig. 3 is for reading Command Resolution figure bis-;

Fig. 4 is DLL basic principle schematic;

Fig. 5 is the basic schematic diagram of delay counter;

Fig. 6 is that instruction is read in the sampling of traditional delay counter;

Fig. 7 is negative edge delay counter operating diagram;

Fig. 8 is negative edge delay counter structural representation.

Embodiment

Clk_fb_ δ is that the fixed delay of clk_fb is used for sampling internal and reads instruction.In order to correctly sample clk_fb_ δ and inner read instruction and must ensure Ts and retention time Th, Ts+Th=clock period enough Times Created.So the delay of clk_fb_ δ and clk_fb determines Ts.The size of Ts can not change along with clock frequency, and DRAM storer is in order to reach high frequency requirements, and the value of Ts is determined by the highest design frequency, generally equals 0.5* minimum clock cycle.

As shown in Figure 8, the utility model proposes and utilize the negative edge sampling internal of clk_fb to read instruction.As shown in Figure 7.The negative edge sampling internal of clk_fb is utilized to read instruction, so Ts=Th=0.5*Tck.Its size changes along with system clock change.Thus realize noise resisting ability maximization.δ fb feedback delay circuit produces hold signal for generation of for carrying out process to delayed clock clk_dll.

A kind of negative edge trigger delay method of counting, comprises the following steps:

1] delay clock signals is through fb feedback delay circuit delay output signal clk_fb;

2] counter of enter counter to signal clk_fb counts, and exports input pointer;

3] export through FIFO and read instruction after delay counter.

Claims (2)

1. a negative edge trigger delay counter, comprise δ fb feedback delay circuit, enter counter, output counter and FIFO, it is characterized in that: described enter counter is used for counting the negative edge of the clk_fb that δ fb feedback delay circuit exports, export input pointer to FIFO, the input termination delayed clock clk_dll of described output counter, the output terminal of described output counter is connected with FIFO.

2. negative edge trigger delay counter according to claim 1, is characterized in that: described δ fb feedback delay circuit is used for carrying out process to delayed clock clk_dll and produces hold signal.