CN103684473A - High-speed serial-parallel conversion circuit based on FPGA - Google Patents
High-speed serial-parallel conversion circuit based on FPGA Download PDFInfo
- Publication number
- CN103684473A CN103684473A CN201310685028.9A CN201310685028A CN103684473A CN 103684473 A CN103684473 A CN 103684473A CN 201310685028 A CN201310685028 A CN 201310685028A CN 103684473 A CN103684473 A CN 103684473A
- Authority
- CN
- China
- Prior art keywords
- multistage
- fpga
- type flip
- time delay
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The invention discloses a high-speed serial-parallel conversion circuit based on an FPGA. Under a low-speed clock, high-speed serial digital signals pass through a multi-level delaying tapping device and a multi-level receiving storage based on the FPGA and then are collected in one cycle, and multi-bit digital signals are output in parallel. The high-speed serial-parallel conversion circuit is achieved through the FPGA, serial-parallel conversion processing on the high-speed digital signals can be completed through a low-speed digital circuit, system cost is lowered, circuit designing is simplified, and high cost performance is achieved.
Description
Technical field
The invention belongs to a kind of signal serial-parallel conversion circuit, particularly a kind of high-speed digital signal serial-parallel conversion circuit based on FPGA.
Background technology
Digital signal serial-parallel conversion circuit is the important component part in electronic information and communication aspects application, is widely used in the numerous areas such as national defence, space flight, remote sensing.Conventionally the string the conversion chip that in each field, use, as 74hc595,74hc166 etc., because structure is fixed, kind is comparatively single, causes its range of application to be restricted.
In prior art, if independently build serial-parallel conversion circuit, often have design underaction, cost is higher, realizes the shortcomings such as complicated.
Summary of the invention
The object of the invention is to propose a kind of method of under low-speed clock, high-speed digital signal being gone here and there and being changed, by FPGA design circuit, make high-speed digital signal within the clock cycle, carry out parallel output after repeatedly time delay, the transformation from serial to parallel of low-speed clock being realized to high-speed digital signal becomes possibility.
The technical solution that realizes the object of the invention is: a kind of high speed serial parallel exchange circuit based on FPGA, by multistage time delay tap device and multistage reception memorizer two parts, formed, multistage time delay tap device is composed in series by a plurality of delay units, and multistage reception memorizer is comprised of a plurality of d type flip flops; High-speed digital signal is inputted to multistage time delay tap device and export multistage time delayed signal, then time delayed signals difference correspondences at different levels are inputted the d type flip flop of multistage reception memorizer, when next clock arrives, the signal of current input d type flip flop is stored and exported, realize thus the transformation from serial to parallel of signal in single clock, and continue the digital signal acquiring of next clock cycle.
Described multistage time delay tap device is composed in series by a plurality of delay units, and wherein one end is as input, and digital signal is inputted thus, and each delay unit of process also produces multistage time delay; The output of each delay unit separates a road as the output of multistage time delay tap device, the digital signal through time delays at different levels can be exported in time.
Described multistage reception memorizer is comprised of a plurality of d type flip flops, and the input of each d type flip flop is connected with the output of a delay unit, and quantity is identical with delay unit; Each d type flip flop of the corresponding input of output signal of multistage time delay tap device, a clock cycle of every mistake is exported by the output unification of each d type flip flop.
Described delay unit is realized by FPGA internal searching table, realizes time delay after look-up table.
Described d type flip flop is the elementary cell of FPGA inside, and is controlled by same clock and same reset.
The output end signal of described multistage reception memorizer is the output signal of serial-parallel conversion circuit, for follow-up Digital Signal Processing.
The present invention compared with prior art, its remarkable advantage: circuit provided by the invention is only used FPGA can realize the parallel conversion to high-speed serial signals.This serial-parallel conversion circuit mode similar with other compared, and cost reduces greatly, and has design easily realization and flexibility ratio advantages of higher.
Accompanying drawing explanation
Fig. 1 is the structural representation of high speed serial parallel exchange circuit of the present invention.
Fig. 2 is the concrete structure figure of this high speed serial parallel exchange of the present invention circuit.
Fig. 3 is the basic delay unit schematic diagram of the present invention.
Fig. 4 is d type flip flop schematic diagram of the present invention.
Fig. 5 is the time delay sampling schematic diagram of signal in the clock cycle of the present invention.
Embodiment
The present invention is based on the high speed serial parallel exchange circuit of FPGA, under low-speed clock, high-speed serial digital signal, by after multistage time delay tap device and multistage reception memorizer based on FPGA, can be gathered and parallel output multistation digital signal in one-period.
The present invention is based on the high speed serial parallel exchange circuit of FPGA, it is realized circuit and is comprised of multistage time delay tap device and multistage reception memorizer two parts, and implementation method is as follows:
One, high-speed digital signal enters multistage time delay tap device and exports the signal of multistage time delay;
Two, time delayed signals at different levels are the d type flip flop of the multistage reception memorizer of corresponding input respectively, when next clock arrives, the signal of current input d type flip flop is stored and is exported, and realizes thus the transformation from serial to parallel of signal in single clock.
Described multistage time delay tap device is comprised of the delay unit of a plurality of series connection, and the output of each delay unit separates a road as the output of multistage time delay tap device.
Described multistage reception memorizer is comprised of a plurality of d type flip flops, and the input of each d type flip flop is connected with the output of a delay unit, and quantity is identical with delay unit.
Described delay unit can, by the look-up tables'implementation of FPGA inside, be realized time delay after look-up table.
Described d type flip flop is the elementary cell of FPGA inside, and is controlled by same clock and same reset.
The output of described multistage reception memorizer is the output signal of serial-parallel conversion circuit, for follow-up Digital Signal Processing.
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The invention provides a kind of high speed serial parallel exchange circuit based on FPGA, its implementation structure is comprised of multistage time delay tap device and multistage reception memorizer two parts, as shown in Figure 1.
The concrete structure of high speed serial parallel exchange circuit wherein, as shown in Figure 2, the output of multistage time delay tap device is connected with the input of multistage reception memorizer, and multistage reception memorizer output parallel signal, for follow-up Digital Signal Processing.
Wherein multistage time delay tap device is in series by a plurality of delay units, for making signal produce multistage time delay within a clock cycle; Multistage reception memorizer is comprised of a plurality of d type flip flops, and for receiving and export the signal producing after time delays at different levels, quantity is identical with delay unit, and the output of each delay unit separates a road and is connected with the input of d type flip flop.
Below each several part structure is described in detail:
Delay unit, as shown in Figure 3, by the look-up tables'implementation of FPGA inside, is input as 0 to A0, A1, A2 end, and signal is from the input of A3 end, and time delay after look-up table, from the output of O end.The minimum delay time of signal time delay after look-up table, to realize one-level delay effect, a plurality of delay unit series connection just can realize multistage time delay.The fpga chip of different model, minimum delay time is slightly variant.
D type flip flop, as shown in Figure 4, is FPGA inside elementary cell, and wherein input D is connected with the output of delay unit, and clock end CLK connects same clock signal, and reset key is unified to be connected.When a rising edge clock arrives, d type flip flop is just stored the signal of current input export, to realize the collection to signal.
By placement-and-routing's restriction technique, used look-up table and d type flip flop are arranged in to the position that FPGA is inner adjacent, controlled to realize time delay.
Signal transfers parallel process to by serial, as shown in Figure 5.Signal produces time delay by a delay unit
t, the clock cycle is T, n is delay unit number, the long delay time of signal
t*n should be less than clock cycle T, and n should get and be less than T/
the positive integer of t.Like this high-speed serial signals can be when unit clock cycle T finishes a parallel output n digital signal, for completing follow-up Digital Signal Processing.
Through experiment, when systematic sampling frequency is 100MHz, when delay unit time delay is 0.1ns, clock cycle T is 10ns, and delay unit n should be less than 10/0.1=100.Choosing n is 99, can be within a clock cycle 99 digital signals of parallel output, sample frequency is equivalent to original 99 times and approaches 10GHz, has realized string the conversion of high-speed digital signal.
Claims (6)
1. the high speed serial parallel exchange circuit based on FPGA, is characterized in that: multistage time delay tap device and multistage reception memorizer two parts, consist of, multistage time delay tap device is composed in series by a plurality of delay units, and multistage reception memorizer is comprised of a plurality of d type flip flops; High-speed digital signal is inputted to multistage time delay tap device and export multistage time delayed signal, then time delayed signals difference correspondences at different levels are inputted the d type flip flop of multistage reception memorizer, when next clock arrives, the signal of current input d type flip flop is stored and exported, realize thus the transformation from serial to parallel of signal in single clock, and continue the digital signal acquiring of next clock cycle.
2. the high speed serial parallel exchange circuit based on FPGA according to claim 1, it is characterized in that: described multistage time delay tap device is composed in series by a plurality of delay units, wherein one end is as input, and digital signal is inputted thus, and each delay unit of process also produces multistage time delay; The output of each delay unit separates a road as the output of multistage time delay tap device, the digital signal through time delays at different levels can be exported in time.
3. the high speed serial parallel exchange circuit based on FPGA according to claim 1, it is characterized in that: described multistage reception memorizer is comprised of a plurality of d type flip flops, the input of each d type flip flop is connected with the output of a delay unit, and quantity is identical with delay unit; Each d type flip flop of the corresponding input of output signal of multistage time delay tap device, a clock cycle of every mistake is exported by the output unification of each d type flip flop.
4. the high speed serial parallel exchange circuit based on FPGA according to claim 1 and 2, is characterized in that: described delay unit is realized by FPGA internal searching table, realizes time delay after look-up table.
5. according to the high speed serial parallel exchange circuit based on FPGA described in claim 1 or 3, it is characterized in that: described d type flip flop is the elementary cell of FPGA inside, and controlled by same clock and same reset.
6. the high speed serial parallel exchange circuit based on FPGA according to claim 1, is characterized in that: the output end signal of described multistage reception memorizer is the output signal of serial-parallel conversion circuit, for follow-up Digital Signal Processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310685028.9A CN103684473A (en) | 2013-12-13 | 2013-12-13 | High-speed serial-parallel conversion circuit based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310685028.9A CN103684473A (en) | 2013-12-13 | 2013-12-13 | High-speed serial-parallel conversion circuit based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103684473A true CN103684473A (en) | 2014-03-26 |
Family
ID=50320927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310685028.9A Pending CN103684473A (en) | 2013-12-13 | 2013-12-13 | High-speed serial-parallel conversion circuit based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103684473A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104660334A (en) * | 2015-01-16 | 2015-05-27 | 电子科技大学 | Serial-to-parallel optical converter with high port number enlarging convenience |
| CN107222219A (en) * | 2017-06-28 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | Possesses the high speed serial parallel exchange circuit of frame alignment function |
| CN112199921A (en) * | 2020-12-07 | 2021-01-08 | 南京集成电路设计服务产业创新中心有限公司 | Data path layout method based on analytic layout algorithm |
-
2013
- 2013-12-13 CN CN201310685028.9A patent/CN103684473A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104660334A (en) * | 2015-01-16 | 2015-05-27 | 电子科技大学 | Serial-to-parallel optical converter with high port number enlarging convenience |
| CN104660334B (en) * | 2015-01-16 | 2017-02-22 | 电子科技大学 | Serial-to-parallel optical converter with high port number enlarging convenience |
| CN107222219A (en) * | 2017-06-28 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | Possesses the high speed serial parallel exchange circuit of frame alignment function |
| CN112199921A (en) * | 2020-12-07 | 2021-01-08 | 南京集成电路设计服务产业创新中心有限公司 | Data path layout method based on analytic layout algorithm |
| CN112199921B (en) * | 2020-12-07 | 2021-02-19 | 南京集成电路设计服务产业创新中心有限公司 | Data path layout method based on analytic layout algorithm |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103888147B (en) | A kind of transformation from serial to parallel change-over circuit and converter and converting system | |
| CN104378114A (en) | Method for achieving synchronization of multichannel analog-digital converter | |
| CN108736897B (en) | Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip | |
| US9054941B2 (en) | Clock and data recovery using dual manchester encoded data streams | |
| CN102968513B (en) | A kind of high-speed digital signal gather and analysis method based on FPGA | |
| CN104617926B (en) | A kind of swallow pulse formula clock synchronization circuit | |
| CN102437852A (en) | Realization of 2.5 GSa/s data collection circuit by utilizing low speed ADC and method thereof | |
| CN105306068A (en) | Parallel-serial conversion circuit based on clock phase modulation | |
| CN102353891A (en) | Digital integrated circuit fundamental tester | |
| CN103297037A (en) | Multi-mode frequency divider based on modularization | |
| CN102611447A (en) | Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array) | |
| CN103676742A (en) | Data reconstitution method based on FPGA | |
| CN104283561B (en) | A kind of asynchronous clock parallel-serial conversion half period output circuit | |
| CN103684473A (en) | High-speed serial-parallel conversion circuit based on FPGA | |
| CN102843127B (en) | For the numerical data related method thereof that prompt varying signal controls | |
| CN103684423A (en) | Variable synchronous clock frequency division circuit | |
| CN105306058A (en) | High-speed digital signal acquisition system based on clock phase modulation | |
| CN105245235A (en) | Serial-to-parallel conversion circuit based on clock phase modulation | |
| CN104184456A (en) | Low-frequency multiphase differential clock tree type serializer with high speed and low power consumption for IO interface | |
| CN104714774A (en) | True random number generation method based on digital circuit | |
| CN103247323B (en) | A kind of serial interface flash memory | |
| CN202586998U (en) | Synchronous clock extraction device for noise-added signal based on FPGA (field programmable gate array) | |
| CN203368439U (en) | Pulse-width self-adaptive single bus receiver | |
| CN104348468A (en) | Pulse width self-adaptive single-bus receiver | |
| CN103795402A (en) | Synchronous frequency dividing circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140326 |