CN108347245B - Clock frequency divider - Google Patents
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- CN108347245B CN108347245B CN201810191560.8A CN201810191560A CN108347245B CN 108347245 B CN108347245 B CN 108347245B CN 201810191560 A CN201810191560 A CN 201810191560A CN 108347245 B CN108347245 B CN 108347245B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
- H03K23/44—Out-of-phase gating or clocking signals applied to counter stages using field-effect transistors
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Abstract
The invention discloses a clock frequency divider, which comprises a control signal generation module and a frequency division signal generation module; the control signal generation module is used for receiving an input clock signal and a frequency division parameter, generating a control signal corresponding to the input clock signal according to the frequency division parameter, and then sending the control signal to the frequency division signal generation module; the frequency division signal generating module is used for receiving an input clock signal and generating a sampling clock signal corresponding to the input clock signal according to a received control signal; and the starting clock edge of the clock period corresponding to the sampling clock signal synchronously changes along with the starting clock edge of the clock period corresponding to the input clock signal. The invention ensures that the corresponding sampling edge of the sampling clock signal generated by frequency division still has better clock jitter performance when the sampling clock signal is used as the sampling clock, and greatly weakens the restriction of the clock jitter performance of the sampling clock edge on the dynamic performance of the analog-to-digital converter when the analog-to-digital converter samples the high-intermediate frequency signal.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a clock frequency divider.
Background
With the rapid development of modern communication systems, the sampling rate and resolution of the analog-to-digital converter are also increasingly required. As the bandwidth of the sampled signal is wider and the frequency of the sampled signal is faster and faster, the clock jitter performance of the sampling clock has a greater influence on the dynamic performance (such as the signal-to-noise ratio) of the analog-to-digital converter, and therefore, the improvement of the signal-to-noise ratio of the analog-to-digital converter is greatly restricted by the clock jitter performance of the sampling clock.
In the prior art, for the convenience of system application, clock signals with the same frequency are often sent to each circuit module of the system. Specifically, the internal sampling clock of the analog-to-digital converter is generated by dividing the frequency of the input clock signal by using a conventional CMOS (Complementary Metal Oxide Semiconductor) clock divider; in this frequency division processing method, even though the clock jitter performance of the input clock is good, the clock jitter performance of the generated output clock is poor, and therefore, the improvement of the dynamic performance when the high-speed and high-precision analog-to-digital converter samples the high-frequency signal and the intermediate-frequency signal is severely restricted.
Disclosure of Invention
The invention aims to overcome the defects that in the prior art, the analog-to-digital converter adopts the traditional CMOS clock frequency divider to carry out frequency division processing on a clock signal, the clock jitter performance of an output clock is poor, and the improvement of the dynamic performance of the high-speed and high-precision analog-to-digital converter during sampling of a high-frequency signal and a medium-frequency signal is seriously restricted, and provides a clock frequency divider.
The invention solves the technical problems through the following technical scheme:
the invention provides a clock frequency divider, which comprises a control signal generation module and a frequency division signal generation module;
the control signal generation module is used for receiving an input clock signal and a frequency division parameter, generating a control signal corresponding to the input clock signal according to the frequency division parameter, and then sending the control signal to the frequency division signal generation module;
the frequency division signal generating module is used for receiving the input clock signal and generating a sampling clock signal corresponding to the input clock signal according to the received control signal;
and the starting clock edge of the clock period corresponding to the sampling clock signal synchronously changes along with the starting clock edge of the clock period corresponding to the input clock signal.
Preferably, the control signal generating module is further configured to receive a first clock signal that is inverted with respect to the input clock signal.
Preferably, the clock divider further comprises a first not gate;
the first not gate is electrically connected with the control signal generation module and is used for performing phase inversion processing on the input clock signal to obtain the first clock signal.
Preferably, the control signal generating module comprises a counter and an end-of-cycle detecting circuit;
the counter is used for outputting a count value and sending the count value to the cycle end detection circuit;
the cycle end detection circuit is used for receiving the input clock signal and generating the control signal according to the input clock signal and the count value;
the control signal comprises a first control signal and a second control signal, and the first control signal and the second control signal are in the same clock cycle.
Preferably, the counter comprises at least one flip-flop cell;
the trigger unit comprises a first D trigger (a type of trigger) with a set and reset function, a NAND gate, an OR gate and a second NOT gate;
one input end of the NAND gate is electrically connected with one input end of the OR gate, and the output end of the NAND gate is electrically connected with the set end of the first D flip-flop;
the other input end of the OR gate is electrically connected with the output end of the second NOT gate, and the output end of the OR gate is electrically connected with the reset end of the first D flip-flop;
and the clock input end of the first D trigger is electrically connected with the output end of the first NOT gate, and the output end of the first D trigger is electrically connected with the cycle end detection circuit.
Preferably, the end-of-cycle detection circuit includes a nor gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a second D flip-flop and a third D flip-flop;
the output end of each first D trigger is respectively and electrically connected with a different input end of the NOR gate;
the output end of the NOR gate is electrically connected with the input end of the second D flip-flop;
the output end of the second D trigger is electrically connected with the input end of the fifth NOT gate and the input end of the third D trigger respectively;
the input end of the third not gate is electrically connected with the output end of the first not gate, and the output end of the third not gate is respectively electrically connected with the clock input end of the second D flip-flop and the input end of the fourth not gate;
the output end of the fourth NOT gate is electrically connected with the clock input end of the third D trigger;
the output end of the third D trigger is electrically connected with the input end of the sixth NOT gate;
the output end of the fifth not gate and the output end of the sixth not gate are both electrically connected with the frequency division signal generating module;
wherein an output terminal of the fifth not gate outputs the first control signal, and an output terminal of the sixth not gate outputs the second control signal;
and the output end of the fifth NOT gate is respectively and electrically connected with the other input end of the NAND gate and the input end of the second NOT gate.
Preferably, when the count value satisfies a first set count value, the first control signal and the second control signal output by the end-of-period detection circuit control the divided-frequency signal generation module to output the sampling clock signal that synchronously changes along a start clock edge of a clock period corresponding to the input clock signal;
when the count value meets a second set count value, the frequency division signal generation module outputs a fixed clock period signal;
wherein a clock period of the fixed clock period signal is the same as a clock period of the input clock signal.
Preferably, the frequency division signal generating module includes a first PMOS (Metal Oxide Semiconductor field effect transistor), a second PMOS, a third PMOS, a first NMOS (N-Metal Oxide Semiconductor) transistor, a second NMOS, and a third NMOS;
the grid electrode of the first PMOS tube is electrically connected with the output end of the fifth NOT gate, the source electrode of the first PMOS tube is electrically connected with a power supply end, and the drain electrode of the first PMOS tube is electrically connected with the source electrode of the second PMOS tube;
the grid electrode of the second PMOS tube is electrically connected with the clock signal input port, and the drain electrode of the second PMOS tube is respectively electrically connected with the drain electrode of the third PMOS tube, the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube;
the grid electrode of the third PMOS tube is electrically connected with the output end of the sixth NOT gate, and the source electrode of the third PMOS tube is electrically connected with the power supply end;
the drain electrode of the third PMOS tube is also electrically connected with the clock signal output port;
the grid electrode of the first NMOS tube is electrically connected with the clock signal input port, and the source electrode of the first NMOS tube is electrically connected with the source electrode of the second NMOS tube and the drain electrode of the third NMOS tube respectively;
the grid electrode of the second NMOS tube is electrically connected with the output end of the fifth NOT gate;
the grid electrode of the third NMOS tube is electrically connected with the output end of the sixth NOT gate, and the source electrode of the third NMOS tube is grounded.
Preferably, the initial falling edge of the clock cycle corresponding to the sampling clock signal changes synchronously with the initial rising edge of the clock cycle corresponding to the input clock signal; or, the initial rising edge of the clock period corresponding to the sampling clock signal changes synchronously with the initial falling edge of the clock period corresponding to the input clock signal.
The positive progress effects of the invention are as follows:
the invention generates the sampling clock signal used for sampling after frequency division by respectively processing the clock edge of the input clock signal needing clock jitter performance optimization through the matching of the control signal generating module and the frequency division signal generating module, and the clock jitter additionally added in the processing process is very small, thereby ensuring that the corresponding clock edge of the sampling clock signal generated by frequency division still has better clock jitter performance when the sampling clock signal is used as the sampling clock, greatly reducing the restriction of the clock jitter performance of the sampling clock edge on the dynamic performance of the analog-to-digital converter when the analog-to-digital converter samples high and intermediate frequency signals, and optimizing the dynamic performance of the existing analog-to-digital converter when the analog-to-digital converter samples high and intermediate frequency signals.
Drawings
FIG. 1 is a block diagram of a clock divider according to a preferred embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a control signal generating module of the clock divider according to the preferred embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of an end-of-cycle detection circuit of the clock divider according to the preferred embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a divided signal generating module of the clock divider according to the preferred embodiment of the present invention;
fig. 5 is a schematic diagram of a clock divider according to a preferred embodiment of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
As shown in fig. 1, the clock divider of the present embodiment includes a first not gate 1, a control signal generation block 2, and a divided signal generation block 3.
The control signal generating module 2 is configured to receive a first clock signal that is inverted with respect to the input clock signal.
Specifically, the first not gate 1 is electrically connected to the control signal generating module 2, and is configured to perform inverse processing on an input clock signal to obtain a first clock signal.
The control signal generation module 2 is further configured to receive the input clock signal and the frequency division parameter, generate a control signal corresponding to the input clock signal according to the frequency division parameter, and then send the control signal to the frequency division signal generation module 3;
the frequency division signal generating module 3 is configured to receive an input clock signal and generate a sampling clock signal corresponding to the input clock signal according to a received control signal.
And the starting clock edge of the clock period corresponding to the sampling clock signal synchronously changes along with the starting clock edge of the clock period corresponding to the input clock signal.
In addition, only the rising or falling edge of the clock signal is generally used as the sampling clock edge in sampling systems. The clock divider of this embodiment uses the falling edge of the input clock signal as the sampling clock edge that needs the clock jitter performance optimization when sampling the clock. The rising edge of the input clock signal may also be used as the clock edge that needs the clock jitter performance optimization, and then the falling edge of the sampling clock signal is used as the sampling clock edge of the sampling system, and the clock jitter performance optimization process corresponding to this case is not described here again.
In this embodiment, the falling edge of the input clock signal is used as the clock edge for optimizing the clock jitter performance, and the input clock signal is divided into the clock signal for generating the control signal and the clock signal for generating the frequency division signal, instead of directly driving the two modules, i.e., the control signal generating module 2 and the frequency division signal generating module 3, by the input clock signal, so that the driving load of the input clock signal is reduced, the deterioration of the clock jitter performance of the falling edge of the input clock signal by the load is reduced, and the clock jitter performance of the falling edge of the input clock signal is improved.
The control signal generation block 2 includes a counter 21 and an end-of-period detection circuit 22.
As shown in fig. 2, the counter 21 is configured to output a count value and send the count value to the end-of-period detection circuit 22.
The end-of-cycle detection circuit 22 is configured to receive an input clock signal and generate a control signal according to the input clock signal and a count value;
the control signal comprises a first control signal and a second control signal, and the first control signal and the second control signal are in the same clock cycle.
When the count value meets the first set count value, the first control signal and the second control signal output by the cycle end detection circuit 22 control the frequency division signal generation module 3 to output a sampling clock signal which synchronously changes along with the initial clock edge of the clock cycle corresponding to the input clock signal;
when the count value meets a second set count value, the frequency division signal generation module 3 outputs a fixed clock period signal;
wherein the clock period of the fixed clock period signal is the same as the clock period of the input clock signal.
Specifically, the counter 21 includes at least one flip-flop unit 211. The counter 21 is a programmable counter implementing an arbitrary division ratio of the clock divider. The general counter includes a plurality of flip-flop units 211, and preferably, as shown in fig. 2, the number of flip-flop units 211 is 3, and the achievable frequency division ratio is 1-8.
The flip-flop unit 211 includes a first D flip-flop 2111 having set and reset functions, a nand gate 2112, an or gate 2113, and a second not gate 2114;
an input end of the nand gate 2112 is electrically connected with an input end of the or gate 2113, and an output end of the nand gate 2112 is electrically connected with a set end of the first D flip-flop 2111;
the other input terminal of the or gate 2113 is electrically connected to the output terminal of the second not gate 2114, and the output terminal of the or gate 2113 is electrically connected to the reset terminal of the first D flip-flop 2111;
a clock input terminal of the first D flip-flop 2111 is electrically connected to an output terminal of the first not gate 1, and an output terminal of the first D flip-flop 2111 is electrically connected to the end-of-cycle detection circuit 22.
The end-of-cycle detection circuit 22 is configured to receive the input clock signal and generate a first control signal s1 and a second control signal s2 according to the input clock signal and the count value.
As shown in fig. 3, specifically, the end-of-cycle detection circuit 22 includes a nor gate 221, a third not gate 222, a fourth not gate 223, a fifth not gate 224, a sixth not gate 225, a second D flip-flop 226, and a third D flip-flop 227.
The output of each first D flip-flop 2111 is electrically connected to a different input of the or-nor gate 221. As shown in fig. 3, the output terminals a, b, c of the three first D flip-flops 2111 are electrically connected to a different input terminal of the or-and gate 221, respectively.
The output terminal of the nor gate 221 is electrically connected to the input terminal of the second D flip-flop 226;
the output terminal of the second D flip-flop 226 is electrically connected to the input terminal of the fifth not gate 224 and the input terminal of the third D flip-flop 227, respectively;
an input terminal of the third not gate 222 is electrically connected to an output terminal of the first not gate 1, and output terminals of the third not gate 222 are electrically connected to a clock input terminal of the second D flip-flop 226 and an input terminal of the fourth not gate 223, respectively.
The output terminal of the fourth not gate 223 is electrically connected to the clock input terminal of the third D flip-flop 227;
an output terminal of the third D flip-flop 227 is electrically connected to an input terminal of the sixth not gate 225;
the output end of the fifth not gate 224 and the output end of the sixth not gate 225 are both electrically connected with the frequency division signal generating module 3;
wherein, the output terminal of the fifth not gate 224 outputs the first control signal s1, and the output terminal of the sixth not gate 225 outputs the second control signal s 2;
the output end of the fifth not gate 224 is electrically connected to the other input end of the nand gate 2112 and the input end of the second not gate 2114, respectively.
As shown in FIG. 2, the frequency division ratio of the clock frequency divider is 1 ~ 8, and the output value of the counter 21 is counted down from 2 to 0 in cycles, taking the configuration as an example of frequency division by three.
As shown in fig. 4, in addition, the frequency division signal generating module 3 includes a first PMOS transistor 31, a second PMOS transistor 32, a third PMOS transistor 33, a first NMOS transistor 34, a second NMOS transistor 35, and a third NMOS transistor 36.
The gate of the first PMOS transistor 31 is electrically connected to the output terminal of the fifth not gate 224, the source of the first PMOS transistor 31 is electrically connected to the power supply terminal, and the drain of the first PMOS transistor 31 is electrically connected to the source of the second PMOS transistor 32;
the grid electrode of the second PMOS transistor 32 is electrically connected with the clock signal input port, and the drain electrode of the second PMOS transistor 32 is electrically connected with the drain electrode of the third PMOS transistor 33, the drain electrode of the first NMOS transistor 34 and the drain electrode of the second NMOS transistor 35 respectively;
the gate of the third PMOS transistor 33 is electrically connected to the output terminal of the sixth not gate 225, and the source of the third PMOS transistor 33 is electrically connected to the power supply terminal;
the drain electrode of the third PMOS transistor 33 is also electrically connected to the clock signal output port 5;
the grid electrode of the first NMOS transistor 34 is electrically connected to the clock signal input port 1, and the source electrode of the first NMOS transistor 34 is electrically connected to the source electrode of the second NMOS transistor 35 and the drain electrode of the third NMOS56, respectively;
the gate of the second NMOS transistor 35 is electrically connected to the output terminal of the fifth not gate 224;
the gate of the third NMOS transistor 36 is electrically connected to the output terminal of the sixth not gate 225, and the source of the third NMOS transistor 36 is grounded.
Specifically, as shown in fig. 1, the input clock signal is an input signal of a logic gate in the divided signal generating block 3, and the first control signal s1 and the second control signal s0 are two control signals of the logic gate in the divided signal generating block 3;
in the present embodiment, as shown in fig. 4, when s1 is 0 and s0 is 1, the logic gate in the divided signal generation block 3 is opened, the falling edge of the input clock signal generates the rising edge of the divided output sampling clock signal ckout via the logic gate of the divided signal generation block 3, and the rising edge of the divided output sampling clock signal ckout is used as the sampling clock edge of the sampling system. Since the falling edge of ckin in this embodiment is the clock edge with optimized clock jitter performance, the clock jitter performance of the rising edge of ckout generated directly by the simple logic gate in reverse is still better.
As shown in fig. 5, a waveform diagram of the input clock signal ckin, a waveform diagram of the first clock signal ck1, a timing cycle diagram of the counter 21, an output waveform diagram of the nor gate 221, a waveform diagram of the first control signal s1, a waveform diagram of the second control signal s2, and the sampling clock signal ckout are shown, respectively.
When the count of the counter 21 is 0 in each counting period, the end-of-period detection module 32 generates a valid reload signal at the falling edge of the first clock signal ck1, specifically, the reload signal is at a high level in the present embodiment, and the reload signal continues to output a high level for one clock period corresponding to the input clock signal; the reload signal is a reload signal, and the set and reset signals of each first D flip-flop 2111 in the counter 21 are generated in cooperation with the frequency division ratio setting parameter div <2:0>, so that the start value of the counter 21 in a new counting period is set.
The reverse processing is performed on the reload signal, the first control signal s1 generates a low level and continues inputting a clock cycle corresponding to the clock signal, s0 is generated at the rising edge of the next clock cycle when the reload signal becomes a high level, the generated low level of s0 also continues for a clock cycle, and after the reload signal becomes a high level, the asynchronous setting/resetting is performed on the second D flip-flop 226 and/or the third D flip-flop 227 which form the counter 21, so that the output q <2:0> of the counter 21 is updated to a value equal to div <2:0>, and the counter 21 enters the next counting cycle.
As shown in fig. 2, q <2:0> represents the outputs of the three first D flip-flops 2111 in the counter 21 and is represented by a, b, and c, q <2> corresponds to c in fig. 2, q <1> corresponds to b in fig. 2, and q <0> corresponds to a in fig. 2.
div <2:0> is a frequency division ratio setting parameter, which is a three-digit binary number, and is used to set the frequency division ratio to be the binary number plus one, for example, when div <2:0> is 011, it corresponds to decimal number 3, and at this time, the frequency division ratio is set to 4.
The delay td1 and td2 generated in the first control signal s1 and the second control signal s0 are offset by the frequency division signal generating module 3, so as to obtain the rising edge of the sampling clock signal ckout consistent with the falling edge of the output input clock signal, optimize the clock jitter performance of the falling edge of the input clock signal, ensure that the sampling edge corresponding to the sampling clock signal generated by frequency division still has better clock jitter performance when the sampling clock signal is used as a sampling clock, and greatly weaken the restriction of the clock jitter performance of the sampling clock edge on the dynamic performance of the analog-to-digital converter when the analog-to-digital converter samples high and intermediate frequency signals.
In addition, when s1 and s0 satisfy other conditions, the logic gate in the divided signal generating block 3 has a fixed output, so that the high level of the divided output sampling clock signal ckout lasts for one clock cycle of the input clock signal, and the falling edge of the divided output sampling clock signal ckout is independent of the jitter performance of the input clock.
In the embodiment, the rising edge of the input clock signal to be subjected to clock jitter performance optimization is processed by the control signal generation module 2 and the frequency division signal generation module 3 in a matching way, the falling edge used as the sampling clock signal after frequency division is generated, and additionally increased clock jitter in the processing process is very small, so that the sampling edge corresponding to the sampling clock signal generated by frequency division still has good clock jitter performance when the sampling clock signal is used as the sampling clock, the restriction of the clock jitter performance of the sampling clock edge on the dynamic performance of the analog-to-digital converter when the analog-to-digital converter samples the high-intermediate frequency signal is greatly reduced, and the dynamic performance of the existing analog-to-digital converter when the high-intermediate frequency signal is sampled is optimized.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (3)
1. A clock divider is characterized by comprising a control signal generation module and a frequency division signal generation module;
the control signal generation module is used for receiving an input clock signal and a frequency division parameter, generating a control signal corresponding to the input clock signal according to the frequency division parameter, and then sending the control signal to the frequency division signal generation module;
the frequency division signal generating module is used for receiving the input clock signal and generating a sampling clock signal corresponding to the input clock signal according to the received control signal;
the starting clock edge of the clock period corresponding to the sampling clock signal synchronously changes along with the starting clock edge of the clock period corresponding to the input clock signal;
the control signal generation module is also used for receiving a first clock signal which is opposite in phase to the input clock signal;
the clock divider further comprises a first not gate;
the first NOT gate is electrically connected with the control signal generation module and is used for carrying out reverse phase processing on the input clock signal to obtain a first clock signal;
the control signal generation module comprises a counter and a cycle end detection circuit;
the counter is used for outputting a count value and sending the count value to the cycle end detection circuit;
the cycle end detection circuit is used for receiving the input clock signal and generating the control signal according to the input clock signal and the count value;
the control signal comprises a first control signal and a second control signal, and the first control signal and the second control signal are in the same clock cycle;
the counter comprises at least one trigger unit;
the trigger unit comprises a first D trigger with a set and reset function, a NAND gate, an OR gate and a second NOT gate;
one input end of the NAND gate is electrically connected with one input end of the OR gate, and the output end of the NAND gate is electrically connected with the set end of the first D flip-flop;
the other input end of the OR gate is electrically connected with the output end of the second NOT gate, and the output end of the OR gate is electrically connected with the reset end of the first D flip-flop;
the clock input end of the first D trigger is electrically connected with the output end of the first NOT gate, and the output end of the first D trigger is electrically connected with the cycle end detection circuit;
the cycle end detection circuit comprises a NOR gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a second D trigger and a third D trigger;
the output end of each first D trigger is respectively and electrically connected with a different input end of the NOR gate;
the output end of the NOR gate is electrically connected with the input end of the second D flip-flop;
the output end of the second D trigger is electrically connected with the input end of the fifth NOT gate and the input end of the third D trigger respectively;
the input end of the third not gate is electrically connected with the output end of the first not gate, and the output end of the third not gate is respectively electrically connected with the clock input end of the second D flip-flop and the input end of the fourth not gate;
the output end of the fourth NOT gate is electrically connected with the clock input end of the third D trigger;
the output end of the third D trigger is electrically connected with the input end of the sixth NOT gate;
the output end of the fifth not gate and the output end of the sixth not gate are both electrically connected with the frequency division signal generating module;
wherein an output terminal of the fifth not gate outputs the first control signal, and an output terminal of the sixth not gate outputs the second control signal;
the output end of the fifth not gate is respectively and electrically connected with the other input end of the NAND gate and the input end of the second not gate;
the frequency division signal generating module comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube;
the grid electrode of the first PMOS tube is electrically connected with the output end of the fifth NOT gate, the source electrode of the first PMOS tube is electrically connected with a power supply end, and the drain electrode of the first PMOS tube is electrically connected with the source electrode of the second PMOS tube;
the grid electrode of the second PMOS tube is electrically connected with a clock signal input port, and the drain electrode of the second PMOS tube is respectively electrically connected with the drain electrode of the third PMOS tube, the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube;
the grid electrode of the third PMOS tube is electrically connected with the output end of the sixth NOT gate, and the source electrode of the third PMOS tube is electrically connected with the power supply end;
the drain electrode of the third PMOS tube is also electrically connected with the clock signal output port;
the grid electrode of the first NMOS tube is electrically connected with the clock signal input port, and the source electrode of the first NMOS tube is electrically connected with the source electrode of the second NMOS tube and the drain electrode of the third NMOS tube respectively;
the grid electrode of the second NMOS tube is electrically connected with the output end of the fifth NOT gate;
the grid electrode of the third NMOS tube is electrically connected with the output end of the sixth NOT gate, and the source electrode of the third NMOS tube is grounded.
2. The clock divider according to claim 1, wherein when the count value satisfies a first set count value, the first control signal and the second control signal output by the end-of-cycle detection circuit control the divided-signal generation module to output the sampling clock signal in synchronization with a start clock edge of a clock cycle corresponding to the input clock signal;
when the count value meets a second set count value, the frequency division signal generation module outputs a fixed clock period signal;
wherein a clock period of the fixed clock period signal is the same as a clock period of the input clock signal.
3. The clock divider of claim 1, wherein a starting falling edge of a clock cycle corresponding to the sampling clock signal varies synchronously with a starting rising edge of a clock cycle corresponding to the input clock signal; or, the initial rising edge of the clock period corresponding to the sampling clock signal changes synchronously with the initial falling edge of the clock period corresponding to the input clock signal.
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| CN116844620B (en) * | 2022-03-23 | 2024-05-03 | 长鑫存储技术有限公司 | Signal sampling circuit and semiconductor memory |
| CN115549648A (en) * | 2022-10-09 | 2022-12-30 | 重庆吉芯科技有限公司 | Low-jitter random clock generation circuit |
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