CN103197139A - Clock frequency test method and clock frequency test circuit - Google Patents
Clock frequency test method and clock frequency test circuit Download PDFInfo
- Publication number
- CN103197139A CN103197139A CN2012100044104A CN201210004410A CN103197139A CN 103197139 A CN103197139 A CN 103197139A CN 2012100044104 A CN2012100044104 A CN 2012100044104A CN 201210004410 A CN201210004410 A CN 201210004410A CN 103197139 A CN103197139 A CN 103197139A
- Authority
- CN
- China
- Prior art keywords
- clock
- fast
- clock counter
- counter
- slow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a clock frequency test method. The clock frequency test method includes: dividing a test clock and a tested clock into a fast clock and a slow clock, setting a fast clock counter to carry out counting to the fast clock, setting a slow clock counter to carry out counting to the slow clock; serving a counting interval of the slow clock as a standard counting interval by a counting interval during a test; after the test is started by a system, firstly starting the slow clock counter to carry out counting, after counting is started by the slow clock counter, and then the fast clock counter is started to carry out counting; stopping counting after the slow clock counter is full of memory, and then the fast clock counter is stopped to count; scavenging a test start bit of the system with a signal that the fast clock counter stops counting, reading numerical value of the fast counter, calculating frequencies of the tested clock according to counting values of the fast clock counter, counting values of the slow clock counter and frequencies of a known test clock. The invention further discloses a clock frequency test circuit. Accurate test results can be obtained in limited test time.
Description
Technical field
The present invention relates to a kind of clock rate testing method, the invention still further relates to a kind of clock rate testing circuit.
Background technology
In current chip design, increasing chip internal also uses built-in clock except the clock that uses the interface input.Factors such as process deviation and built-in Clock Generation Circuit error make the deviser that the requirement that built-in clock is tested be arranged.At present, commonplace method of testing is to use interface clock that built-in clock is tested, it is the enabling counting simultaneously of interface clock and built-in clock, calculate the frequency of built-in clock by the count value between certain count block and known interface clock frequency meter, with the frequency of definite built-in clock and the deviation between the design load.Such test circuit is not considered the speed relation between test clock and the tested clock usually, it is the reference count interval that unification is used between the count block of test clock, and directly removes to start respectively the counter of test clock and tested clock with the enabling signal of system.The test error of this test circuit is unit with the cycle of slow clock often, under the widely different situation of test clock and tested clock frequency, can introduce sizable test error, especially under the much lower situation of the frequency of the frequency ratio test clock of tested clock.Sort circuit still can increase the test duration if the reduction test error can only increase between the count block.
Summary of the invention
Technical matters to be solved by this invention provides a kind of clock rate testing method, can obtain more accurate test result in the limited test duration; For this reason, the present invention also will provide a kind of clock rate testing circuit.
For solving the problems of the technologies described above, clock rate testing method of the present invention is to adopt following technical scheme to realize:
Step 3, slow clock counter stop counting after writing all over, and then stop fast clock counter counting;
The test starting position of step 4, the signal removal system that stops to count with fast clock counter, read the numerical value of fast clock counter, according to the frequency of the tested clock of frequency computation part of the count value of the count value of fast clock counter, slow clock counter and known test clock.
Described clock rate testing circuit comprises: slow clock circuit, fast clock circuit and system clock;
Described system clock circuit comprises:
One four d flip-flop, its data output end output system starts test signal;
One the 3rd two-stage synchronizer, its data output end is connected with the data input pin of the 5th d type flip flop, and this data output end is connected with an input end of door with the 4th through a reverser;
One the 5th d type flip flop, its data output end is connected with another input end of door with the 4th;
One the 4th with the door, its output terminal is connected with the synchronous reset end of described four d flip-flop, the synchronous enabling signal negative edge of warp for detection of fast clock counter, when the synchronous enabling signal negative edge of the warp that detects fast clock counter, its output signal resets described four d flip-flop, and scavenge system starts test signal synchronously;
The input end of clock input system clock signal of described four d flip-flop, the 3rd two-stage synchronizer and the 5th d type flip flop;
Described fast clock circuit comprises:
One second two-stage synchronizer, its data output end is connected with an input end of door with the 3rd with the data input pin of 3d flip-flop;
One 3d flip-flop, its data output end is connected with another input end of door with the 3rd through a reverser, and this data output end is connected with the data input pin that the counting of fast clock counter enables input end and described the 3rd two-stage synchronizer; Export the synchronous enabling signal of warp of fast clock counter;
One fast clock counter, its terminal count output is exported fast clock count value;
One the 3rd with the door, its output terminal is connected with the synchronous reset end of described fast clock counter;
The input end of clock of described second two-stage synchronizer, 3d flip-flop and fast clock counter is imported fast clock signal;
Described slow clock circuit comprises:
One first two-stage synchronizer, its data input pin is connected with the data output end of described four d flip-flop, and input system starts test signal; Its data output end is connected with an input end of door and the data input pin of first d type flip flop with first;
One first d type flip flop, its data output end is connected with an input end of door with second, and this data output end is connected with another input end of door with first through a reverser;
One slow clock counter, its counting enable input end and are connected with the output terminal of door with second, import the enabling signal of slow clock counter;
One first with the door, its output terminal is connected with the synchronous reset end of described slow clock counter;
One comparer, its reverse input end is connected its positive input input reference with the terminal count output of slow clock counter;
One second with the door, its another input end is connected with the output terminal of described comparer;
One second d type flip flop, its data input pin is connected with the output terminal of door with second; Its data output end is connected with the data input pin of described second two-stage synchronizer, export fast clock counter without the fast synchronous enabling signal of clock circuit;
The input end of clock input slow clock signal of described first two-stage synchronizer, first d type flip flop, slow clock counter and second d type flip flop;
Described " two-stage synchronizer " is composed in series by two d type flip flops, is used for asynchronous signal is carried out synchronously.
The present invention compares with the method for traditional testing clock frequency, the test error of clock frequency can be controlled in very little scope, just test the error of hour counter and can control in two fast clock period, this is very important under the bigger situation of test clock and measured clock frequency difference.
The present invention can reduce test error effectively, obtains test result more accurately.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is one embodiment of the invention clock rate testing circuit structure diagram;
Fig. 2 is described clock rate testing method flow diagram.
Embodiment
Present many products have built-in clock, in order to understand the frequency of built-in clock, generally be to adopt the clock of contact interface to remove to test built-in clock, be that test clock and tested clock are counted simultaneously, the frequency of the tested clock of frequency computation part by the count value in the certain hour and known interface clock then.Adopt said method testing clock frequency error bigger, especially built-in 100KHz clock and contact clock frequency difference has tens times more than in the project that has, and this will make test error to accept.
Present invention focuses on the boot sequence of gated counter accurately and select between correct count block, so that can reduce test error effectively, obtain test result more accurately in the short period of time.
Fig. 1 is one embodiment of the invention, shown in the clock rate testing circuit formed by system clock circuit, slow clock circuit and fast clock circuit three parts, what consider here is three clocks asynchronous situations fully, therefore it is synchronous that signal all needs to carry out two-stage from a clock zone to another clock zone, and the reference value of comparing with the count value of slow clock counter namely is between the count block of test, can be fixed value, also can be a programmable value.
Described system clock circuit comprises:
One four d flip-flop DFF4, its input end of clock CLK input system clock sys_clk, data output end Q output system starts test signal start_test (high level is effective).
One the 3rd two-stage synchronizer 2DFF3, its data output end Q is connected with the data input pin D of the 5th d type flip flop DFF5, and the data output end Q of the 3rd two-stage synchronizer 2DFF3 is connected its input end of clock CLK input system clock sys_clk with the 4th with the input end of door AND4 through a reverser.(described " two-stage synchronizer " is composed in series by two d type flip flops, just input signal played two bats, and effect is that asynchronous signal is carried out synchronously)
One the 5th d type flip flop DFF5, its input end of clock CLK input system clock sys_clk, data output end Q is connected with another input end of door AND4 with the 4th.
One the 4th with the door AND4, its output terminal is connected with the synchronous reset end R of described four d flip-flop DFF4, the synchronous enabling signal start_fastcounter negative edge of warp for detection of fast clock counter KJ, when the synchronous enabling signal start_fastcounter negative edge of the warp that detects fast clock counter, its output signal resets described four d flip-flop DFF4, comes synchronous scavenge system to start test signal start_test.
Described fast clock circuit comprises:
One second two-stage synchronizer 2DFF2, its data output end Q is connected with the input end of door AND3 with the 3rd with the data input pin D of 3d flip-flop DFF3, and its input end of clock CLK imports fast clock signal fast_clk.
One 3d flip-flop DFF3, its input end of clock CLK imports fast clock signal fast_clk; Its data output end Q is connected with another input end of door AND3 with the 3rd through a reverser, and its data output end Q is connected with the data input pin D that the counting of fast clock counter KJ enables the 3rd two-stage synchronizer 2DFF3 of input end EN and described system clock circuit, exports the synchronous enabling signal start_fastcounter of warp of fast clock counter KJ.
One fast clock counter KJ, its input end of clock CLK imports fast clock signal fast_clk, and terminal count output is exported fast clock count value fast_counter.
One the 3rd with a door AND3, its output terminal is connected with the fast synchronous reset end R of clock counter KJ.
Described slow clock circuit comprises:
One first two-stage synchronizer 2DFF1, its input end of clock CLK input slow clock signal slow_clk, its data input pin D is connected with the data output end Q of the four d flip-flop DFF of described system clock circuit, and input system starts test signal start_test; Its data output end Q is connected with the input end of door AND1 and the data input pin D of the first d type flip flop DFF1 with first.
One first d type flip flop DFF1, its input end of clock CLK input slow clock signal slow_clk, its data output end Q is connected with the input end of door AND2 with second, and the data output end Q of the first d type flip flop DFF1 is connected with another input end of door AND1 with first through a reverser.
One slow clock counter MJ, its input end of clock CLK input slow clock signal slow_clk, its counting enable input end EN and are connected with the output terminal of door AND2 with second, import the enabling signal start_slow counter of slow clock counter;
One first with a door AND1, its output terminal is connected with the slow synchronous reset end R of clock counter MJ.
One comparer BJ, its reverse input end is connected its positive input input reference with the terminal count output of slow clock counter MJ.
One second with the door AND2, its another input end is connected with the output terminal of described comparer BJ.
One second d type flip flop DFF2, its input end of clock CLK input slow clock signal slow_clk, its data input pin D is connected with the output terminal of door AND2 with second; Its data output end Q is connected with the data input pin D of the second two-stage synchronizer 2DFF2 of described fast clock circuit, export fast clock counter without the fast synchronous enabling signal slowclk_start_fastclk of clock circuit.
Shown in Fig. 1,2, after system starts test, slow clock circuit carries out synchronous to the startup test signal start_test of system earlier and detects its rising edge, behind the rising edge that the system that detects starts test signal start_test, first makes slow clock counter MJ synchronously clear 0 with the output of door AND1, then starts the slow clock signal slow_clk of slow clock counter MJ and counts.
In slow clock counter MJ enabling counting and between meter expires, the fast clock counter KJ of the enabling signal slowclk_start_fastclk deactivation without synchronous that slow clock circuit produces counts.
Fast clock circuit is to carrying out synchronous and detecting its rising edge without synchronous enabling signal slowclk_start_fastclk, when the rising edge that detects without synchronous enabling signal slowclk_start_Fastclk, the 3rd makes fast clock counter KJ synchronously clear 0 with the output of door AND3, and the fast clock counter KJ of startup counts under the synchronous enabling signal start_fastcounter effect of the warp of the fast clock counter KJ that produces.
After writing all over, slow clock counter MJ stops counting, the fast clock counter of second d type flip flop DFF2 output can become low level automatically without the fast synchronous enabling signal slowclk_start_fastclk of clock circuit, thereby fast clock counter KJ also can stop counting automatically.
System clock circuit carries out synchronously the enabling signal start_fastcounter of fast clock counter, and detect the enabling signal start_fastcounter negative edge of fast clock counter, when detecting the enabling signal start_fastcounter negative edge of fast clock counter, make four d flip-flop DFF4 synchronous reset, come synchronous scavenge system to start test signal start_test.System reads the count value fast_counter of fast clock counter, according to the frequency of the tested clock of frequency computation part of the count value of the count value of fast clock counter, slow clock counter and known test clock.
Between the count block of circuit shown in Figure 1 fully being benchmark between the count block of slow clock, because the speed clock is asynchronous fully, the place that error may occur is startup and the end of fast clock counter, but the error maximum of Yin Ruing is no more than a fast clock period respectively, therefore the error of introducing altogether is no more than two fast clock period, and namely the count value fast_counter error of fast clock counter is no more than 2.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. a clock rate testing method is characterized in that, comprises the steps:
Step 1, test clock and tested clock are divided into fast clock and slow clock, fast clock counter are set fast clock is counted, slow clock counter is set slow clock is counted; Between the count block during test being the reference count interval between the count block of slow clock;
Step 2, system start the test back slow clock counter of elder generation's startup and count, and restart fast clock counter after the slow clock counter enabling counting and count;
Step 3, slow clock counter stop counting after writing all over, and then stop fast clock counter counting;
The test starting position of step 4, the signal removal system that stops to count with fast clock counter, read the numerical value of fast clock counter, according to the frequency of the tested clock of frequency computation part of the count value of the count value of fast clock counter, slow clock counter and known test clock.
2. a clock rate testing circuit is characterized in that, comprising: slow clock circuit, fast clock circuit and system clock;
Described system clock circuit comprises:
One four d flip-flop, its data output end output system starts test signal;
One the 3rd two-stage synchronizer, its data output end is connected with the data input pin of the 5th d type flip flop, and this data output end is connected with an input end of door with the 4th through a reverser;
One the 5th d type flip flop, its data output end is connected with another input end of door with the 4th;
One the 4th with the door, its output terminal is connected with the synchronous reset end of described four d flip-flop, the synchronous enabling signal negative edge of warp for detection of fast clock counter, when the synchronous enabling signal negative edge of the warp that detects fast clock counter, its output signal resets described four d flip-flop, and scavenge system starts test signal synchronously;
The input end of clock input system clock signal of described four d flip-flop, the 3rd two-stage synchronizer and the 5th d type flip flop;
Described fast clock circuit comprises:
One second two-stage synchronizer, its data output end is connected with an input end of door with the 3rd with the data input pin of 3d flip-flop;
One 3d flip-flop, its data output end is connected with another input end of door with the 3rd through a reverser, and this data output end is connected with the data input pin that the counting of fast clock counter enables input end and described the 3rd two-stage synchronizer; Export the synchronous enabling signal of warp of fast clock counter;
One fast clock counter, its terminal count output is exported fast clock count value;
One the 3rd with the door, its output terminal is connected with the synchronous reset end of described fast clock counter;
The input end of clock of described second two-stage synchronizer, 3d flip-flop and fast clock counter is imported fast clock signal;
Described slow clock circuit comprises:
One first two-stage synchronizer, its data input pin is connected with the data output end of described four d flip-flop, and input system starts test signal; Its data output end is connected with an input end of door and the data input pin of first d type flip flop with first;
One first d type flip flop, its data output end is connected with an input end of door with second, and this data output end is connected with another input end of door with first through a reverser;
One slow clock counter, its counting enable input end and are connected with the output terminal of door with second, import the enabling signal of slow clock counter;
One first with the door, its output terminal is connected with the synchronous reset end of described slow clock counter;
One comparer, its reverse input end is connected its positive input input reference with the terminal count output of slow clock counter;
One second with the door, its another input end is connected with the output terminal of described comparer;
One second d type flip flop, its data input pin is connected with the output terminal of door with second; Its data output end is connected with the data input pin of described second two-stage synchronizer, export fast clock counter without the fast synchronous enabling signal of clock circuit;
The input end of clock input slow clock signal of described first two-stage synchronizer, first d type flip flop, slow clock counter and second d type flip flop;
Described " two-stage synchronizer " is composed in series by two d type flip flops, is used for asynchronous signal is carried out synchronously.
3. clock rate testing circuit as claimed in claim 2, it is characterized in that: after system starts test, described slow clock circuit carries out synchronous to system's startup test signal earlier and detects its rising edge, behind the rising edge that the system that detects starts test signal, described first makes slow clock counter synchronously clear 0 with the output of door, then starts slow clock counter slow clock signal is counted;
In described slow clock counter enabling counting and between meter expiry, slow clock circuit produce fast clock counter without the fast synchronous enabling signal of clock circuit, start fast clock counter and count.
4. clock rate testing circuit as claimed in claim 3, it is characterized in that: described fast clock circuit carries out synchronously and detects its rising edge without synchronous enabling signal fast clock counter, when detecting described rising edge without synchronous enabling signal, the 3rd makes fast clock counter synchronously clear 0 with the output of door, and starts fast clock counter count under the synchronous enabling signal effect of the warp of fast clock counter.
5. as claim 2 or 3 described clock rate testing circuit, it is characterized in that: stop counting after slow clock counter is write all over, then fast clock counter become low level automatically without the fast synchronous enabling signal of clock circuit, fast clock counter stops counting automatically.
6. clock rate testing circuit as claimed in claim 2, it is characterized in that: system clock circuit carries out synchronously the synchronous enabling signal of the warp of fast clock counter, and detect this through synchronous enabling signal negative edge, when detecting described negative edge, make the four d flip-flop synchronous reset, remove described system synchronously and start test signal.
7. clock rate testing circuit as claimed in claim 2, it is characterized in that: system reads the count value of fast clock counter, according to the frequency of the tested clock of frequency computation part of the count value of the count value of fast clock counter, slow clock counter and known test clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210004410.4A CN103197139B (en) | 2012-01-06 | 2012-01-06 | Clock rate testing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210004410.4A CN103197139B (en) | 2012-01-06 | 2012-01-06 | Clock rate testing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103197139A true CN103197139A (en) | 2013-07-10 |
| CN103197139B CN103197139B (en) | 2017-03-15 |
Family
ID=48719824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210004410.4A Active CN103197139B (en) | 2012-01-06 | 2012-01-06 | Clock rate testing circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103197139B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103698603A (en) * | 2013-12-27 | 2014-04-02 | 深圳芯邦科技股份有限公司 | Chip, chip clock testing method and chip clock testing system |
| CN104931779A (en) * | 2015-05-08 | 2015-09-23 | 中国电子科技集团公司第四十一研究所 | Single-channel realized continuous frequency measure method |
| CN104931778A (en) * | 2015-06-09 | 2015-09-23 | 浙江大学 | Clock frequency detection circuit |
| WO2019019708A1 (en) * | 2017-07-27 | 2019-01-31 | 江苏集萃有机光电技术研究所有限公司 | Quartz crystal microbalance, detection method and computer-readable medium |
| CN109976955A (en) * | 2017-12-28 | 2019-07-05 | 上海坚芯电子科技有限公司 | A kind of clock rate testing circuit and measuring method |
| CN111026232A (en) * | 2019-11-08 | 2020-04-17 | 深圳市汇顶科技股份有限公司 | Clock calibration method, chip and electronic equipment |
| CN113129991A (en) * | 2021-04-01 | 2021-07-16 | 深圳市纽创信安科技开发有限公司 | Chip safety protection method and circuit for ROMBIST test |
| CN114461009A (en) * | 2022-01-07 | 2022-05-10 | 山东云海国创云计算装备产业创新中心有限公司 | Method for automatically identifying clock domain conversion applied to FPGA single-bit signal |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5742650A (en) * | 1994-02-04 | 1998-04-21 | Motorola, Inc. | Power reduction method and apparatus for phase-locked loop based clocks in a data processing system |
| JPH10190568A (en) * | 1996-12-27 | 1998-07-21 | Matsushita Electric Ind Co Ltd | Radio receiving device |
| CN1567120A (en) * | 2003-06-23 | 2005-01-19 | 华为技术有限公司 | Method and circuit for conducting real time test for single chip clock shaking |
| CN1767390A (en) * | 2004-10-27 | 2006-05-03 | 中兴通讯股份有限公司 | Multipath clock detecting device |
| CN101366188A (en) * | 2005-11-09 | 2009-02-11 | 高通股份有限公司 | Apparatus and methods for estimating a sleep clock frequency |
| CN101959298A (en) * | 2009-07-17 | 2011-01-26 | 联芯科技有限公司 | Method and device for calibrating slow timing clock and terminal |
-
2012
- 2012-01-06 CN CN201210004410.4A patent/CN103197139B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5742650A (en) * | 1994-02-04 | 1998-04-21 | Motorola, Inc. | Power reduction method and apparatus for phase-locked loop based clocks in a data processing system |
| JPH10190568A (en) * | 1996-12-27 | 1998-07-21 | Matsushita Electric Ind Co Ltd | Radio receiving device |
| CN1567120A (en) * | 2003-06-23 | 2005-01-19 | 华为技术有限公司 | Method and circuit for conducting real time test for single chip clock shaking |
| CN1767390A (en) * | 2004-10-27 | 2006-05-03 | 中兴通讯股份有限公司 | Multipath clock detecting device |
| CN101366188A (en) * | 2005-11-09 | 2009-02-11 | 高通股份有限公司 | Apparatus and methods for estimating a sleep clock frequency |
| CN101959298A (en) * | 2009-07-17 | 2011-01-26 | 联芯科技有限公司 | Method and device for calibrating slow timing clock and terminal |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103698603A (en) * | 2013-12-27 | 2014-04-02 | 深圳芯邦科技股份有限公司 | Chip, chip clock testing method and chip clock testing system |
| CN103698603B (en) * | 2013-12-27 | 2017-03-15 | 深圳芯邦科技股份有限公司 | A kind of chip and its clock test methodology and chip clock test system |
| CN104931779A (en) * | 2015-05-08 | 2015-09-23 | 中国电子科技集团公司第四十一研究所 | Single-channel realized continuous frequency measure method |
| CN104931778A (en) * | 2015-06-09 | 2015-09-23 | 浙江大学 | Clock frequency detection circuit |
| CN104931778B (en) * | 2015-06-09 | 2017-09-12 | 浙江大学 | A kind of clock frequency detection circuit |
| WO2019019708A1 (en) * | 2017-07-27 | 2019-01-31 | 江苏集萃有机光电技术研究所有限公司 | Quartz crystal microbalance, detection method and computer-readable medium |
| CN109976955A (en) * | 2017-12-28 | 2019-07-05 | 上海坚芯电子科技有限公司 | A kind of clock rate testing circuit and measuring method |
| CN111026232A (en) * | 2019-11-08 | 2020-04-17 | 深圳市汇顶科技股份有限公司 | Clock calibration method, chip and electronic equipment |
| CN113129991A (en) * | 2021-04-01 | 2021-07-16 | 深圳市纽创信安科技开发有限公司 | Chip safety protection method and circuit for ROMBIST test |
| CN113129991B (en) * | 2021-04-01 | 2023-04-07 | 深圳市纽创信安科技开发有限公司 | Chip safety protection method and circuit for ROMBIST test |
| CN114461009A (en) * | 2022-01-07 | 2022-05-10 | 山东云海国创云计算装备产业创新中心有限公司 | Method for automatically identifying clock domain conversion applied to FPGA single-bit signal |
| CN114461009B (en) * | 2022-01-07 | 2024-04-26 | 山东云海国创云计算装备产业创新中心有限公司 | Method for automatically identifying clock domain conversion by using FPGA single bit signal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103197139B (en) | 2017-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103197139A (en) | Clock frequency test method and clock frequency test circuit | |
| CN109217951B (en) | Transmission delay testing method and device based on FPGA | |
| CN105245203B (en) | High-precision low-speed clock duty ratio detecting system and method | |
| CN2922277Y (en) | Clock burr testing circuit | |
| CN103487649B (en) | Method and device capable of measuring both frequency of continuous waves and frequency of pulse modulation carrier waves | |
| CN102830247A (en) | Method and device for detecting rotation state of rotation part | |
| TWI407696B (en) | Asynchronous ping-pong counter | |
| CN103558753B (en) | A kind of high-resolution clock detection method and device | |
| CN103607509B (en) | A kind of shutdown alarm clock trigger system of mobile terminal and triggering method thereof | |
| CN102147426B (en) | Broadband triggering circuit of digital oscilloscope | |
| CN113009961A (en) | Cross-clock synchronous circuit and SoC system | |
| CN103227558A (en) | Wave-by-wave current limiting method and device | |
| CN202794346U (en) | Pulse width detection circuit | |
| CN103955255A (en) | Accurate measurement system based on FPG binary input event, and method thereof | |
| CN106645784A (en) | Method and circuit for measuring rotating speed of rotary machine | |
| CN103647552A (en) | Clock frequency detection circuit | |
| CN106707034A (en) | Pulse signal detection method based on Windows system function and multi-thread technology | |
| CN107565936B (en) | Logic implementation device of input clock stabilizing circuit | |
| CN107247183B (en) | Phase measurement system and method | |
| CN103744094B (en) | Based on the navigational system difference of injection time measurement module of CPLD combination | |
| CN109256998A (en) | Control the method and system and servo motor of current of electric sampling with high precision | |
| WO2022110235A1 (en) | Chip and clock detection method | |
| CN204480671U (en) | A kind of antimierophonic delay counter | |
| CN112506838A (en) | SPI clock synchronization method applied to IR46 electric meter calibrating device | |
| CN105224481A (en) | PWM transmits the implementation of data in input mode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |