CN204480671U - A kind of antimierophonic delay counter - Google Patents
A kind of antimierophonic delay counter Download PDFInfo
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- CN204480671U CN204480671U CN201520069917.7U CN201520069917U CN204480671U CN 204480671 U CN204480671 U CN 204480671U CN 201520069917 U CN201520069917 U CN 201520069917U CN 204480671 U CN204480671 U CN 204480671U
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Abstract
The utility model relates to a kind of antimierophonic delay counter, comprises δ fb feedback delay circuit, sample circuit, digital filter, enter counter, output counter and FIFO.The utility model solve existing memory latency counter exist output pointer to input pointer position make a mistake, the technical matters that the data reading instruction exported in the cycle of mistake, the utility model is by increasing digital filter, ensure that the position that hold signal occurs can not change, thus ensure the appearance of hold signal period property along with the change output pointer of voltage/temperature/technique can not mistake to the phase relation inputting pointer.Implementation is simple.
Description
Technical field
The utility model relates to semiconductor DRAM memory design field, is specifically related to a kind of antimierophonic delay counter.
Background technology
Computing machine and various electronic equipment are widely used in the various aspects of the modern life, increasing to memory article (DRAM storer) demand.People are more and more faster to rate request, and the clock of storer is just more and more less.So the impact of noise on properties of product is increasing.
The delay counter of storer is used to realize the instruction of reading of storer.Whenever one is read instruction, the rising edge clock after user is desirably in a fixed delay period (user can configure) obtains the data expected, be illustrated in figure 1 DRAM memory read instructions operation chart, in figure, delay period is 6.In order to realize above-mentioned read operation, DRAM storer generally divides 3 steps to complete:
Step A: storer accepts outside and reads instruction, produce internal clocking clk_rcv, the delay of internal clocking clk_rcv and external clock clk is δ 0;
Step B: utilize internal clocking to count
Step C: terminate to export data at counter, the effective time is δ 1 from internal clocking to data
As shown in Figure 2, two apparent problems are had:
1, export data to align with external clock clk;
2, along with the clock period is more and more less, internal latency (δ 0+ δ 1) is likely greater than a clock period, as Fig. 2 data likely occur 5/6/7... clock period.
In order to solve the problem, digital delay phase-locked loop DLL introduced by DRAM storer, produce a delayed clock clk_dll of internal clocking clk_rcv, the phase differential of delayed clock clk_dll and external clock clk is δ 1, as shown in Figure 3, if the delay δ dll of the delayed clock clk_dll that digital delay phase-locked loop DLL produces and internal clocking clk_rcv, meet δ dll=N*Tck-(δ 0+ δ 1), the data exported by delayed clock clk_dll like this and external clock complete matching.
As shown in Figure 4, Figure 5, DRAM delay counter utilizes δ fb delay circuit to produce a hold signal and is used for guarantee output pointer (output pointer) to the sequential relationship inputting pointer (input pointer).If δ fb=δ 0+ δ 1, so clk_fb and clk_rcv phase place is with regard to complete matching.After user sets DRAM delay period, hold signal will periodically occur ensureing that the change output pointer along with voltage/temperature/technique can not mistake to the phase relation of input pointer.In the ideal case (voltage/temperature/technique is constant), the position that hold signal occurs can not change, and the position of same input pointer and output pointer also can not change as shown in Figure 6.
But when system generation noise time, the impact that hold signal produced by the foundation/retention time can make a mistake.Thus cause output pointer to make a mistake to the position of input pointer, finally cause the data reading instruction to export as shown in Figure 7 in the cycle of mistake.
Summary of the invention
In order to solve existing memory latency counter exist output pointer to input pointer position make a mistake, the technical matters that the data reading instruction exported in the cycle of mistake, the utility model provides a kind of antimierophonic delay counter.
Technical solution of the present utility model:
A kind of antimierophonic delay counter, its special character is: comprise
δ fb feedback delay circuit: produce hold signal for carrying out process to delayed clock clk_dll:
Sample circuit: for sampling to hold signal, exports the input pointer of current hold set and upper N hold set input pointer value;
Digital filter: receive the input pointer of the current hold set that sample circuit exports and upper N hold set input pointer value, and compare output permission hold set input pointer:
Enter counter: for counting permission hold set input pointer, export input pointer;
Output counter: export output pointer for carrying out counting to delayed clock clk_dll, export input pointer;
FIFO: export and read instruction for receiving input pointer, output pointer and read pointer after delay counter.
Above-mentioned δ fb feedback delay circuit hold signal is used for ensureing the sequential relationship of output pointer to input pointer.
N in above-mentioned upper N hold set input pointer value meets: N > 0.
The advantage that the utility model has:
The utility model, by increasing digital filter, ensures that the position that hold signal occurs can not change, thus ensure the appearance of hold signal period property along with the change output pointer of voltage/temperature/technique can not mistake to the phase relation inputting pointer.Implementation is simple.
Accompanying drawing explanation
Fig. 1 is DRAM memory read instructions operation chart;
Fig. 2 is for reading Command Resolution figure mono-schematic diagram;
Fig. 3 is for reading Command Resolution figure bis-schematic diagram;
Fig. 4 is DLL basic principle schematic;
Fig. 5 is the basic schematic diagram of delay counter;
Fig. 6 is correct hold signal schematic representation;
Fig. 7 is the hold signal schematic representation of mistake;
Fig. 8 is the structural representation of the utility model delay counter.
Embodiment
Digital delay phase-locked loop DLL introduced by DRAM storer, produce a delayed clock clk_dll of internal clocking clk_rcv, the phase differential of delayed clock clk_dll and external clock clk is δ 1, if the delay δ dll of the delayed clock clk_dll that digital delay phase-locked loop DLL produces and internal clocking clk_rcv, meet δ dll=N*Tck-(δ 0+ δ 1), the data exported by delayed clock clk_dll like this and external clock complete matching.
DRAM delay counter utilizes δ fb feedback delay circuit to produce a hold signal and is used for ensureing the sequential relationship of output pointer to input pointer.If δ fb=δ 0+ δ 1, so clk_fb and clk_rcv phase place is with regard to complete matching.After user sets DRAM delay period, hold signal will periodically occur ensureing that the change output pointer along with voltage/temperature/technique can not mistake to the phase relation of input pointer.In the ideal case (voltage/temperature/technique is constant), the position that hold signal occurs can not change; But when system generation noise time, the impact that hold signal produced by the foundation/retention time can make a mistake.Digital filter is added when hold home position signal input pointer.
As shown in Figure 8, a kind of antimierophonic delay counter, comprising δ fb feedback delay circuit: produce hold signal for carrying out process to delayed clock clk_dll: sample circuit: for sampling to hold signal, exporting the input pointer of current hold set and upper N hold set input pointer value (N > 0); Digital filter: receive the input pointer of the current hold set that sample circuit exports and upper N hold set input pointer value, and compare output permission hold set input pointer: enter counter: for counting permission hold set input pointer, output inputs pointer; Output counter: export output pointer for carrying out counting to delayed clock clk_dll, export input pointer; FIFO: export and read instruction for receiving input pointer, output pointer and read pointer after delay counter.
Claims (3)
1. an antimierophonic delay counter, is characterized in that: comprise
δ fb feedback delay circuit: produce hold signal for carrying out process to delayed clock clk_dll:
Sample circuit: for sampling to hold signal, exports the input pointer of current hold set and upper N hold set input pointer value;
Digital filter: receive the input pointer of the current hold set that sample circuit exports and upper N hold set input pointer value, and compare output permission hold set input pointer:
Enter counter: for counting permission hold set input pointer, export input pointer;
Output counter: export output pointer for carrying out counting to delayed clock clk_dll, export input pointer;
FIFO: export and read instruction for receiving input pointer, output pointer and read pointer after delay counter.
2. antimierophonic delay counter according to claim 1, is characterized in that: described δ fb feedback delay circuit hold signal is used for ensureing the sequential relationship of output pointer to input pointer.
3. antimierophonic delay counter according to claim 1 and 2, is characterized in that: the N in described upper N hold set input pointer value meets: N > 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520069917.7U CN204480671U (en) | 2015-01-30 | 2015-01-30 | A kind of antimierophonic delay counter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520069917.7U CN204480671U (en) | 2015-01-30 | 2015-01-30 | A kind of antimierophonic delay counter |
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| Publication Number | Publication Date |
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| CN204480671U true CN204480671U (en) | 2015-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201520069917.7U Withdrawn - After Issue CN204480671U (en) | 2015-01-30 | 2015-01-30 | A kind of antimierophonic delay counter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658596A (en) * | 2015-01-30 | 2015-05-27 | 西安华芯半导体有限公司 | Anti-noise delay counter |
-
2015
- 2015-01-30 CN CN201520069917.7U patent/CN204480671U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658596A (en) * | 2015-01-30 | 2015-05-27 | 西安华芯半导体有限公司 | Anti-noise delay counter |
| CN104658596B (en) * | 2015-01-30 | 2018-01-19 | 西安紫光国芯半导体有限公司 | A kind of antimierophonic delay counter |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee before: Xi'an Sinochip Semiconductors Co., Ltd. |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20150715 Effective date of abandoning: 20180119 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20150715 Effective date of abandoning: 20180119 |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |