CN104283561B - A kind of asynchronous clock parallel-serial conversion half period output circuit - Google Patents
A kind of asynchronous clock parallel-serial conversion half period output circuit Download PDFInfo
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- CN104283561B CN104283561B CN201410485272.5A CN201410485272A CN104283561B CN 104283561 B CN104283561 B CN 104283561B CN 201410485272 A CN201410485272 A CN 201410485272A CN 104283561 B CN104283561 B CN 104283561B
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Abstract
The embodiment of the invention discloses a kind of asynchronous clock parallel-serial conversion half period output circuit, including synchronization frequency division clock generation circuit 10, data synchronization circuit 20, control signal generation circuit 40 and parallel-serial conversion output circuit 30.Data synchronization circuit 20 realizes that input data is synchronous with high frequency clock signal, and parallel-serial conversion output circuit 30 realize by input data from Parallel transformation be Serial output.In the circuit of the embodiment of the present invention, asynchronous clock synchronization and parallel-serial conversion can be realized at the same time, and circuit structure is simple.
Description
Technical field
The present invention relates to production line analog-digital converter technical field, more particularly, to a kind of asynchronous clock parallel-serial conversion half period
Output circuit.
Background technology
Production line analog-digital converter（PL_ADC）There is preferable compromise in area, power consumption, speed and precision aspect, gradually
One of implementation as High Speed High Precision ADC.
In PL_ADC, to realize the parallel output of multiple bit digital signal needs multiple output pads（PAD）, due to output
PAD Limited Numbers, so being exported again after data first to be done to parallel-serial conversion.But this further relates to the problem of clock is asynchronous.By
In the digital signal of parallel output produced under the control of internal low-frequency clock, i.e., it is same with internal low-frequency rising edge clock
Step.To be exported under the control of exterior high frequency clock, problems faced seeks to synchronize asynchronous clock first why
Sample realizes the synchronization of low-and high-frequency clock on the premise of to the value of digital signal accurately sample, at present for when have certain difficulty
Degree.Next the problem of facing is parallel-serial conversion, and the method for parallel-serial conversion has very much, but all excessively complicated or during to exporting
The frequency requirement of clock is higher.Being realized in circuit traditional at present will realize that asynchronous clock is synchronous and parallel-serial conversion is seldom at the same time, and
And it is more complicated, the effect reached is less desirable.
The content of the invention
An object of the present invention be to provide it is a kind of can realize that asynchronous clock is synchronous at the same time and parallel-serial conversion it is asynchronous when
Clock parallel-serial conversion half period output circuit.
Technical solution disclosed by the invention includes：
Provide a kind of asynchronous clock parallel-serial conversion half period output circuit, it is characterised in that including：Synchronization frequency division clock
Generation circuit 10, the synchronization frequency division clock generation circuit 10 are based on high frequency clock signal clk_f and produce the first frequency-dividing clock letter
Number clk1, the second sub-frequency clock signal clk2, three frequency division clock signal clk3 and the 4th sub-frequency clock signal clk4；Data are same
Step circuit 20, the data synchronization circuit 20 are connected to the synchronization frequency division clock generation circuit 10, the data synchronization circuit
20 receive input data D<7:0>And according to the first sub-frequency clock signal clk1 by the input data D<7:0>With it is described
High frequency clock signal clk_f is synchronous；Control signal generation circuit 40, the control signal generation circuit 40 are connected to the synchronization
Frequency-dividing clock generation circuit 10, and according to the first sub-frequency clock signal clk1, the second sub-frequency clock signal clk2, the 3rd point
Frequency clock signal clk3 and the 4th sub-frequency clock signal clk4 produces control signal sel<3:0>；Parallel-serial conversion output circuit 30,
The parallel-serial conversion output circuit 30 is connected to the data synchronization circuit 20 and the control signal generation circuit 40, and according to
The control signal sel<3:0>By the input data Serial output.
In one embodiment of the present of invention, the synchronization frequency division clock generation circuit includes the first d type flip flop 101 and second
D type flip flop 102, wherein：The input end of clock of first d type flip flop 101 is connected to the high frequency clock signal clk_f, institute
The positive output end for stating the first d type flip flop 101 exports the 4th sub-frequency clock signal clk4 and is connected to the 2nd D side by side and touches
The data input pin of device 102 is sent out, the reversed-phase output of first d type flip flop 101 exports second sub-frequency clock signal
clk2；The input end of clock of second d type flip flop 102 is connected to the high frequency clock signal clk_f, the 2nd D triggerings
The positive output end of device 102 exports the first sub-frequency clock signal clk1, the reversed-phase output of second d type flip flop 102
Export the three frequency division clock signal clk3 and be connected to the data input pin of first d type flip flop 101.
In one embodiment of the present of invention, the data synchronization circuit 20 includes the first d type flip flop group 201 and the 2nd D is touched
Device group 202 is sent out, wherein：The input end of clock of the first d type flip flop group 201 is connected to the inversion signal of low-frequency clock signal
Clk0B, the data input pin of the first d type flip flop group 201 are connected to the input data D<7:0>, the first D triggerings
The positive output end of device group 201 is connected to the data input pin of the second d type flip flop group 202；The second d type flip flop group
202 input end of clock is connected to the first sub-frequency clock signal clk1, the positive output of the second d type flip flop group 202
Hold the data output end for the data synchronization circuit 20 and export synchrodata dataout<7:0>.
In one embodiment of the present of invention, the control signal generation circuit 40 include the first NAND gate 400, second with it is non-
The 403, the 3rd NAND gate 405 of door, the 4th NAND gate 409, the first NOT gate 401, the second NOT gate 404, the 3rd NOT gate 406 and the 4th are non-
Door 410, wherein：Two input terminals of first NAND gate 400 be connected respectively to the first sub-frequency clock signal clk1 and
The 4th sub-frequency clock signal clk4, the output terminal of first NAND gate 400 export the inversion signal of the 3rd control signal
selB<3>And the input terminal of first NOT gate 401 is connected to, the 3rd control letter of output terminal output of first NOT gate 401
Number sel<3>；Two input terminals of second NAND gate 403 are connected respectively to the first sub-frequency clock signal clk1 and institute
State the second sub-frequency clock signal clk2, the inversion signal of the output terminal output second control signal of second NAND gate 403
selB<2>And the input terminal of second NOT gate 404 is connected to, output terminal output the second control letter of second NOT gate 404
Number sel<2>；Two input terminals of the 3rd NAND gate 405 are connected respectively to the three frequency division clock signal clk3 and institute
State the second sub-frequency clock signal clk2, the inversion signal of the output terminal output first control signal of the 3rd NAND gate 405
selB<1>And the input terminal of the 3rd NOT gate 406 is connected to, output terminal output the first control letter of the 3rd NOT gate 406
Number sel<1>；Two input terminals of the 4th NAND gate 409 are connected respectively to the three frequency division clock signal clk3 and institute
The 4th sub-frequency clock signal clk4 is stated, the output terminal of the 4th NAND gate 409 exports the inversion signal of the 0th control signal
selB<0>And the input terminal of the 4th NOT gate 410 is connected to, the 0th control letter of output terminal output of the 4th NOT gate 410
Number sel<0>.
In one embodiment of the present of invention, the parallel-serial conversion output circuit 30 is passed including the first transmission gate group 300, second
Defeated door group 301,3d flip-flop 302, four d flip-flop 303, the 5th d type flip flop 304 and multiple selector circuit 305, its
In：The input terminal of the first transmission gate group 300 is connected to the synchrodata dataout<7:0>In odd bits, described
The output terminal of one transmission gate group 300 is connected to the data input pin of the 3d flip-flop 302, the first transmission gate group 300
The first control terminal be connected to the control signal sel<3:0>, the second control terminal of the first transmission gate group 300 is connected to
The inversion signal selB of the control signal<3:0>；The input end of clock of the 3d flip-flop 302 is connected to the high frequency
The inversion signal clk_fB of clock signal, the positive output end of the 3d flip-flop 302 are connected to the multiple selector electricity
The first input end on road 305；The input terminal of the second transmission gate group 301 is connected to the synchrodata dataout<7:0>In
Zero-bit and even bit, the data that the output terminal of the second transmission gate group 301 is connected to the four d flip-flop 303 it is defeated
Enter end, the first control terminal of the second transmission gate group 301 is connected to the control signal sel<3:0>, second transmission gate
Second control terminal of group 301 is connected to the inversion signal selB of the control signal<3:0>；The four d flip-flop 303 when
Clock input terminal is connected to the inversion signal clk_fB of the high frequency clock signal, the positive output end of the four d flip-flop 303
It is connected to the data input pin of the 5th d type flip flop 304；The input end of clock of 5th d type flip flop 304 is connected to described
High frequency clock signal clk_f, the positive output end of the 5th d type flip flop 304 are connected to the multiple selector circuit 305
Second input terminal；First control terminal of the multiple selector circuit 305 is connected to the high frequency clock signal clk_f, described
Second control terminal of multiple selector circuit 305 is connected to the inversion signal clk_fB of the high frequency clock signal.
In the circuit of the embodiment of the present invention, asynchronous clock synchronization and parallel-serial conversion, and circuit knot can be realized at the same time
Structure is simple.
Brief description of the drawings
Fig. 1 is the structure diagram signal of the asynchronous clock parallel-serial conversion half period output circuit of one embodiment of the invention
Figure.
Fig. 2 is the structure diagram of the synchronization frequency division clock generation circuit of one embodiment of the invention.
Fig. 3 is the structure diagram of the data synchronization circuit of one embodiment of the invention.
Fig. 4 is the structure diagram of the control signal generation circuit of one embodiment of the invention.
Fig. 5 is the structure diagram of the parallel-serial conversion output circuit of one embodiment of the invention.
Embodiment
Below in conjunction with the asynchronous clock parallel-serial conversion half period output circuit of the attached drawing embodiment that the present invention will be described in detail
Concrete structure.
As shown in Figure 1, in one embodiment of the present of invention, a kind of asynchronous clock parallel-serial conversion half period output circuit includes
Synchronization frequency division clock generation circuit 10, data synchronization circuit 20, control signal generation circuit 40 and parallel-serial conversion output circuit 30.
Synchronization frequency division clock generation circuit 10 is used to be based on high frequency clock signal（For example, exterior high frequency clock signal）
Clk_f produces the first sub-frequency clock signal clk1, the second sub-frequency clock signal clk2, three frequency division clock signal clk3 and the 4th
Sub-frequency clock signal clk4.
Data synchronization circuit 20 is connected on synchronization frequency division clock generation circuit 10.The data synchronization circuit 20 receives input
Data（For example, in the case where input data is 8, D<7:0>）And according to the first sub-frequency clock signal clk1 by input data
D<7:0>It is synchronous with high frequency clock signal clk_f.
Control signal generation circuit 40 is connected to synchronization frequency division clock generation circuit 10, and during according to the first foregoing frequency dividing
Clock signal clk1, the second sub-frequency clock signal clk2, three frequency division clock signal clk3 and the 4th sub-frequency clock signal clk4 productions
Raw control signal sel<3:0>.
Parallel-serial conversion output circuit 30 is connected to data synchronization circuit 20 and control signal generation circuit 40, and according to control
The control signal sel that signal generating circuit 40 produces<3:0>The input data being synchronized via data synchronization circuit 20 is serial
Output.
As shown in Fig. 2, in one embodiment of the present of invention, synchronization frequency division clock generation circuit 10 can be touched including the first D
Send out 101 and second d type flip flop 102 of device.
The input end of clock of first d type flip flop 101 is connected to high frequency clock signal clk_f, and the first d type flip flop 101 is just
Phase output terminal exports the data input pin that the 4th sub-frequency clock signal clk4 is connected to the second d type flip flop 102 side by side, and the first D is touched
The reversed-phase output for sending out device 101 exports the second sub-frequency clock signal clk2.
The input end of clock of second d type flip flop 102 is connected to high frequency clock signal clk_f, and the second d type flip flop 102 is just
Phase output terminal exports the first sub-frequency clock signal clk1, the reversed-phase output output three frequency division clock letter of the second d type flip flop 102
Number clk3 is simultaneously connected to the data input pin of the first d type flip flop 101.
In the present embodiment, synchronization frequency division clock generation circuit 10 is used for the high frequency clock signal clk_f produced with the cycle is T
The difference of rising edge synch is followed successively by 90 degree four sub-frequency clock signal clk1, clk2, clk3 and clk4.
As shown in figure 3, in one embodiment of the present of invention, data synchronization circuit 20 can include the first d type flip flop group 201
With the second d type flip flop group 202.
The input end of clock of first d type flip flop group 201 is connected to the inversion signal clk0B of low-frequency clock signal, and the first D is touched
The data input pin of hair device group 201 is connected to input data D<7:0>, the positive output end of the first d type flip flop group 201 is connected to
The data input pin of second d type flip flop group 202.
The input end of clock of second d type flip flop group 202 is connected to the first sub-frequency clock signal clk1, the second d type flip flop group
202 positive output end is the data output end of data synchronization circuit 20 and exports synchrodata（It is i.e. foregoing same via data
The input data that step circuit 20 is synchronized）dataout<7:0>.
In the present embodiment, input signal D<7:0>External low frequency clock signal clk0 rising edge synch with the cycle for 4T,
So first signal is sampled to obtain precise and stable signal di with clk0 trailing edges<7:0>, then with same all with clk0
The local low-frequency clock signal clk1 rising edges of phase sample, and obtain the signal with output high frequency clock clk_f rising edge synch
dataout<7:0>。
As shown in figure 4, in one embodiment of the present of invention, control signal generation circuit 40 can include the first NAND gate
400th, the second NAND gate 403, the 3rd NAND gate 405, the 4th NAND gate 409, the first NOT gate 401, the second NOT gate the 404, the 3rd are non-
406 and the 4th NOT gate 410 of door.
Two input terminals of the first NAND gate 400 are connected respectively to the first sub-frequency clock signal clk1 and the 4th frequency-dividing clock
Signal clk4, the output terminal of the first NAND gate 400 export the inversion signal selB of the 3rd control signal<3>And it is non-to be connected to first
The input terminal of door 401, the output terminal of the first NOT gate 401 export the 3rd control signal sel<3>.
Two input terminals of the second NAND gate 403 are connected respectively to the first sub-frequency clock signal clk1 and the second frequency-dividing clock
Signal clk2, the inversion signal selB of the output terminal output second control signal of the second NAND gate 403<2>And it is non-to be connected to second
The input terminal of door 404, the output terminal output second control signal sel of the second NOT gate 404<2>.
Two input terminals of the 3rd NAND gate 405 are connected respectively to three frequency division clock signal clk3 and the second frequency-dividing clock
Signal clk2, the inversion signal selB of the output terminal output first control signal of the 3rd NAND gate 405<1>And it is non-to be connected to the 3rd
The input terminal of door 406, the output terminal output first control signal sel of the 3rd NOT gate 406<1>.
Two input terminals of the 4th NAND gate 409 are connected respectively to three frequency division clock signal clk3 and the 4th frequency-dividing clock
Signal clk4, the output terminal of the 4th NAND gate 409 export the inversion signal selB of the 0th control signal<0>And it is non-to be connected to the 4th
The input terminal of door 410, the output terminal of the 4th NOT gate 410 export the 0th control signal sel<0>.
In the present embodiment, the not overlapping control signal sel of four phases can be produced<3:0>And its inversion signal selB<3:0>,
They are followed successively by 90 degree of local low-frequency clock by difference（I.e. foregoing sub-frequency clock signal）clk1、clk2、clk3、clk4
Produce.
As shown in figure 5, in one embodiment of the present of invention, parallel-serial conversion output circuit 30 include the first transmission gate group 300,
Second transmission gate group 301,3d flip-flop 302, four d flip-flop 303, the 5th d type flip flop 304 and multiple selector circuit
305。
The input terminal of first transmission gate group 300 is connected to synchrodata dataout<7:0>In odd bits（For example,
dataout<7,5,3,1>）, the output terminal of the first transmission gate group 300 is connected to the data input pin of 3d flip-flop 302, and
First control terminal of one transmission gate group 300 is connected to control signal sel<3:0>, the second control terminal company of the first transmission gate group 300
It is connected to the inversion signal selB of control signal<3:0>.
The input end of clock of 3d flip-flop 302 is connected to the inversion signal clk_fB of high frequency clock signal, and the 3rd D is touched
The positive output end of hair device 302 is connected to the first input end of multiple selector circuit 305.
The input terminal of second transmission gate group 301 is connected to synchrodata dataout<7:0>In zero-bit and even bit
（For example, dataout<6,4,2,0>）, the output terminal of the second transmission gate group 301 is connected to the data input of four d flip-flop 303
End, the first control terminal of the second transmission gate group 301 are connected to control signal sel<3:0>, the second control of the second transmission gate group 301
End processed is connected to the inversion signal selB of control signal<3:0>.
The input end of clock of four d flip-flop 303 is connected to the inversion signal clk_fB of high frequency clock signal, and the 4th D is touched
The positive output end of hair device 303 is connected to the data input pin of the 5th d type flip flop 304.
The input end of clock of 5th d type flip flop 304 is connected to high frequency clock signal clk_f, and the 5th d type flip flop 304 is just
Phase output terminal is connected to the second input terminal of multiple selector circuit 305.
First control terminal of multiple selector circuit 305 is connected to high frequency clock signal clk_f, multiple selector circuit
305 the second control terminal is connected to the inversion signal clk_fB of high frequency clock signal.
In one embodiment of the present of invention, which for example can be alternative circuit.
In the present embodiment, first by input data（For example, foregoing synchrodata dataout<7:0>）Odd bits and
Even bit is divided into two output channels, odd bits dataout<7,5,3,1>By by signal sel<3:0>And selB<3:0>Control
First transmission gate group 300 of system, the trailing edge sampling of clock signal clk_f of the signal through 3d flip-flop 302 of output；It is even
Numerical digit dataout<6,4,2,0>It is connected to by signal sel<3:0>And selB<3:0>Second transmission gate group 301 of control, output
Signal first by four d flip-flop 303 clock signal clk_f trailing edge sample, then by the 5th d type flip flop 304 when
The upper drop of clock signal clk_f is along re-sampling；The odd bits and even bit signal adopted finally all reach alternative circuit 305,
Odd bits, low level valid period carry-out bit are exported in the clk_f high level valid periods.The advantages of alternative circuit, is one
Clk_f cycles exportable two digits signal；So it can realize that 8bit parallel datas are serial with 4 clk_f clock cycle
Output.
In the circuit of the embodiment of the present invention, asynchronous clock synchronization and parallel-serial conversion, and circuit knot can be realized at the same time
Structure is simple.
Above by specific embodiment, the present invention is described, but the present invention is not limited to these specific implementations
Example.It will be understood by those skilled in the art that various modifications, equivalent substitution, change etc. can also be done to the present invention, these conversion
, all should be within protection scope of the present invention without departing from the spirit of the present invention.In addition, " the reality described in above many places
Apply example " represent different embodiments, naturally it is also possible to it is completely or partially combined in one embodiment.
Claims (4)
- A kind of 1. asynchronous clock parallel-serial conversion half period output circuit, it is characterised in that including：Synchronization frequency division clock generation circuit（10）, the synchronization frequency division clock generation circuit（10）Based on high frequency clock signal （clk_f）Produce the first sub-frequency clock signal（clk1）, the second sub-frequency clock signal（clk2）, three frequency division clock signal （clk3）With the 4th sub-frequency clock signal（clk4）；Data synchronization circuit（20）, the data synchronization circuit（20）It is connected to the synchronization frequency division clock generation circuit（10）, The data synchronization circuit（20）Receive input data D<7:0>And according to first sub-frequency clock signal（clk1）By described in Input data D<7:0>With the high frequency clock signal（clk_f）It is synchronous；Control signal generation circuit（40）, the control signal generation circuit（40）It is connected to the synchronization frequency division clock and produces electricity Road（10）, and according to first sub-frequency clock signal（clk1）, the second sub-frequency clock signal（clk2）, three frequency division clock letter Number（clk3）With the 4th sub-frequency clock signal（clk4）Produce control signal sel<3:0>；Parallel-serial conversion output circuit（30）, the parallel-serial conversion output circuit（30）It is connected to the data synchronization circuit（20）With The control signal generation circuit（40）, and according to the control signal sel<3:0>By the input data Serial output；Wherein described synchronization frequency division clock generation circuit includes the first d type flip flop（101）With the second d type flip flop（102）, wherein：First d type flip flop（101）Input end of clock be connected to the high frequency clock signal（clk_f）, the first D touches Send out device（101）Positive output end export the 4th sub-frequency clock signal（clk4）And it is connected to second d type flip flop （102）Data input pin, first d type flip flop（101）Reversed-phase output export second sub-frequency clock signal （clk2）；Second d type flip flop（102）Input end of clock be connected to the high frequency clock signal（clk_f）, the 2nd D touches Send out device（102）Positive output end export first sub-frequency clock signal（clk1）, second d type flip flop（102）It is anti- Phase output terminal exports the three frequency division clock signal（clk3）And it is connected to first d type flip flop（101）Data input End.
- 2. circuit as claimed in claim 1, it is characterised in that：The data synchronization circuit（20）Including the first d type flip flop group （201）With the second d type flip flop group（202）, wherein：The first d type flip flop group（201）Input end of clock be connected to the inversion signal of low-frequency clock signal（clk0B）, institute State the first d type flip flop group（201）Data input pin be connected to the input data D<7:0>, the first d type flip flop group （201）Positive output end be connected to the second d type flip flop group（202）Data input pin；The second d type flip flop group（202）Input end of clock be connected to first sub-frequency clock signal（clk1）, described 2-D trigger group（202）Positive output end be the data synchronization circuit（20）Data output end and export synchrodata dataout<7:0>。
- 3. circuit as claimed in claim 1, it is characterised in that：The control signal generation circuit（40）Including the first NAND gate （400）, the second NAND gate（403）, the 3rd NAND gate（405）, the 4th NAND gate（409）, the first NOT gate（401）, the second NOT gate （404）, the 3rd NOT gate（406）With the 4th NOT gate（410）, wherein：First NAND gate（400）Two input terminals be connected respectively to first sub-frequency clock signal（clk1）With it is described 4th sub-frequency clock signal（clk4）, first NAND gate（400）Output terminal export the 3rd control signal inversion signal （selB<3>）And it is connected to first NOT gate（401）Input terminal, first NOT gate（401）Output terminal output the 3rd Control signal（sel<3>）；Second NAND gate（403）Two input terminals be connected respectively to first sub-frequency clock signal（clk1）With it is described Second sub-frequency clock signal（clk2）, second NAND gate（403）Output terminal output second control signal inversion signal （selB<2>）And it is connected to second NOT gate（404）Input terminal, second NOT gate（404）Output terminal output second Control signal（sel<2>）；3rd NAND gate（405）Two input terminals be connected respectively to the three frequency division clock signal（clk3）With it is described Second sub-frequency clock signal（clk2）, the 3rd NAND gate（405）Output terminal output first control signal inversion signal （selB<1>）And it is connected to the 3rd NOT gate（406）Input terminal, the 3rd NOT gate（406）Output terminal output first Control signal（sel<1>）；4th NAND gate（409）Two input terminals be connected respectively to the three frequency division clock signal（clk3）With it is described 4th sub-frequency clock signal（clk4）, the 4th NAND gate（409）Output terminal export the 0th control signal inversion signal （selB<0>）And it is connected to the 4th NOT gate（410）Input terminal, the 4th NOT gate（410）Output terminal output the 0th Control signal（sel<0>）.
- 4. circuit as claimed in claim 2, it is characterised in that：The parallel-serial conversion output circuit（30）Including the first transmission gate Group（300）, the second transmission gate group（301）, 3d flip-flop（302）, four d flip-flop（303）, the 5th d type flip flop（304） With multiple selector circuit（305）, wherein：The first transmission gate group（300）Input terminal be connected to the synchrodata dataout<7:0>In odd bits, institute State the first transmission gate group（300）Output terminal be connected to the 3d flip-flop（302）Data input pin, it is described first pass Defeated door group（300）The first control terminal be connected to the control signal sel<3:0>, the first transmission gate group（300）Second Control terminal is connected to the inversion signal selB of the control signal<3:0>；The 3d flip-flop（302）Input end of clock be connected to the inversion signal of the high frequency clock signal（clk_fB）, The 3d flip-flop（302）Positive output end be connected to the multiple selector circuit（305）First input end；The second transmission gate group（301）Input terminal be connected to the synchrodata dataout<7:0>In zero-bit and idol Numerical digit, the second transmission gate group（301）Output terminal be connected to the four d flip-flop（303）Data input pin, it is described Second transmission gate group（301）The first control terminal be connected to the control signal sel<3:0>, the second transmission gate group（301） The second control terminal be connected to the inversion signal selB of the control signal<3:0>；The four d flip-flop（303）Input end of clock be connected to the inversion signal of the high frequency clock signal（clk_fB）, The four d flip-flop（303）Positive output end be connected to the 5th d type flip flop（304）Data input pin；5th d type flip flop（304）Input end of clock be connected to the high frequency clock signal（clk_f）, the 5th D touches Send out device（304）Positive output end be connected to the multiple selector circuit（305）The second input terminal；The multiple selector circuit（305）The first control terminal be connected to the high frequency clock signal（clk_f）, the multichannel Selector circuit（305）The second control terminal be connected to the inversion signal of the high frequency clock signal（clk_fB）.
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| CN201410485272.5A CN104283561B (en) | 2014-09-22 | 2014-09-22 | A kind of asynchronous clock parallel-serial conversion half period output circuit |
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| CN107425844B (en) * | 2017-07-17 | 2020-09-11 | 北京时代民芯科技有限公司 | Configurable clock buffer suitable for SRAM type FPGA |
| CN111224658A (en) * | 2020-01-16 | 2020-06-02 | 电子科技大学 | Design method of parallel data-to-serial data conversion circuit |
| CN113364468A (en) * | 2021-06-24 | 2021-09-07 | 成都纳能微电子有限公司 | Serial-to-parallel conversion alignment circuit and method |
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