CN107943205B - Circuit and method for calculating clock period by using delay chain in DDR (double data rate) comprehensive physical layer - Google Patents
Circuit and method for calculating clock period by using delay chain in DDR (double data rate) comprehensive physical layer Download PDFInfo
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Abstract
The invention relates to a technology for calculating a clock period by a delay chain in a DDR (double data rate) comprehensive physical layer. The invention aims to automatically and precisely measure the clock period of an input clock so as to meet the flexibility of measuring clocks under different processes, and provides a circuit and a method for calculating the clock period by using a delay chain in a DDR (double data rate) comprehensive physical layer, wherein the technical scheme is as follows: the first clock obtains a first output signal after passing through the first clock phase detection register and the second clock phase detection register; the second clock obtains a second output signal after passing through a third clock phase detection register and a fourth clock phase detection register; adjusting the delay value set by the main delay chain to align the rising edge of the input clock with the rising edge of the second clock, so that the value of the first output signal is 1, the value of the second clock signal is 0, and the main delay chain and the auxiliary delay chain lock the input clock at the moment; and adding the actual delay values of the adjusted main delay chain and the adjusted auxiliary delay chain to obtain the final clock period.
Description
Technical Field
The invention relates to a delay chain clock period measuring technology, in particular to a technology for calculating a clock period by using a delay chain in a DDR (double data rate) comprehensive physical layer.
Background
Nowadays, the memory is diversified, but Double Data Rate (DDR) memory still dominates, and a stable and efficient DDR physical layer is necessary to process data stream of up to 2 Gb/s. If the DDR physical layer is a synthesizable physical layer, great flexibility is brought to the design because the delay chain of the important components in the synthesizable physical layer exists in the design in the form of RTL code, which allows the delay circuit to be used in circuits of various technologies. The DDR clock has multiple clock frequencies such as 533Mhz,667Mhz, and 800Mhz, and it becomes an important issue that the delay chain can automatically measure the clock.
Disclosure of Invention
The invention aims to provide a circuit and a method for calculating a clock period by using a delay chain in a DDR (double data rate) comprehensive physical layer, which can automatically measure the clock period of an input clock with high precision so as to meet the requirement of measuring the flexibility of clocks under different processes.
The invention solves the technical problem, and adopts the technical scheme that: the DDR can synthesize the circuit that calculates the clock cycle with the delay chain in the physical layer, including the input clock, characterized by, also include the master delay chain, the auxiliary delay chain, the first clock phase detection register, the second clock phase detection register, the third clock phase detection register and the fourth clock phase detection register, the said input clock is connected with clock end of the first to fourth clock phase detection register separately, the input clock is connected with input end of the master delay chain, the output end of the master delay chain is connected with input end of the auxiliary delay chain, the output end of the auxiliary delay chain is connected with signal end of the third clock phase detection register, the output end of the third clock phase detection register is connected with signal end of the fourth clock phase detection register, the signal of the output end of the fourth clock phase detection register is the second output signal, the output end of the master delay chain is connected with signal end of the first clock phase detection register, the output end of the first clock phase detection register is connected with the signal end of the second clock phase detection register, and the output signal of the output end of the second clock phase detection register is a first output signal.
In particular, the main delay chain sets a delay value that covers at least half a period of the input clock.
Further, the main delay chain includes 128 stages of delay devices.
In particular, the input clock is to minimize clock skew.
Still further, the delay value set by the secondary delay chain spans at least the clock edge metastability of the input clock.
In particular, the secondary delay chain includes 8 stages of delay devices.
A method for calculating a clock period by using a delay chain in a DDR synthesizable physical layer is applied to a circuit for calculating a clock period by using a delay chain in a DDR synthesizable physical layer, and is characterized by comprising the following steps:
step 1, an input clock passes through a main delay chain to obtain a first clock;
step 2, the first clock obtains a second clock after passing through the auxiliary delay chain;
step 3, the first clock obtains a first output signal after passing through the first clock phase detection register and the second clock phase detection register;
step 4, the second clock obtains a second output signal after passing through a third clock phase detection register and a fourth clock phase detection register;
step 5, adjusting a delay value set by the main delay chain to align a rising edge of the input clock with a rising edge of the second clock, so that the value of the first output signal is 1, the value of the second clock signal is 0, and the main delay chain and the auxiliary delay chain lock the input clock at the moment;
and 6, adding the actual delay value of the adjusted main delay chain and the actual delay value of the auxiliary delay chain to obtain the final clock period.
Specifically, in step 1, the main delay chain includes 128 stages of delay devices.
Further, in step 2, the sub-delay chain includes 8 stages of delay devices.
Specifically, in step 5, if the delay value set by the main delay chain and the delay value set by the auxiliary delay chain are enough to cover the whole period, the main delay chain is in the full period mode, and the sum of the actual delay value of the main delay chain and the actual delay value of the auxiliary delay chain is the whole period of the input clock; if the frequency of the input clock is low enough to make the delay value set by the main delay chain and the delay value set by the auxiliary delay chain not cover the whole period, so that the first output signal and the second output signal cannot meet the condition that the value of the first output signal is 1 and the value of the second output signal is 0, at the moment, the main delay chain can automatically switch to a half-period mode, in the half-period mode, the main delay chain locks the input clock when the second clock reaches the half period of the input clock, and at the moment, 2 times of the sum of the actual delay value of the main delay chain and the actual delay value of the auxiliary delay chain is the whole period of the input clock; if the clock frequency is as low as the delay value set by the main delay chain and the delay value set by the auxiliary delay chain can not sample for half a cycle, the delay value set by the main delay chain is adjusted to be maximum, the mode is called a saturation mode, the input clock rate is slow, and the other delay chains can measure the cycle of the input clock according to default settings.
The circuit and the method for calculating the clock period by using the delay chain in the DDR synthesizable physical layer have the advantages that the circuit and the method for calculating the clock period by using the delay chain in the DDR synthesizable physical layer can automatically adapt to input clocks with various frequencies, the flexibility of the DDR synthesizable physical layer is improved, and meanwhile, the circuit for measuring the clock can be used in circuits of various processes.
Drawings
FIG. 1 is a circuit diagram of a DDR integrated physical layer with delay chain clock cycle calculation according to the present invention.
Wherein DLM is a master delay chain, DLR is a slave delay chain, FF1-0 is a first clock phase detection register, FF1-1 is a second clock phase detection register, FF2-0 is a third clock phase detection register, FF2-1 is a fourth clock phase detection register, IN1 is an input terminal of the master delay chain, OUT1 is an output terminal of the master delay chain, IN2 is an input terminal of the slave delay chain, OUT2 is an output terminal of the slave delay chain, D1 is a signal terminal of the first clock phase detection register, Q1 is an output terminal of the first clock phase detection register, CLK1 is a clock terminal of the first clock phase detection register, D2 is a signal terminal of the second clock phase detection register, Q2 is an output terminal of the second clock phase detection register, CLK2 is a clock terminal of the second clock phase detection register, D3 is a signal terminal of the third clock phase detection register, q3 is the output terminal of the third clock phase detection register, CLK3 is the clock terminal of the third clock phase detection register, D4 is the signal terminal of the fourth clock phase detection register, Q4 is the output terminal of the fourth clock phase detection register, and CLK4 is the clock terminal of the fourth clock phase detection register.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.
The DDR can synthesize the circuit which calculates the clock cycle with the delay chain in the physical layer and is made up of input clock, main delay chain, vice delay chain, the first clock phase detection register, the second clock phase detection register, the third clock phase detection register and the fourth clock phase detection register, its circuit structure chart is shown in figure 1, wherein, the input clock connects with the clock end of the first to the fourth clock phase detection register separately, the input clock connects with the input end of the main delay chain, the output end of the main delay chain connects with the input end of the vice delay chain, the output end of the vice delay chain connects with the signal end of the third clock phase detection register, the output end of the third clock phase detection register connects with the signal end of the fourth clock phase detection register, the signal of the output end of the fourth clock phase detection register is the second output signal, the output end of the main delay chain is connected with the signal end of the first clock phase detection register, the output end of the first clock phase detection register is connected with the signal end of the second clock phase detection register, and the output signal of the output end of the second clock phase detection register is a first output signal.
A method for calculating a clock period by using a delay chain in a DDR (double data rate) comprehensive physical layer is applied to a circuit for calculating the clock period by using the delay chain in the DDR comprehensive physical layer and comprises the following steps:
step 1, an input clock passes through a main delay chain to obtain a first clock;
step 2, the first clock obtains a second clock after passing through the auxiliary delay chain;
step 3, the first clock obtains a first output signal after passing through the first clock phase detection register and the second clock phase detection register;
step 4, the second clock obtains a second output signal after passing through a third clock phase detection register and a fourth clock phase detection register;
step 5, adjusting a delay value set by the main delay chain to align a rising edge of the input clock with a rising edge of the second clock, so that the value of the first output signal is 1, the value of the second clock signal is 0, and the main delay chain and the auxiliary delay chain lock the input clock at the moment;
and 6, adding the actual delay value of the adjusted main delay chain and the actual delay value of the auxiliary delay chain to obtain the final clock period.
Examples
The DDR circuit for calculating clock period by using delay chain in physical layer of the embodiment of the invention comprises an input clock, a main delay chain, a sub-delay chain, a first clock phase detection register, a second clock phase detection register, a third clock phase detection register and a fourth clock phase detection register, wherein the input clock is respectively connected with the clock ends of the first to fourth clock phase detection registers, the input clock is connected with the input end of the main delay chain, the output end of the main delay chain is connected with the input end of the sub-delay chain, the output end of the sub-delay chain is connected with the signal end of the third clock phase detection register, the output end of the third clock phase detection register is connected with the signal end of the fourth clock phase detection register, the signal of the output end of the fourth clock phase detection register is a second output signal, the output end of the main delay chain is connected with the signal end of the first clock phase detection register, the output end of the first clock phase detection register is connected with the signal end of the second clock phase detection register, and the output signal of the output end of the second clock phase detection register is a first output signal.
In the circuit, the delay value set by the main delay chain at least covers a half period of the input clock; the main delay chain preferably comprises 128 stages of delay devices, and can be freely set according to actual needs; inputting a clock to minimize clock skew; the delay value set by the secondary delay chain at least spans the clock edge metastability of the input clock; the secondary delay chain preferably comprises 8 stages of delay devices and can be freely set according to actual needs.
A method for calculating a clock period by using a delay chain in a DDR synthesizable physical layer is applied to a circuit for calculating a clock period by using a delay chain in a DDR synthesizable physical layer, and comprises the following steps:
step 1, obtaining a first clock after an input clock passes through a main delay chain, wherein the main delay chain can preferably comprise 128 stages of delay devices;
step 2, the first clock obtains a second clock after passing through the auxiliary delay chain, preferably, the auxiliary delay chain can comprise 8 stages of delay devices;
step 3, the first clock obtains a first output signal after passing through the first clock phase detection register and the second clock phase detection register;
step 4, the second clock obtains a second output signal after passing through a third clock phase detection register and a fourth clock phase detection register;
step 5, adjusting a delay value set by the main delay chain to align a rising edge of the input clock with a rising edge of the second clock, so that the value of the first output signal is 1, the value of the second clock signal is 0, and the main delay chain and the auxiliary delay chain lock the input clock at the moment;
and 6, adding the actual delay value of the adjusted main delay chain and the actual delay value of the auxiliary delay chain to obtain the final clock period.
In the method, in step 5, if the delay value set by the main delay chain and the delay value set by the auxiliary delay chain are sufficient to cover the whole period, the main delay chain is in a full period mode, and the sum of the actual delay value of the main delay chain and the actual delay value of the auxiliary delay chain is the whole period of the input clock; if the frequency of the input clock is low enough to make the delay value set by the main delay chain and the delay value set by the auxiliary delay chain not cover the whole period, so that the first output signal and the second output signal cannot meet the condition that the value of the first output signal is 1 and the value of the second output signal is 0, at the moment, the main delay chain can automatically switch to a half-period mode, in the half-period mode, the main delay chain locks the input clock when the second clock reaches the half period of the input clock, and at the moment, 2 times of the sum of the actual delay value of the main delay chain and the actual delay value of the auxiliary delay chain is the whole period of the input clock; if the clock frequency is as low as the delay value set by the main delay chain and the delay value set by the auxiliary delay chain can not sample for half a cycle, the delay value set by the main delay chain is adjusted to be maximum, the mode is called a saturation mode, the input clock rate is slow, and the other delay chains can measure the cycle of the input clock according to default settings.
Claims (10)
1. A DDR can synthesize the circuit that calculates the clock cycle with the delay chain in the physical layer, including the input clock, characterized by, also include the master delay chain, the auxiliary delay chain, the first clock phase detection register, the second clock phase detection register, the third clock phase detection register and the fourth clock phase detection register, the said input clock is connected with clock end of the first to fourth clock phase detection register separately, the input clock is connected with input end of the master delay chain, the output end of the master delay chain is connected with input end of the auxiliary delay chain, the output end of the auxiliary delay chain is connected with signal end of the third clock phase detection register, the output end of the third clock phase detection register is connected with signal end of the fourth clock phase detection register, the signal of the output end of the fourth clock phase detection register is the second output signal, the output end of the master delay chain is connected with signal end of the first clock phase detection register, the output end of the first clock phase detection register is connected with the signal end of the second clock phase detection register, and the output signal of the output end of the second clock phase detection register is a first output signal.
2. The DDR circuit with a delay chain to compute a clock cycle in the physical layer of claim 1, wherein the master delay chain sets a delay value that covers at least half a cycle of the input clock.
3. The DDR circuit to compute clock cycles with a delay chain in the physical layer of claim 2, wherein the main delay chain comprises 128 stages of delay devices.
4. The DDR scalable physical layer of claim 1, wherein the input clock is a minimum clock skew.
5. The DDR device with delay chain in integrated physical layer of claim 1, wherein the delay value set by the secondary delay chain spans at least a clock edge metastability of the input clock.
6. The DDR synthesizable physical layer clock cycle calculation circuit with delay chains as claimed in claim 5, wherein the secondary delay chain comprises 8 stages of delay devices.
7. A method for calculating a clock cycle by using a delay chain in a DDR synthesizable physical layer, which is applied to the circuit for calculating a clock cycle by using a delay chain in a DDR synthesizable physical layer according to any one of claims 1 to 6, comprising the following steps:
step 1, an input clock passes through a main delay chain to obtain a first clock;
step 2, the first clock obtains a second clock after passing through the auxiliary delay chain;
step 3, the first clock obtains a first output signal after passing through the first clock phase detection register and the second clock phase detection register;
step 4, the second clock obtains a second output signal after passing through a third clock phase detection register and a fourth clock phase detection register;
step 5, adjusting a delay value set by the main delay chain to align a rising edge of the input clock with a rising edge of the second clock, so that the value of the first output signal is 1, the value of the second clock signal is 0, and the main delay chain and the auxiliary delay chain lock the input clock at the moment;
and 6, adding the actual delay value of the adjusted main delay chain and the actual delay value of the auxiliary delay chain to obtain the final clock period.
8. The method for calculating clock period by using delay chain in DDR SYNC physical layer as claimed in claim 7, wherein in step 1, said master delay chain comprises 128 stages of delay devices.
9. The method for calculating clock period by using delay chain in DDR SYNC physical layer as claimed in claim 7, wherein in step 2, said secondary delay chain comprises 8 stages of delay devices.
10. The method for calculating clock period by using delay chain in DDR SYNC physical layer as claimed in claim 7, wherein in step 5, if the delay value set by the main delay chain and the delay value set by the sub-delay chain are enough to cover the whole period, the main delay chain is in full period mode, and the sum of the actual delay value of the main delay chain and the actual delay value of the sub-delay chain is the whole period of the input clock; if the frequency of the input clock is low enough to make the delay value set by the main delay chain and the delay value set by the auxiliary delay chain not cover the whole period, so that the first output signal and the second output signal cannot meet the condition that the value of the first output signal is 1 and the value of the second output signal is 0, at the moment, the main delay chain can automatically switch to a half-period mode, in the half-period mode, the main delay chain locks the input clock when the second clock reaches the half period of the input clock, and at the moment, 2 times of the sum of the actual delay value of the main delay chain and the actual delay value of the auxiliary delay chain is the whole period of the input clock; if the clock frequency is as low as the delay value set by the main delay chain and the delay value set by the auxiliary delay chain can not sample for half a cycle, the delay value set by the main delay chain is adjusted to be maximum, the mode is called a saturation mode, in this case, the input clock rate is slow, and the other delay chains can measure the cycle of the input clock according to default settings.
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