CN104658596B

CN104658596B - A kind of antimierophonic delay counter

Info

Publication number: CN104658596B
Application number: CN201510052160.5A
Authority: CN
Inventors: 亚历山大
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2015-01-30
Filing date: 2015-01-30
Publication date: 2018-01-19
Anticipated expiration: 2035-01-30
Also published as: CN104658596A

Abstract

The present invention relates to a kind of antimierophonic delay counter, including δ fb feedback delay circuits, sample circuit, digital filter, input counter, output counter and FIFO.The present invention solves the position that existing memory latency counter has output pointer to input pointer and made a mistake, technical problem of the data of reading instruction in the cycle output of mistake, the present invention is by increasing digital filter, ensure that the position that hold signals occur will not change, so as to ensure that the appearance of hold signal period property will not mistake with the phase relation of change output pointer to the input pointer of voltage/temperature/technique.Implementation is simple.

Description

A kind of antimierophonic delay counter

Technical field

The present invention relates to semiconductor DRAM memory design field, and in particular to a kind of antimierophonic delay counter.

Background technology

Computer and various electronic equipments are widely used in the various aspects of the modern life, to memory article (DRAM Memory) demand is increasing.People are more and more faster to rate request, and the clock of memory is with regard to less and less.So noise pair The influence of properties of product is increasing.

The delay counter of memory is the reading instruction for realizing memory.Whenever a reading instruction, user it is expected Rising edge clock after a fixed delay period (user can configure) obtains desired data, is as shown in Figure 1 DRAM Memory read instructions operation chart, delay period is 6 in figure.In order to realize above-mentioned read operation, DRAM memory typically divides 3 steps Complete：

Step A：Memory receives outside reading instruction, produces internal clocking clk_rcv, internal clocking clk_rcv and outside Clock clk delay is δ 0；

Step B：Counted using internal clocking

Step C：Terminate output data in counter, the effective time is δ 1 from internal clocking to data

As shown in Fig. 2 have two it is apparent the problem of：

1st, output data can not align with external clock clk；

2nd, as the clock cycle is less and less, internal latency (δ 0+ δ 1) is possible to be more than a clock cycle, such as Fig. 2 numbers According to being possible to occur in the 5/6/7... clock cycle.

In order to solve the above problems, DRAM memory introduces digital delay phase-locked loop DLL, produces internal clocking clk_rcv A delayed clock clk_dll, delayed clock clk_dll and external clock clk phase difference be δ 1, if as shown in figure 3, Delayed clock clk_dll caused by digital delay phase-locked loop DLL and internal clocking clk_rcv delay δ dll, meet δ dll= N*Tck- (δ 0+ δ 1), it is so perfectly aligned by the delayed clock clk_dll data exported and external clock.

As shown in Figure 4, Figure 5, DRAM delay counters are defeated for ensureing using δ fb delay circuits one hold signal of generation Go out pointer (output pointer) to the sequential relationship of input pointer (input pointer).If δ fb=δ 0+ δ 1, then Clk_fb and clk_rcv phases are with regard to perfectly aligned.After user sets DRAM delay periods, hold signals will the cycle Property appearance to ensure that the phase relation of the change output pointer with voltage/temperature/technique to input pointer will not mistake. Ideally (voltage/temperature/technique is constant), the position that hold signals occur will not change, it is same input pointer and The position of output pointer will not also change as shown in Figure 6.

But when noise occurs for system, hold signals produce to be influenceed to make a mistake by foundation/retention time. So as to cause the position of output pointer to input pointer to be made a mistake, the data for ultimately resulting in reading instruction export in the cycle of mistake As shown in Figure 7.

The content of the invention

The position that output pointer to input pointer in order to solve existing memory latency counter be present is made a mistake, and is read The data of instruction are in the technical problem of the cycle output of mistake, a kind of antimierophonic delay counter of present invention offer.

The technical solution of the present invention：

A kind of antimierophonic delay counter, it is characterized in that：Including

δ fb feedback delay circuits：Hold signals are produced for carrying out processing to delayed clock clk_dll；

Sample circuit：For being sampled to hold signals, the input pointer of current hold set and upper n times hold are exported Set inputs pointer value；

Digital filter：Input pointer and the upper n times hold set for receiving the current hold set of sample circuit output are defeated Enter pointer value, and being compared output allows hold set to input pointer：

Input counter：For being counted to allowing hold set to input pointer, output input pointer；

Output counter：For carrying out counting output output pointer to delayed clock clk_dll；

FIFO：For receiving input pointer, output pointer and read pointer, and export the reading instruction after delay counter.

Hold signals caused by above-mentioned δ fb feedback delay circuits are used for ensureing that the sequential of output pointer to input pointer is closed System.

N in above-mentioned upper n times hold set input pointer value meets：N ＞ 0.

Advantage for present invention：

The present invention ensures that the position that hold signals occur will not change, so as to ensure by increasing digital filter The appearance of hold signal period property will not with the phase relation of change output pointer to the input pointer of voltage/temperature/technique Mistake.Implementation is simple.

Brief description of the drawings

Fig. 1 is DRAM memory reading instruction operation chart；

Fig. 2 is the schematic diagram of reading instruction exploded view one；

Fig. 3 is the schematic diagram of reading instruction exploded view two；

Fig. 4 is DLL basic principle schematics；

Fig. 5 is the basic schematic diagram of delay counter；

Fig. 6 is correct hold signal schematic representations；

Fig. 7 is the hold signal schematic representations of mistake；

Fig. 8 is the structural representation of delay counter of the present invention.

Embodiment

DRAM memory introduces digital delay phase-locked loop DLL, produces an internal clocking clk_rcv delayed clock clk_ Dll, delayed clock clk_dll and external clock clk phase difference are δ 1, if postponed caused by digital delay phase-locked loop DLL Clock clk_dll and internal clocking clk_rcv delay δ dll, meet δ dll=N*Tck- (δ 0+ δ 1), so by delayed clock The data and external clock of clk_dll outputs are perfectly aligned.

DRAM delay counters produce hold signal using δ fb feedback delay circuits and are used for ensureing output pointer to defeated Enter the sequential relationship of pointer.If δ fb=δ 0+ δ 1, then clk_fb and clk_rcv phases are with regard to perfectly aligned.Whenever user After setting DRAM delay periods, hold signals will periodically occur to ensure as the change of voltage/temperature/technique is defeated The phase relation for going out pointer to input pointer will not mistake.(voltage/temperature/technique is constant) in the ideal case, hold signals The position of appearance will not change；But when noise occurs for system, hold signals were produced by foundation/retention time Influence can make a mistake.Digital filter is added when hold home position signals input pointer.

As shown in figure 8, a kind of antimierophonic delay counter, including δ fb feedback delay circuits：For to delayed clock Clk_dll carries out processing and produces hold signals：Sample circuit：For being sampled to hold signals, current hold set is exported Input pointer and upper n times hold set input pointer value (N ＞ 0)；Digital filter：Receive the current of sample circuit output The input pointer of hold set and upper n times hold set input pointer value, and being compared output allows hold set input to refer to Pin：Input counter：For being counted to allowing hold set to input pointer, output input pointer；Output counter：For Delayed clock clk_dll is carried out to count output output pointer；FIFO：For receiving input pointer, output pointer and reading to refer to Pin, and export the reading instruction after delay counter.

Claims

A kind of 1. antimierophonic delay counter, it is characterised in that：Including

δ fb feedback delay circuits：Hold signals are produced for carrying out processing to delayed clock clk_dll；

Sample circuit：For being sampled to hold signals, the input pointer of current hold set and upper n times hold set are exported Input pointer value；

Digital filter：The input pointer and upper n times hold set input for receiving the current hold set of sample circuit output refer to Pin value, and being compared output allows hold set to input pointer：

Input counter：For being counted to allowing hold set to input pointer, output input pointer；

Output counter：For carrying out counting output output pointer to delayed clock clk_dll；

FIFO：For receiving input pointer, output pointer and read pointer, and export the reading instruction after delay counter.
2. antimierophonic delay counter according to claim 1, it is characterised in that：The δ fb feedback delay circuits production Raw hold signals are used for ensureing output pointer to the sequential relationship of input pointer.
3. antimierophonic delay counter according to claim 1 or 2, it is characterised in that：The upper n times hold set is defeated The N entered in pointer value meets：N ＞ 0.