CN1770448A - 半导体集成电路和其设计方法 - Google Patents
半导体集成电路和其设计方法 Download PDFInfo
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- CN1770448A CN1770448A CNA2005100799227A CN200510079922A CN1770448A CN 1770448 A CN1770448 A CN 1770448A CN A2005100799227 A CNA2005100799227 A CN A2005100799227A CN 200510079922 A CN200510079922 A CN 200510079922A CN 1770448 A CN1770448 A CN 1770448A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 177
- 238000000034 method Methods 0.000 title claims description 119
- 238000013461 design Methods 0.000 title claims description 110
- 230000006870 function Effects 0.000 claims abstract description 86
- 239000011159 matrix material Substances 0.000 claims description 278
- 238000012360 testing method Methods 0.000 claims description 46
- 230000008859 change Effects 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 7
- 235000016936 Dendrocalamus strictus Nutrition 0.000 claims description 5
- 238000009826 distribution Methods 0.000 claims description 5
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (39)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004322730 | 2004-11-05 | ||
JP322730/2004 | 2004-11-05 | ||
JP2005061442A JP2006156929A (ja) | 2004-04-19 | 2005-03-04 | 半導体集積回路及びその設計方法 |
JP061442/2005 | 2005-03-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1770448A true CN1770448A (zh) | 2006-05-10 |
CN1770448B CN1770448B (zh) | 2010-10-06 |
Family
ID=34941560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2005100799227A Expired - Fee Related CN1770448B (zh) | 2004-11-05 | 2005-06-27 | 半导体集成电路和其设计方法 |
Country Status (4)
Country | Link |
---|---|
EP (2) | EP1655779A3 (zh) |
KR (2) | KR100869087B1 (zh) |
CN (1) | CN1770448B (zh) |
TW (1) | TWI303481B (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101320707B (zh) * | 2008-05-19 | 2010-06-09 | 深圳市国微电子股份有限公司 | 结构化专用集成电路设置和生产方法 |
CN102217190A (zh) * | 2008-10-09 | 2011-10-12 | 阿尔特拉公司 | 用于提供备选导体以连接振荡器电路中的部件的技术 |
CN105760558A (zh) * | 2014-12-16 | 2016-07-13 | 京微雅格(北京)科技有限公司 | Fpga芯片中多输入查找表的布局方法 |
CN106407496A (zh) * | 2015-07-30 | 2017-02-15 | 三星电子株式会社 | 设计半导体装置的布图的方法和制造半导体装置的方法 |
CN107547200A (zh) * | 2017-05-04 | 2018-01-05 | 华邦电子股份有限公司 | 半导体装置、半导体装置制造方法及特有信息的产生方法 |
USRE49780E1 (en) | 2015-07-30 | 2024-01-02 | Samsung Electronics Co., Ltd. | Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8042075B2 (en) | 2009-03-25 | 2011-10-18 | International Business Machines Corporation | Method, system and application for sequential cofactor-based analysis of netlists |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6124250A (ja) * | 1984-07-13 | 1986-02-01 | Nippon Gakki Seizo Kk | 半導体集積回路装置 |
JPH0230163A (ja) | 1988-07-20 | 1990-01-31 | Fujitsu Ltd | マスタスライス型半導体集積回路装置およびその製造方法 |
JP2666807B2 (ja) * | 1988-06-16 | 1997-10-22 | 富士通株式会社 | 集積回路パターンの形成方法 |
US5224057A (en) * | 1989-02-28 | 1993-06-29 | Kabushiki Kaisha Toshiba | Arrangement method for logic cells in semiconductor IC device |
US5206529A (en) * | 1989-09-25 | 1993-04-27 | Nec Corporation | Semiconductor integrated circuit device |
US5459340A (en) * | 1989-10-03 | 1995-10-17 | Trw Inc. | Adaptive configurable gate array |
JPH0743742B2 (ja) * | 1990-09-12 | 1995-05-15 | 株式会社日立製作所 | 自動配線方法 |
JP3076410B2 (ja) * | 1991-07-08 | 2000-08-14 | 株式会社東芝 | 半導体集積回路の設計方法 |
JPH06163860A (ja) | 1992-11-17 | 1994-06-10 | Fujitsu Ltd | ゲートアレイとその製造方法 |
US5796129A (en) * | 1993-08-03 | 1998-08-18 | Seiko Epson Corp. | Master slice type integrated circuit system having block areas optimized based on function |
JPH07249748A (ja) * | 1994-03-14 | 1995-09-26 | Fujitsu Ltd | マスタースライス型lsiの設計装置 |
US5723883A (en) * | 1995-11-14 | 1998-03-03 | In-Chip | Gate array cell architecture and routing scheme |
JP3260622B2 (ja) * | 1996-04-15 | 2002-02-25 | 株式会社東芝 | 半導体装置の製造方法 |
JP2828026B2 (ja) * | 1996-04-25 | 1998-11-25 | 日本電気株式会社 | 自動配線方法 |
JP2885213B2 (ja) * | 1997-01-23 | 1999-04-19 | 日本電気株式会社 | 半導体集積回路 |
JPH10321728A (ja) * | 1997-05-19 | 1998-12-04 | Fujitsu Ltd | 半導体集積回路のレイアウトシステムにおける階層化配線処理方法および階層化配線処理プログラムを記録した媒体 |
US6330707B1 (en) * | 1997-09-29 | 2001-12-11 | Matsushita Electric Industrial Co., Ltd. | Automatic routing method |
JP3123974B2 (ja) * | 1998-03-19 | 2001-01-15 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路の配線方法 |
US6412102B1 (en) * | 1998-07-22 | 2002-06-25 | Lsi Logic Corporation | Wire routing optimization |
WO2000005764A1 (fr) * | 1998-07-23 | 2000-02-03 | Seiko Epson Corporation | Circuit integre a semiconducteur avec integration sur la plaquette et procede de conception correspondant |
JP3420089B2 (ja) * | 1998-11-04 | 2003-06-23 | Necエレクトロニクス株式会社 | 電子デバイス並びに半導体装置、及び電極形成方法 |
JP3313668B2 (ja) * | 1999-07-07 | 2002-08-12 | エヌイーシーマイクロシステム株式会社 | データ処理装置、情報記憶媒体 |
JP2001110903A (ja) * | 1999-10-13 | 2001-04-20 | Matsushita Electric Ind Co Ltd | 集積回路のレイアウト構造、並びにcmos回路のレイアウト設計方法および設計装置 |
US7170115B2 (en) * | 2000-10-17 | 2007-01-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method of producing the same |
JP3621354B2 (ja) * | 2001-04-04 | 2005-02-16 | Necエレクトロニクス株式会社 | 半導体集積回路の配線方法及び構造 |
US7053424B2 (en) * | 2002-10-31 | 2006-05-30 | Yamaha Corporation | Semiconductor integrated circuit device and its manufacture using automatic layout |
-
2005
- 2005-06-03 EP EP05253415A patent/EP1655779A3/en not_active Withdrawn
- 2005-06-03 EP EP09157971A patent/EP2079109A3/en not_active Withdrawn
- 2005-06-06 TW TW094118559A patent/TWI303481B/zh not_active IP Right Cessation
- 2005-06-27 CN CN2005100799227A patent/CN1770448B/zh not_active Expired - Fee Related
- 2005-06-30 KR KR1020050058649A patent/KR100869087B1/ko not_active IP Right Cessation
-
2008
- 2008-01-02 KR KR1020080000169A patent/KR20080009166A/ko not_active Application Discontinuation
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101320707B (zh) * | 2008-05-19 | 2010-06-09 | 深圳市国微电子股份有限公司 | 结构化专用集成电路设置和生产方法 |
CN102217190A (zh) * | 2008-10-09 | 2011-10-12 | 阿尔特拉公司 | 用于提供备选导体以连接振荡器电路中的部件的技术 |
CN102217190B (zh) * | 2008-10-09 | 2015-12-09 | 阿尔特拉公司 | 用于提供备选导体以连接振荡器电路中的部件的技术 |
CN105760558A (zh) * | 2014-12-16 | 2016-07-13 | 京微雅格(北京)科技有限公司 | Fpga芯片中多输入查找表的布局方法 |
CN105760558B (zh) * | 2014-12-16 | 2019-04-09 | 京微雅格(北京)科技有限公司 | Fpga芯片中多输入查找表的布局方法 |
CN106407496A (zh) * | 2015-07-30 | 2017-02-15 | 三星电子株式会社 | 设计半导体装置的布图的方法和制造半导体装置的方法 |
CN106407496B (zh) * | 2015-07-30 | 2021-10-15 | 三星电子株式会社 | 设计半导体装置的布图的方法和制造半导体装置的方法 |
USRE49780E1 (en) | 2015-07-30 | 2024-01-02 | Samsung Electronics Co., Ltd. | Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same |
CN107547200A (zh) * | 2017-05-04 | 2018-01-05 | 华邦电子股份有限公司 | 半导体装置、半导体装置制造方法及特有信息的产生方法 |
CN107547200B (zh) * | 2017-05-04 | 2020-04-10 | 华邦电子股份有限公司 | 半导体装置、半导体装置制造方法及特有信息的产生方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1655779A3 (en) | 2007-10-31 |
EP1655779A2 (en) | 2006-05-10 |
TWI303481B (en) | 2008-11-21 |
TW200616202A (en) | 2006-05-16 |
KR20060049722A (ko) | 2006-05-19 |
EP2079109A2 (en) | 2009-07-15 |
CN1770448B (zh) | 2010-10-06 |
EP2079109A3 (en) | 2010-06-30 |
KR20080009166A (ko) | 2008-01-24 |
KR100869087B1 (ko) | 2008-11-18 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
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ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081031 |
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Effective date of registration: 20081031 Address after: Tokyo, Japan, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Applicant before: Fujitsu Ltd. |
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CI01 | Correction of invention patent gazette |
Correction item: Claims Correct: 29 items False: 31 items Number: 40 Volume: 26 |
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CI03 | Correction of invention patent |
Correction item: Claims Correct: 29 items False: 31 items Number: 40 Page: Description Volume: 26 |
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ERR | Gazette correction |
Free format text: CORRECT: CLAIM OF RIGHT; FROM: ITEM 31 TO: ITEM 29 |
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ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150515 |
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C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20150515 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101006 Termination date: 20170627 |