CN1755941A - 具有沟槽扩散区的mos器件及其形成方法 - Google Patents
具有沟槽扩散区的mos器件及其形成方法 Download PDFInfo
- Publication number
- CN1755941A CN1755941A CNA2005100781685A CN200510078168A CN1755941A CN 1755941 A CN1755941 A CN 1755941A CN A2005100781685 A CNA2005100781685 A CN A2005100781685A CN 200510078168 A CN200510078168 A CN 200510078168A CN 1755941 A CN1755941 A CN 1755941A
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- drain regions
- source
- conduction type
- given
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims description 28
- 238000009792 diffusion process Methods 0.000 title description 16
- 239000000463 material Substances 0.000 claims description 31
- 239000012535 impurity Substances 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 description 26
- 239000000758 substrate Substances 0.000 description 26
- 235000012431 wafers Nutrition 0.000 description 17
- 230000008859 change Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000007645 offset printing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003334 potential effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
一种MOS器件包括具有第一导电类型的半导体层和形成在所述半导体层中靠近其上表面的、具有第二导电类型的第一和第二源极/漏极区。该第一和第二源极/漏极区彼此分隔。形成在半导体层上方并与半导体层电隔离的栅极,至少部分置于第一和第二源极/漏极区之间。构造至少一个给定的第一和第二源极/漏极区,它的有效宽度基本上大于位于半导体层和给定的源极/漏极区之间的结宽度。
Description
技术领域
本发明一般涉及半导体器件,尤其是具有改善的高频性能的金属-氧化物-半导体(MOS)器件和形成该器件的方法。
背景技术
MOS器件,包括横向扩散的MOS器件(LDMOS),应用在许多领域,如无线电通讯***中的功率放大器。关于LDMOS器件的直流(DC)性能,通常希望具有低接通电阻和高跨导。低压(如,小于约10V的击穿电压)LDMOS器件的接通电阻主要取决于器件沟道区的电阻。例如,在低压LDMOS器件中,沟道电阻占器件接通总电阻的大约80%。比较起来,高压功率MOS场效应晶体管(MOSFET)器件的接通电阻主要取决于器件漂移区的电阻。
为了获得低接通电阻和/或高功率处理能力,通常需要更宽的沟道。然而,由于器件的平面特性,形成具有较宽沟道的器件会消耗更多的芯片面积。而且,器件的输出电容,它是器件的P-N结周长的函数,作为沟道宽度的函数会相应地提高。不利地是,器件输出电容的提高影响LDMOS器件的高频性能(如,大于约1GHz)。
已知的方法是,通过采用折叠栅极LDMOS结构提高LDMOS的沟道宽度却没有必然地消耗额外的芯片面积,这种方法已被Yuanzheng Zhu等发表的论文所揭示,该论文刊登在2001年12月第48卷第12期的《IEEE电子器件学报》(IEEE Transactions onElectron Devices),题目是“具有低接通电阻和高跨导的折叠栅极LDMOS晶体管”(Folded Gate LDMOS Transistor with LowOn-Resistance and High Transconductance),该论文在这里作为参考文献被引用。然而,尽管LDMOS器件的折叠栅极构造能制造具有降低的接通电阻而不会明显提高芯片面积的器件,这种方法在提高器件的高频性能方面基本没有用处,这是因为,如果形成的沟道区基本上是平坦的,器件的P-N结的周长从而结电容保持不变。
因此,存在对这样的MOS器件的需要,即具有改进的高频性能和接通特性而不具有通常影响传统MOS器件的一种或多种上述的缺陷。进一步希望这样的MOS器件与标准的集成电路(IC)加工技术充分兼容。
发明内容
本发明提供这样的技术,即降低MOS器件的接通电阻而没有显著提高器件的输出电容,从而提高器件的高频性能和DC性能。而且,本发明的技术能够采用与传统的CMOS兼容的加工技术制造IC器件,例如LDMOS器件。因此,制造IC器件的费用不会明显提高。
根据本发明的一个方面,MOS器件包括具有第一导电类型的半导体层和在半导体层中靠近其上表面形成的具有第二导电类型的第一和第二源极/漏极区。该第一和第二源极/漏极区彼此分开。栅极形成在半导体层上方并与半导体层电隔离,至少部分位于第一和第二源极/漏极区之间。至少构造第一和第二源极/漏极区中的给定一个,使其具有较半导体层和给定的源极/漏极区之间的结宽度大得多的有效宽度。
给定的源极/漏极区可以包括形成在半导体层中靠近其上表面的多个沟槽。这样安排沟槽的间距,以使分隔两个相邻沟槽的壁基本上由第二导电类型的材料构成。这样,与MOS器件相关的结电容基本上不依赖于沟槽的深度,而是给定源极/漏极区的线性宽度的函数。因此,有利地,降低了MOS器件的接通电阻而器件的结电容没有明显的提高。
根据本发明的又一个方面,提供一种形成金属-氧化物-半导体器件的方法,它包括下面的步骤:在第二导电类型的半导体层中形成第一导电类型的第一和第二源极/漏极区,该第一和第二源极/漏极区靠近半导体层的上表面形成并彼此分开;在半导体层上方形成栅极并使之与半导体层电隔离,该栅极至少部分形成在第一和第二源极/漏极区之间。使第一和第二源极/漏极区中的至少给定一个形成为,其有效宽度较位于半导体层和给定的源极/漏极区之间的结的宽度大得多。
从下面对示例实施例详细的描述并结合附图,本发明的这些和其它的特点和优点将变得明显。
附图说明
图1是显示可以采用本发明技术的示范性的MOS器件的至少一部分的俯视图。
图2是显示图1所示的MOS器件的至少一部分的沿A-A′线的横截面图。
图3是显示图1所示的MOS器件的至少一部分的沿A-A′线的横截面图,其中采用了本发明的技术。
图4是根据本发明的又一个实施例形成的示例MOS器件的至少一部分的横截面图。
图5是根据本发明的第三实施例形成的示例MOS器件的至少一部分的横截面图。
图6是根据本发明的又一个实施例形成的示例MOS器件的至少一部分的横截面图。
图7A-7D显示了根据本发明的一个实施例用于形成图4所示的示例MOS器件的示例方法的步骤。
图8A-8C显示了根据本发明的又一个实施例用于形成图6所示的示例MOS器件的示例方法的步骤。
具体实施方式
这里将参照示例的CMOS半导体制造技术描述本发明,该技术用于形成DMOS晶体管和其它的器件和/或电路。然而,应当理解的是,本发明不限于制造这种或任何给定的器件或电路。相反,本发明更适用于这样的MOS器件,它包括新颖的沟槽扩散排列,这种排列有利于提高器件的电性能(如降低的接通电阻)和高频性能而不会明显提高器件消耗的芯片面积值。
尽管这里特别参照MOS器件和互补金属-氧化物-半导体(CMOS)制造方法描述本发明的施行,但是熟悉本领域的人员可以理解,经过该变或不经改变,本发明的技术同样应用于其它的制造方法(如双极结)和/或形成其它的器件,如双极结晶体管(BJT)、垂直扩散MOS(DMOS)器件、延伸漏极MOS场效应晶体管(MOSFET)器件等,但不仅限于此。进一步,尽管这里参照N-沟道MOS器件描述本发明,熟悉本领域的人员会理解,采用简单地以相反极性替代N-沟道实施例的极性可以形成P-沟道MOS器件,和本发明的技术和优点将同样适应于替代实施例。
可以理解,附图中显示的不同的层和/或区不是按比例绘制,为了便于解释,通常用在这种集成电路结构的一个或多个一种类型的半导体层和/或区不可能在一个给定的图中明确地表示。这不意味着在实际的集成电路结构中没有明确示出的半导体层和/或区能够省略。
图1和图2分别显示了示例的MOS器件100的至少一部分的俯视图和横截面图,其中可以采用本发明技术。MOS器件100优选的包括形成在衬底112上的外延层104。衬底112通常由单晶硅形成,尽管可以采用替代材料,如锗、砷化镓等,但不仅限于此。另外,可以通过添加杂质或掺杂剂,如通过扩散或注入步骤,改变材料的导电性(如N-型或P-型)来改变衬底112。在本发明的优选实施例中,衬底112具有P-型导电性,它是重掺杂的,通常标以“+”号表示,从而可以标记为P+衬底。可以采用诸如扩散或注入的步骤向衬底材料中添加希望浓度的(如大约5×1018到大约5×1019原子/cm3)P-型杂质或掺杂剂(如硼)形成P+衬底112。外延层104优选地以已知浓度水平的P-型杂质掺杂以将选择性地将材料的导电率改变为预期值。替代地,可以采用,如传统的扩散工艺形成作为P-型扩散层的外延层104。与衬底112的掺杂浓度相比,外延层104的掺杂浓度优选地略低一些(如大约1015到大约1016原子/cm3)。
这里使用的术语“半导体层”指其它材料可以形成在其上和/或其中的任何半导体材料。半导体层可以形成在衬底112上,可以包括单一层,如外延层104,或包括不同材料的多层和/或具有不同掺杂浓度的相同材料的多层。
源极区102和漏极区106分别形成在外延层104中靠近其外表面并彼此分开。例如采用注入或扩散工艺,源极区102和漏极区106优选地被掺杂以已知浓度水平的杂质(如磷、砷等)以选择性地将材料的导电率改变到预期值。优选地,源极区102和漏极区106具有相关的与外延层104的导电类型相反的导电类型,以便于在器件中形成有源区。在本发明的优选实施例中,源极区102和漏极区106属于重掺杂的N-型导电类型,从而可以标记为N+源极和漏极区。在N+源极区102和漏极区106与P-型外延层104之间的边界在这里可以标记为P-N结。
可以理解,对于简单的MOS器件,因为该MOS器件本性上对称,因而是双向的,在MOS器件中分配源极和漏极标记基本上是随意的。因此,源极和漏极区通常分别作为第一和第二源极/漏极区,其中术语“源极/漏极”在这里代表源极区或漏极区。
栅极108形成在外延层104上方并至少部分置于源极区102和漏极区106之间。栅极108通常形成在绝缘层(未示出)上,优选地为一种氧化物(如二氧化硅),形成在至少部分外延层上以与相对源极区102和漏极区106电隔离栅极。栅极108优选地由导电材料形成,如多晶硅,尽管适合的替代材料(如金属等)可以同样地被采用。可以通过向栅极提供硅化物层(未示出)降低栅极108的电阻,这对某些高频应用中的使用尤其有益。沟道区(未示出)形成在MOS器件100的靠近栅极108的本体区(未示出)中,主要来自被施加到栅极上的正电势作用聚积的电子。尽管未示出,轻掺杂的漏极(LDD)区可以形成在外延层104中,靠近外延层的上表面并置于栅极108和漏极区106之间。
在MOS器件中希望提高导电率,从而降低接通电阻。一种提高MOS器件的导电率的方法是提高器件的有效沟道宽度Weff。为了实现此目的,多个沟槽110形成在外延层104中,每个沟槽水平地(如在基本上与衬底112平行的平面)延伸在源极区102和漏极区106之间。参照图2,其是示例的MOS器件100的至少一部分漏极区的沿图1的A-A′线的横截面图,沟槽110的存在通过提高器件的表面积基本上提高了器件的有效宽度,而没有消耗任何额外的芯片面积。例如,通过使各沟槽110的深度D基本上等于沟槽的宽度Wt,在MOS器件100中沟道区的密度加倍,导致跨导提高和接通电阻降低。在前面引用的题目为“具有低接通电阻和高跨导的折叠栅极LDMOS晶体管”的Yuanzheng Zhu等的论文中描述了为提高表面积采用相同的方法的器件,其可以作为折叠栅极LDMOS器件。
然而,尽管折叠栅极LDMOS结构在降低接通电阻而不消耗任何额外的芯片面积方面可以提供某些益处,但这种排列在提高器件的高频性能方面基本上没有提供任何益处。这主要由于器件的结电容Cj,它是器件的P-N结宽度的函数,随MOS器件的有效宽度成比例增加。MOS器件100的结电容的降低不依赖于沟槽宽度,这样如果沟道区基本上平坦的形成(如非沟槽),MOS器件100的结电容基本上保持不变。
P-N结的宽度可以被确定为N+漏极区106的周长之和,该漏极区106在遍及沟道区的宽度上沿沟槽110与P-型外延层104重叠。要注意的是,尽管图2中作为两维尺度的横截面示出,沟槽110基本上在器件的源极区102和漏极区106之间三维延伸。这样,给定沟槽的电容分布将是沟槽中P-N结的周长的函数,该周长是大约两倍的沟槽深度加上沟槽宽度(如2D+Wt)。同样,与两个相邻沟槽110之间的漏极区106的各部分有关的电容分布,即台地114(mesa)有关的电容分布,是台地114的P-N结的周长的函数,对于此实施例该周长是大约两部的沟槽深度加上台地的厚度T(如2D+T)。
图3是示例MOS器件的至少一部分的横截面图,其中本发明的技术被实施。构造MOS器件300以有利地提高器件的导电率,从而降低接通电阻而没有消耗额外的芯片面积和明显增加器件的结电容。这样,结电容Cj不与器件的有效沟道宽度Weff成比例增长。因此,与标准MOS器件比较,MOS器件300将提供增加的高频性能。为了实现此目的,形成示例的MOS器件300,这样出于用于确定器件的导电率的目的,有效宽度Weff较器件的P-N结的宽度大得多。
如图2显示的MOS器件100一样,示例的MOS器件300包括P+衬底302和形成在衬底上的P-型外延层304。多个沟槽310形成在外延层304中以提高器件的表面积,如前面的解释。N+漏极区306形成在外延层中,例如采用注入和/或扩散工艺。漏极区306靠近MOS器件300的外表面形成,从而会依照由沟槽310造成的器件的起伏的上表面轮廓。尽管图3示出的仅是MOS器件300的漏极区,可以理解,器件的源极区可以以同样的方式形成。对于LDMOS器件的例子,其中源极区通常与衬底电连接,源极区的电容分布通常可以忽略。
不象图2所示的MOS器件100的排列,在示例的MOS器件300中沟槽310的间距S被有利地设置,这样形成漏极区306后,在各对相邻沟槽之间的台地308基本上完全由具有N-型导电性的材料构成。MOS器件300的有效宽度Weff将是器件的沟槽310的深度和数目的函数。由于基本上没有形成在台地308中的P-N结,台地的结电容相对于器件的整个输出电容的分布基本上会为零。这样,至少出于确定结电容的目的,漏极区P-N结的宽度会,至少部分地,基于整个漏极区的P-N结的线性宽度WLIN加上两倍的沟槽深度(WLIN+2D)确定。
通常,P-N结的线性宽度会基本上大于沟槽深度,这样可归因于台地308的结电容会基本上不依赖于沟槽深度。在本发明的优选实施例中,可以采用大约1μm到大约50μm的沟槽深度,MOS器件300的导电率以沟槽深度函数的方式提高。对于图3所示的示例MOS器件300,P-N结电容Cj的降低与器件的有效宽度Weff成比例,其至少部分根据下面的表达式实现:
Cj∝Weff-2nD
其中n是所采用的沟槽数目,D是沟槽深度。从上述表达式可以看出,对于给定的有效宽度Weff,器件的结电容Cj随器件中所用的沟槽数目的增加而降低,同样随沟槽深度的增加而降低。
在一优选实施例中,MOS器件300中漏极区306的横截面厚度为大约0.3μm。由于用来形成漏极区306的N-型杂质会从两个相邻沟槽310的侧壁扩散进入各台地308,大约0.6μm或更小的沟槽间距会保证台地中几乎所有的P-型外延材料被N+漏极区所消耗。可以理解,MOS器件300不限于给定的沟槽310的间距。如,可以通过提高MOS器件300中漏极区306的横截面厚度,使用大于0.6μm的沟槽间距。
图4是根据本发明的又一个实施例形成的示例MOS器件400的至少部分的横截面图。图4主要显示了MOS器件400中漏极区。象图3中所示的MOS器件300一样,这样构造MOS器件400,使器件的有效宽度Weff基本上比器件的P-N结的宽度大,从而有利地降低器件中的接通电阻而没有消耗额外的芯片面积和没有提高器件的结电容。
示例MOS器件400包括形成在P+衬底402上的P-型外延层404。多个沟槽410形成在外延层404中靠近外延层的上表面。在两个相邻的沟槽410之间的外延区指台地412。台地412的中心部分优选地包括绝缘材料408,如氧化物(如二氧化硅)。优选形成的绝缘材料408的深度几乎等于沟槽410的深度(如大约1μm到大约50μm)。
N+漏极区406形成在外延层404中,如通过使用注入和/或扩散工艺。图示很明显,漏极区406优选地形成在靠近外延层404的上表面,这样基本上依照沟槽410造成的外延层上表面的起伏轮廓。然而,在MOS器件400中,漏极区406不是形成为连续的区域,替代地形成为分隔的区段,漏极区段通过台地412中形成的绝缘材料408彼此分开。漏极区段406主要被限制在沟槽410的侧壁和底壁,这样会具有相应的沟槽410的形状。尽管图4示出的仅为MOS器件400的漏极区406的部分横截面,可以理解,这里所描述的本发明的技术同样地被应用于形成器件的源极区。
MOS器件400的沟道区的有效宽度Weff可以被确定为器件中所有漏极区段406的周长之和,对于给定的沟槽,该有效宽度是沟槽深度D的两倍加上沟槽宽度W(即2D+W)的函数。确定MOS器件400的结电容时,器件中P-N结的宽度基本上仅是沟槽宽度的函数,这是因为由于绝缘材料408的存在没有P-N结形成在台地412中。这样,象图3所示的MOS器件300一样,这样构造MOS器件400,使沟道区的有效宽度基本上大于器件的漏极区的P-N结的宽度。
图5是根据本发明的第三实施例形成的示例MOS器件500的至少部分的横截面图。图5主要显示了MOS器件500中漏极区506的横截面图。MOS器件500优选地包括形成在P+衬底502上的P-型外延层504。象图3所示的MOS器件300一样,MOS器件500包括形成在外延层504中靠近其上表面的多个沟槽。与图3所示的MOS器件300的沟槽310比较,优选形成的MOS器件500的沟槽510具有底切(undercut)壁514,这样给定沟槽的底面较沟槽的上部开口宽得多。可以形成底切壁,如采用各向异性刻蚀工艺。这样,可以形成具有希望斜率的侧壁(如正和/或负斜率)的沟槽510。
优选地,这样构造两个相邻沟槽510之间的间距和N+漏极区506的厚度,这样在外延层504中形成漏极区后,靠近两个相邻沟槽底壁的漏极区部分基本上合并在一起,以贯穿沟槽的底壁形成几乎连续和水平的P-N结。于是形成在相邻沟槽之间的台地512将包括几乎被N+漏极区506包围的P-型外延材料508的芯部,以使P-型芯部材料508与外延层504电隔离。
MOS器件500中沟道区的有效宽度Weff可以被确定为与器件的漏极区506相关的所有区段周长之和,对于给定的沟槽,该有效宽度是大约稍多于两倍的沟槽宽度W(如基于倾斜侧壁514的倾斜角)加上沟槽宽度的函数。确定MOS器件500的结电容时,器件中P-N结的宽度基本上仅是P-N结的线性宽度WLIN的函数,这是因为,由于,至少部分由于漏极区506的存在基本上挤没了台地中的P-型材料,没有活性P-N结形成在台地512中。可归因于台地512的结电容基本上为零,尤其与器件的总结电容比较。这样,分别象图3和图4所示的MOS器件300和400一样,MOS器件500的沟道区的有效宽度基本上大于器件的P-N结的宽度。
图6是根据本发明的第四实施例形成的示例MOS器件600的至少部分的横截面图。图6主要显示了MOS器件600的漏极区606。象前面图3-5所描述的MOS器件的实施例一样,有利地构造示例MOS器件600,这样器件沟道区的有效宽度Weff基本上大于器件的P-N结的宽度。这使MOS器件600的导电率有利地提高,从而降低接通电阻而没有显著提高器件的结电容。
MOS器件600优选地包括形成在P+衬底602上的P-型外延层604。多个沟槽610形成在外延层604中靠近其上表面。形成在相邻沟槽610之间的台地612优选地基本上由已知浓度水平(如,大约1014到大约1015原子/cm3)的轻掺杂N-型材料608(如砷或磷)构成,例如通过采用注入和/或扩散工艺。然后较重掺杂的N+漏极区606(如,大约1015到大约1016原子/cm3)在靠近外延层604的上表面处形成,这样基本上依照沟槽610造成的外延层的起伏的上表面轮廓。起伏的漏极区606的排列提高了MOS器件600中沟道区的有效宽度,如前面的解释。
MOS器件600的有效宽度将基于器件中漏极区606的总周长之和确定,该有效宽度是沟槽610的深度D、沟槽的宽度W和台地的厚度T的函数。另一方面,器件中P-N结的宽度主要被确定为P-型外延层604和靠近各沟槽底壁的N+漏极区606之间的结的周长的函数,基本上不依赖于沟槽深度。P-N结也形成在外延层604和台地612中轻掺杂N-型材料608之间。然而,因为N-型材料608的掺杂浓度较N+漏极区606的掺杂浓度低的多,可归于与台地612相关的P-N结的结电容将小得多。象图3-5所示的示例MOS器件实施例一样,与形成漏极区606同样的方式,可以在MOS器件600中形成源极区(未示出)。
不损害一般性,这里描述和显示了用于形成MOS器件的各种示例的实施例,该MOS器件的有效宽度基本上大于器件中P-N结的宽度。本发明的技术和优点可以容易地扩展到形成替代器件,这一点对本领域的技术人员是明显的。
图7A-7D显示了根据本发明的一个实施例用于形成图4所示的示例MOS器件的示例方法的步骤。将参照传统的CMOS兼容半导体制造方法的技术进行描述。可以理解,本发明不限于制造该器件的此方法或其它方法。如前所述,图中所示的各种层和/或区没有按比例绘制,和为了便于说明某些半导体层已经被省略。
参照图7A,显示了至少部分示例半导体晶片700,其中本发明的技术被施行。晶片700优选地包括衬底702。衬底702优选地是具有高导电率的P+型衬底,尽管N+型衬底可以替代地采用。本领域的技术人员可以理解,可以通过扩散或注入步骤,向衬底材料中添加希望浓度(如大约5×1018到大约5×1019原子/cm3)的P-型杂质或掺杂剂(如硼),以将材料的导电率改变到预期值,来形成P+衬底。然后外延层704优选地在晶片700的整个表面生长。外延层704也可以通过添加P-型杂质改变。
第一部分的多个沟槽706形成在外延层704中,如通过在晶片700的上表面中开孔限定相应的沟槽。可以通过在晶片700的上表面上沉积一层光致抗蚀剂(未示出)和采用传统的平板印刷的步骤和随后的刻蚀步骤以除去不想要的晶片部分来形成开口。在外延层704中优选地形成(如采用活性离子刻蚀(RIE)、干刻蚀等)希望深度的沟槽706。如图7B所示,然后采用如传统的沟槽填充工艺,以绝缘材料,如氧化物(如二氧化硅),填充沟槽706,以形成填充的氧化物区708。填充的氧化物区708优选地形成为与外延层704的外表面基本平行。
参照图7C,然后在外延层704中靠近其上表面处形成第二部分的多个沟槽710。第二部分的多个沟槽710优选地借助于填充的氧化物区708彼此分开,各填充的氧化物区优选地置于两个相邻的沟槽710之间。如图7D所示,随后通过向外延层中添加预期浓度(如大约5×1018到大约5×1019原子/cm3)的N-型杂质或掺杂剂(如磷或砷)在外延层704靠近沟槽710的侧壁和底壁处形成漏极区714。如,可以采用注入或扩散工艺形成漏极区714以将材料的导电率改变到预期值。
图8A-8C显示了根据本发明的又一个实施例用于形成图6所示的示例MOS器件的示例方法的步骤。将参照传统的CMOS兼容的半导体制造方法的技术描述该示例方法。可以理解,本发明不限于制造该器件的此方法或任何其它给定的方法。
参照图8A,显示了示例半导体晶片800的至少一部分,其中本发明的技术可以被施行。晶片800优选地包括衬底802。衬底802优选地是具有高导电率的P+型衬底,尽管N+型衬底可以替代地被使用。本领域的技术人员可以理解,可以通过扩散或注入步骤,向衬底材料中添加预期浓度(如大约5×1018到大约5×1019原子/cm3)的P-型杂质或掺杂剂(如硼)形成P+衬底,以将材料的导电率改变到预期值。然后在晶片800的整个表面上优选地生长外延层804。外延层804也可以通过添加P-型杂质改变,尽管优选地是具有低于衬底802的掺杂浓度。轻掺杂的N-型层806优选地形成在至少部分外延层804上,例如通过采取注入或扩散工艺以将外延材料的导电率改变到预期值。
如图8B所示,多个沟槽808形成在轻掺杂的N-型层806中,如通过在晶片800的上表面开孔限定相应的沟槽。可以这样形成孔:在晶片800的上表面上沉积一层光致抗蚀剂(未示出),并采用传统的平板印刷工艺和随后的刻蚀工艺以除去不想要的晶片部分。在轻掺杂的N-型层806中优选地形成预期深度的沟槽808(如采用活性离子刻蚀(RIE),干刻蚀)。当形成沟槽808时,外延层804可以作为刻蚀阻挡层使用,从而通过沟槽的底壁裸露至少部分外延层,尽管不需要裸露外延层。
参照图8C,然后通过向N-型层中添加预期浓度(如大约5×1018到大约5×1019原子/cm3)的N-型杂质或掺杂剂812(如磷或砷)在轻掺杂的N-型层806中形成漏极区810。优选地在靠近晶片800的上表面处形成漏极区810,这样漏极区810将基本上具有由沟槽808造成的起伏轮廓。漏极区810可以被形成,如采取注入或扩散步骤以将材料的导电率改变到预期值。漏极区810的横截面厚度th优选地是约0.3μm,尽管漏极区不限于任何给定的尺寸和/或形状。
本发明的MOS器件至少部分可以应用于集成电路。形成集成电路时,通常在半导体晶片的表面上以重复的方式制造多个相同的裸片。各裸片包括这里所述的器件,可以包括其它的结构或电路。单个裸片被从晶片上划切,然后封装为集成电路。本领域的技术人员了解如何划切晶片和封装裸片以制造集成电路。如此制造的集成电路顾及了本发明的一部分。
尽管这里参照附图描述了本发明的示例性实施例,可以理解,本发明不限于那些具体的实施例,本领域技术人员可以进行各种其它的改变和修正而没有脱离附带的权利要求书的保护范围。
Claims (10)
1、一种金属-氧化物-半导体器件,包括:
具有第一导电类型的半导体层;
形成在所述半导体层中靠近其上表面的、具有第二导电类型的第一和第二源极/漏极区,该第一和第二源极/漏极区彼此分开;和
形成在半导体层上方并与半导体层电隔离的栅极,该栅极至少部分置于第一和第二源极/漏极区之间;
其中,所述第一和第二源极/漏极区中的至少给定一个被构造成具有基本上比在半导体层和所述给定的源极/漏极区之间的结的宽度大的有效宽度。
2、如权利要求1所述的器件,其特征在于,至少该给定的源极/漏极区包括形成在所述半导体层中靠近其上表面的多个沟槽,这些沟槽的间距这样安排以致于分隔两个相邻沟槽的至少部分半导体层基本上完全由第二导电类型的材料构成。
3、如权利要求2所述的器件,其特征在于,该器件的有效宽度与位于半导体层和给定的源极/漏极区之间的结宽度的比率是半导体层中各沟槽的深度的函数。
4、如权利要求1所述的器件,其特征在于,至少该给定的源极/漏极区包括形成在所述半导体层中靠近其上表面的多个沟槽,所述沟槽中的至少一个子组被构造成使得分隔两个相邻沟槽的部分半导体层的宽度小于所述给定的源极/漏极区的横截面厚度的两倍,以致于分隔两个相邻沟槽的部分半导体层基本上完全由第二导电类型的材料构成。
5、如权利要求1所述的器件,其特征在于,至少该给定的源极/漏极区这样形成:在所述半导体层中形成靠近其上表面的多个沟槽,向所述半导体层中靠近其上表面处注入第二导电类型的杂质,这样构造沟槽的间距,以致于分隔两个相邻沟槽的至少部分半导体层基本上由第二导电类型的材料取代。
6、如权利要求1所述的器件,其特征在于,至少该给定的源极/漏极区包括形成在所述半导体层中靠近其上表面的多个沟槽,所述沟槽中至少一个子组中的每个沟槽被构造成具有包括第二导电类型的材料的底壁和侧壁,这样构造这些沟槽,以致于各个沟槽的底壁在半导体层中形成基本连续的第二导电类型的区域。
7、如权利要求1所述的器件,其特征在于,至少该给定的源极/漏极区包括形成在所述半导体层中靠近其上表面的多个沟槽,所述沟槽中至少一个子组中的每个沟槽被构造成具有包括第二导电类型材料的底壁和倾斜的侧壁,这样构造两个相邻沟槽的侧壁,以致于靠近相邻沟槽底壁的第二导电类型的材料合并而在半导体层中形成基本上连续的第二导电类型的区域。
8、一种金属-氧化物-半导体器件,包括:
具有第一导电类型的第一半导体层;
形成在第一半导体层上的具有第二导电类型的第二半导体层;
形成在第二半导体层中的具有第二导电类型的第一和第二源极/漏极区,第一和第二源极/漏极区彼此分开,所述第一和第二源极/漏极区中的至少给定一个在第一半导体层和该给定的源极/漏极区之间形成至少一个结;和
形成在第二半导体层上方并与第二半导体层电隔离的栅极,该栅极至少部分置于第一和第二源极/漏极区之间;
其中,所述源极/漏极区中的至少该给定一个被构造成其有效宽度基本上大于在第一半导体层和该给定的源极/漏极区之间的至少一个结的宽度。
9、一种形成金属-氧化物-半导体器件的方法,该方法包括下面的步骤:
在第二导电类型的半导体层中形成具有第一导电类型的第一和第二源极/漏极区,该第一和第二源极/漏极区在靠近半导体层的上表面处形成并彼此分开;和
在半导体层上方形成与半导体层电隔离的栅极,该栅极至少部分形成在第一和第二源极/漏极区之间;
其中,所述第一和第二源极/漏极区中的至少给定一个被形成为其有效宽度基本上大于在半导体层和该给定的源极/漏极区之间的结的宽度。
10、一种包括至少一个金属-氧化物-半导体器件的集成电路,该至少一个金属-氧化物-半导体器件包括:
一具有第一导电类型的半导体层;
形成在所述半导体层中靠近其上表面的、具有第二导电类型的第一和第二源极/漏极区,该第一和第二源极/漏极区彼此分开;和
形成在半导体层上方并与半导体层电隔离的栅极,该栅极至少部分置于第一和第二源极/漏极区之间;
其中,所述第一和第二源极/漏极区中的至少给定一个被构造成其有效宽度基本上大于在半导体层和该给定的源极/漏极区之间的结的宽度。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/953,018 US20060071270A1 (en) | 2004-09-29 | 2004-09-29 | Metal-oxide-semiconductor device having trenched diffusion region and method of forming same |
US10/953,018 | 2004-09-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1755941A true CN1755941A (zh) | 2006-04-05 |
CN100461452C CN100461452C (zh) | 2009-02-11 |
Family
ID=36124684
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100781685A Expired - Fee Related CN100461452C (zh) | 2004-09-29 | 2005-06-17 | 具有沟槽扩散区的mos器件及其形成方法 |
Country Status (4)
Country | Link |
---|---|
US (3) | US20060071270A1 (zh) |
JP (2) | JP2006100824A (zh) |
KR (1) | KR101210014B1 (zh) |
CN (1) | CN100461452C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102315251A (zh) * | 2010-07-06 | 2012-01-11 | 瑞萨电子株式会社 | 半导体集成电路器件以及半导体集成电路器件的制造方法 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060071270A1 (en) * | 2004-09-29 | 2006-04-06 | Shibib Muhammed A | Metal-oxide-semiconductor device having trenched diffusion region and method of forming same |
US7348642B2 (en) | 2005-08-03 | 2008-03-25 | International Business Machines Corporation | Fin-type field effect transistor |
US7781832B2 (en) * | 2008-05-28 | 2010-08-24 | Ptek Technology Co., Ltd. | Trench-type power MOS transistor and integrated circuit utilizing the same |
EP2338177B1 (en) * | 2008-10-20 | 2014-06-04 | Nxp B.V. | Insulated gate semiconductor device and method of manufacturing the same |
US7951680B2 (en) * | 2008-10-30 | 2011-05-31 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit system employing an elevated drain |
JP5372578B2 (ja) | 2009-04-09 | 2013-12-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
WO2010133923A1 (en) * | 2009-05-22 | 2010-11-25 | X-Fab Semiconductor Foundries Ag | Semiconductor device comprising an isolation trench including semiconductor islands |
US9543383B2 (en) * | 2011-02-17 | 2017-01-10 | Qualcomm Incorporated | High-speed high-power semiconductor devices |
KR101896665B1 (ko) * | 2012-01-11 | 2018-09-07 | 삼성전자주식회사 | 반도체 패키지 |
US9748341B2 (en) | 2013-07-02 | 2017-08-29 | General Electric Company | Metal-oxide-semiconductor (MOS) devices with increased channel periphery |
US9024328B2 (en) | 2013-07-02 | 2015-05-05 | General Electric Company | Metal-oxide-semiconductor (MOS) devices with increased channel periphery and methods of manufacture |
US9443958B2 (en) * | 2014-10-06 | 2016-09-13 | United Microelectronics Corp. | High voltage metal-oxide-semiconductor transistor device and method of forming the same |
WO2021065740A1 (ja) * | 2019-09-30 | 2021-04-08 | ローム株式会社 | 半導体装置 |
US11569345B2 (en) * | 2020-11-23 | 2023-01-31 | Alpha And Omega Semiconductor (Cayman) Ltd. | Gas dopant doped deep trench super junction high voltage MOSFET |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5671974A (en) * | 1979-11-16 | 1981-06-15 | Fujitsu Ltd | Insulating gate type electric field effect transistor |
JP2522041B2 (ja) * | 1989-04-21 | 1996-08-07 | 富士電機株式会社 | プラズマエッチング方法 |
JPH04212466A (ja) * | 1990-07-09 | 1992-08-04 | Toshiba Corp | 半導体装置およびその製造方法 |
JPH04324955A (ja) * | 1991-04-25 | 1992-11-13 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
KR920022546A (ko) * | 1991-05-31 | 1992-12-19 | 김광호 | 모오스 트랜지스터의 구조 및 그 제조방법 |
JPH05110083A (ja) * | 1991-10-15 | 1993-04-30 | Oki Electric Ind Co Ltd | 電界効果トランジスタ |
JPH05110078A (ja) * | 1991-10-16 | 1993-04-30 | Oki Electric Ind Co Ltd | 電界効果トランジスタ及びその製造方法 |
JPH05218415A (ja) * | 1992-01-31 | 1993-08-27 | Kawasaki Steel Corp | 半導体装置 |
JPH05315613A (ja) * | 1992-05-13 | 1993-11-26 | Oki Electric Ind Co Ltd | 半導体装置およびシリサイド層の形成方法 |
US5675164A (en) * | 1995-06-07 | 1997-10-07 | International Business Machines Corporation | High performance multi-mesa field effect transistor |
US5831312A (en) * | 1996-04-09 | 1998-11-03 | United Microelectronics Corporation | Electrostic discharge protection device comprising a plurality of trenches |
KR19980048864A (ko) | 1996-12-18 | 1998-09-15 | 김광호 | 반도체 장치의 소자분리방법 |
TW360954B (en) * | 1997-01-16 | 1999-06-11 | United Microelectronics Corp | Read-only memory structure and method of fabricating the same |
US6013551A (en) * | 1997-09-26 | 2000-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby |
US6518621B1 (en) * | 1999-09-14 | 2003-02-11 | General Semiconductor, Inc. | Trench DMOS transistor having reduced punch-through |
JP2001185721A (ja) * | 1999-12-22 | 2001-07-06 | Nec Corp | 半導体装置 |
WO2001086726A1 (en) * | 2000-05-10 | 2001-11-15 | Koninklijke Philips Electronics N.V. | A semiconductor device |
JP2002118255A (ja) * | 2000-07-31 | 2002-04-19 | Toshiba Corp | 半導体装置およびその製造方法 |
JP4042530B2 (ja) * | 2002-10-30 | 2008-02-06 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
JP5110776B2 (ja) * | 2004-07-01 | 2012-12-26 | セイコーインスツル株式会社 | 半導体装置の製造方法 |
US20060071270A1 (en) * | 2004-09-29 | 2006-04-06 | Shibib Muhammed A | Metal-oxide-semiconductor device having trenched diffusion region and method of forming same |
-
2004
- 2004-09-29 US US10/953,018 patent/US20060071270A1/en not_active Abandoned
-
2005
- 2005-06-17 CN CNB2005100781685A patent/CN100461452C/zh not_active Expired - Fee Related
- 2005-09-26 JP JP2005277004A patent/JP2006100824A/ja active Pending
- 2005-09-28 KR KR1020050090479A patent/KR101210014B1/ko not_active IP Right Cessation
-
2007
- 2007-12-04 US US11/999,168 patent/US8153484B2/en active Active
-
2012
- 2012-03-23 US US13/428,540 patent/US8648445B2/en active Active
- 2012-10-25 JP JP2012235816A patent/JP2013042169A/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102315251A (zh) * | 2010-07-06 | 2012-01-11 | 瑞萨电子株式会社 | 半导体集成电路器件以及半导体集成电路器件的制造方法 |
CN102315251B (zh) * | 2010-07-06 | 2017-10-20 | 瑞萨电子株式会社 | 半导体集成电路器件以及半导体集成电路器件的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2013042169A (ja) | 2013-02-28 |
US20120175702A1 (en) | 2012-07-12 |
KR20060051752A (ko) | 2006-05-19 |
US8648445B2 (en) | 2014-02-11 |
US8153484B2 (en) | 2012-04-10 |
US20080093667A1 (en) | 2008-04-24 |
KR101210014B1 (ko) | 2012-12-07 |
US20060071270A1 (en) | 2006-04-06 |
CN100461452C (zh) | 2009-02-11 |
JP2006100824A (ja) | 2006-04-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100461452C (zh) | 具有沟槽扩散区的mos器件及其形成方法 | |
US6501129B2 (en) | Semiconductor device | |
US10446678B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
CN1738057A (zh) | 具有增强的屏蔽结构的金属氧化物半导体器件 | |
CN1040814C (zh) | 一种用于半导体器件的表面耐压区 | |
US7928505B2 (en) | Semiconductor device with vertical trench and lightly doped region | |
US5385852A (en) | Method for manufacturing vertical MOS transistors | |
CN1240136C (zh) | 横向半导体器件 | |
CN1211844C (zh) | 功率mosfet及利用自对准体注入制作其的方法 | |
JP3721172B2 (ja) | 半導体装置 | |
US8174066B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
US6822288B2 (en) | Trench MOSFET device with polycrystalline silicon source contact structure | |
CN1547765A (zh) | 具有内嵌的沟槽肖特基整流器的沟槽dmos晶体管 | |
CN107068759B (zh) | 半导体器件及其制造方法 | |
CN1468449A (zh) | 内含沟道型肖特基整流器的沟道型dmos晶体管 | |
US7893490B2 (en) | HVNMOS structure for reducing on-resistance and preventing BJT triggering | |
US20080157193A1 (en) | Semiconductor device and method for fabricating the same | |
CN1663049A (zh) | 横向半导体器件 | |
JP2007005723A (ja) | 半導体装置 | |
CN1886835A (zh) | 沟槽绝缘栅场效应晶体管 | |
CN1274025C (zh) | 半导体器件及其制造方法 | |
JP2018156996A (ja) | 半導体装置 | |
JP2012204636A (ja) | 半導体装置およびその製造方法 | |
CN101060122A (zh) | 半导体装置 | |
US7566933B2 (en) | Trench-gate semiconductor device and manufacturing method of trench-gate semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090211 Termination date: 20150617 |
|
EXPY | Termination of patent right or utility model |