CN1744303A - 用于半导体器件的封装基底、其制造方法以及半导体器件 - Google Patents
用于半导体器件的封装基底、其制造方法以及半导体器件 Download PDFInfo
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- CN1744303A CN1744303A CNA2005100966709A CN200510096670A CN1744303A CN 1744303 A CN1744303 A CN 1744303A CN A2005100966709 A CNA2005100966709 A CN A2005100966709A CN 200510096670 A CN200510096670 A CN 200510096670A CN 1744303 A CN1744303 A CN 1744303A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2009—Reinforced areas, e.g. for a specific part of a flexible printed circuit
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1178—Means for venting or for letting gases escape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
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Abstract
Description
Claims (23)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004252568A JP4559163B2 (ja) | 2004-08-31 | 2004-08-31 | 半導体装置用パッケージ基板およびその製造方法と半導体装置 |
JP2004-252568 | 2004-08-31 | ||
JP2004252568 | 2004-08-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1744303A true CN1744303A (zh) | 2006-03-08 |
CN1744303B CN1744303B (zh) | 2010-05-05 |
Family
ID=35942718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2005100966709A Active CN1744303B (zh) | 2004-08-31 | 2005-08-31 | 用于半导体器件的封装基底、其制造方法以及半导体器件 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7378745B2 (zh) |
JP (1) | JP4559163B2 (zh) |
KR (1) | KR100773461B1 (zh) |
CN (1) | CN1744303B (zh) |
TW (1) | TWI278972B (zh) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102254897A (zh) * | 2010-05-18 | 2011-11-23 | 台湾积体电路制造股份有限公司 | 具有中介层的封装*** |
CN102469691A (zh) * | 2010-11-10 | 2012-05-23 | 三星电机株式会社 | 印刷电路板及其制造方法 |
CN102804940A (zh) * | 2009-09-24 | 2012-11-28 | 奥普蒂恩公司 | 包括电路板和电子集成元件的封装型***的接触垫的布置 |
CN102820270A (zh) * | 2011-06-09 | 2012-12-12 | 欣兴电子股份有限公司 | 封装基板及其制法 |
CN103378040A (zh) * | 2012-04-11 | 2013-10-30 | 台湾积体电路制造股份有限公司 | 半导体器件封装件及半导体器件封装方法 |
CN104701217A (zh) * | 2013-12-06 | 2015-06-10 | 日本麦可罗尼克斯股份有限公司 | 布线基板导通孔配置确定装置及方法 |
CN108476585A (zh) * | 2015-12-02 | 2018-08-31 | 马尔泰克技术有限公司 | Pcb混合重分布层 |
CN111029326A (zh) * | 2018-10-09 | 2020-04-17 | 西安邮电大学 | 基于lcp工艺的凸点互连结构 |
CN111052885A (zh) * | 2017-08-25 | 2020-04-21 | 塔克托科技有限公司 | 用于承载电子器件的多层结构及其相关制造方法 |
CN113068322A (zh) * | 2021-02-11 | 2021-07-02 | 赵行 | 一种柔性电路板新型接线方法 |
WO2022160800A1 (zh) * | 2021-01-28 | 2022-08-04 | 华为技术有限公司 | 连接组件、板级架构,以及一种计算设备 |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI388042B (zh) * | 2004-11-04 | 2013-03-01 | Taiwan Semiconductor Mfg | 基於奈米管基板之積體電路 |
JP4533248B2 (ja) * | 2005-06-03 | 2010-09-01 | 新光電気工業株式会社 | 電子装置 |
DE102005039365B4 (de) * | 2005-08-19 | 2022-02-10 | Infineon Technologies Ag | Gate-gesteuertes Fin-Widerstandselement, welches als pinch - resistor arbeitet, zur Verwendung als ESD-Schutzelement in einem elektrischen Schaltkreis und Einrichtung zum Schutz vor elektrostatischen Entladungen in einem elektrischen Schaltkreis |
KR100719376B1 (ko) * | 2006-01-05 | 2007-05-17 | 삼성전자주식회사 | 실장 불량을 줄일 수 있는 패드 구조체를 구비하는 반도체장치 |
JP2007201254A (ja) * | 2006-01-27 | 2007-08-09 | Ibiden Co Ltd | 半導体素子内蔵基板、半導体素子内蔵型多層回路基板 |
JP4881044B2 (ja) * | 2006-03-16 | 2012-02-22 | 株式会社東芝 | 積層型半導体装置の製造方法 |
JP4870584B2 (ja) * | 2007-01-19 | 2012-02-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4800253B2 (ja) * | 2007-04-04 | 2011-10-26 | 新光電気工業株式会社 | 配線基板の製造方法 |
TWI334643B (en) * | 2007-04-11 | 2010-12-11 | Nan Ya Printed Circuit Board Corp | Solder pad and method of making the same |
JP5125389B2 (ja) * | 2007-10-12 | 2013-01-23 | 富士通株式会社 | 基板の製造方法 |
JP2009099620A (ja) * | 2007-10-12 | 2009-05-07 | Fujitsu Ltd | コア基板およびその製造方法 |
US20090294961A1 (en) * | 2008-06-02 | 2009-12-03 | Infineon Technologies Ag | Semiconductor device |
WO2010099158A1 (en) * | 2009-02-26 | 2010-09-02 | Arkema Inc. | Electrode arrays based on polyetherketoneketone |
JP5445001B2 (ja) * | 2009-09-29 | 2014-03-19 | 沖電気工業株式会社 | 半導体素子内蔵基板及び半導体素子内蔵基板の製造方法 |
US8278214B2 (en) * | 2009-12-23 | 2012-10-02 | Intel Corporation | Through mold via polymer block package |
JP5514560B2 (ja) | 2010-01-14 | 2014-06-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN102163558B (zh) * | 2010-02-23 | 2012-12-19 | 日月光半导体制造股份有限公司 | 芯片封装结构的制造方法 |
JP2011222946A (ja) * | 2010-03-26 | 2011-11-04 | Sumitomo Bakelite Co Ltd | 回路基板、半導体装置、回路基板の製造方法および半導体装置の製造方法 |
US8174826B2 (en) | 2010-05-27 | 2012-05-08 | International Business Machines Corporation | Liquid cooling system for stackable modules in energy-efficient computing systems |
US8279597B2 (en) | 2010-05-27 | 2012-10-02 | International Business Machines Corporation | Heatsink allowing in-situ maintenance in a stackable module |
US8179674B2 (en) | 2010-05-28 | 2012-05-15 | International Business Machines Corporation | Scalable space-optimized and energy-efficient computing system |
US8358503B2 (en) | 2010-05-28 | 2013-01-22 | International Business Machines Corporation | Stackable module for energy-efficient computing systems |
US8426961B2 (en) * | 2010-06-25 | 2013-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded 3D interposer structure |
TWI420983B (zh) * | 2010-12-17 | 2013-12-21 | Darfon Electronics Corp | 陶瓷電路基板與製造方法 |
US9721872B1 (en) | 2011-02-18 | 2017-08-01 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US8810025B2 (en) * | 2011-03-17 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reinforcement structure for flip-chip packaging |
WO2012176402A1 (ja) * | 2011-06-21 | 2012-12-27 | 株式会社村田製作所 | 回路モジュール |
JP5468572B2 (ja) * | 2011-06-22 | 2014-04-09 | 新光電気工業株式会社 | 配線基板 |
US9888568B2 (en) | 2012-02-08 | 2018-02-06 | Crane Electronics, Inc. | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module |
CN104145538B (zh) * | 2012-02-08 | 2018-12-14 | 克兰电子公司 | 多层式电子组件和用于将电路部件嵌入三维模块的方法 |
US8890302B2 (en) * | 2012-06-29 | 2014-11-18 | Intel Corporation | Hybrid package transmission line circuits |
JP6122606B2 (ja) * | 2012-10-16 | 2017-04-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2014086651A (ja) * | 2012-10-26 | 2014-05-12 | Ibiden Co Ltd | プリント配線板及びプリント配線板の製造方法 |
US9799592B2 (en) | 2013-11-19 | 2017-10-24 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
KR101366461B1 (ko) | 2012-11-20 | 2014-02-26 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
JP6291738B2 (ja) | 2013-07-25 | 2018-03-14 | 富士通株式会社 | 回路基板、回路基板の製造方法及び電子機器 |
KR101607981B1 (ko) | 2013-11-04 | 2016-03-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지 |
CN205726710U (zh) * | 2014-02-07 | 2016-11-23 | 株式会社村田制作所 | 树脂多层基板及元器件模块 |
CN105140198B (zh) * | 2014-05-29 | 2017-11-28 | 日月光半导体制造股份有限公司 | 半导体衬底、半导体封装结构及其制造方法 |
JP6374338B2 (ja) * | 2015-03-24 | 2018-08-15 | 京セラ株式会社 | 配線基板 |
US20180047692A1 (en) * | 2016-08-10 | 2018-02-15 | Amkor Technology, Inc. | Method and System for Packing Optimization of Semiconductor Devices |
US9960328B2 (en) | 2016-09-06 | 2018-05-01 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
KR102639101B1 (ko) * | 2017-02-24 | 2024-02-22 | 에스케이하이닉스 주식회사 | 전자기간섭 차폐 구조를 갖는 반도체 패키지 |
US10074919B1 (en) * | 2017-06-16 | 2018-09-11 | Intel Corporation | Board integrated interconnect |
US10973128B2 (en) * | 2017-08-30 | 2021-04-06 | Panasonic Intellectual Property Management Co., Ltd. | Flexible printed circuit and imaging apparatus including same |
KR102028715B1 (ko) | 2017-12-19 | 2019-10-07 | 삼성전자주식회사 | 반도체 패키지 |
KR102029099B1 (ko) | 2018-02-05 | 2019-10-07 | 삼성전자주식회사 | 반도체 패키지 |
US10645808B2 (en) * | 2018-02-22 | 2020-05-05 | Apple Inc. | Devices with radio-frequency printed circuits |
JP7214966B2 (ja) * | 2018-03-16 | 2023-01-31 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
TWI681527B (zh) * | 2019-03-21 | 2020-01-01 | 創意電子股份有限公司 | 線路結構及晶片封裝件 |
US11519957B2 (en) * | 2019-09-26 | 2022-12-06 | International Business Machines Corporation | Ball grid array current meter with a current sense wire |
US11226369B2 (en) * | 2019-09-26 | 2022-01-18 | International Business Machines Corporation | Ball grid array current meter with a current sense loop |
US11054442B2 (en) | 2019-09-26 | 2021-07-06 | International Business Machines Corporation | Ball grid array current meter with a current sense mesh |
Family Cites Families (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1992011654A1 (en) | 1990-12-21 | 1992-07-09 | Motorola, Inc. | Leadless pad array chip carrier |
US5672911A (en) * | 1996-05-30 | 1997-09-30 | Lsi Logic Corporation | Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package |
KR100234719B1 (ko) * | 1997-03-14 | 1999-12-15 | 김영환 | 에리어 어레이 패키지 및 그 제조방법 |
US6639155B1 (en) * | 1997-06-11 | 2003-10-28 | International Business Machines Corporation | High performance packaging platform and method of making same |
US5847936A (en) * | 1997-06-20 | 1998-12-08 | Sun Microsystems, Inc. | Optimized routing scheme for an integrated circuit/printed circuit board |
KR19990011236A (ko) * | 1997-07-22 | 1999-02-18 | 문정환 | 반도체장치의 다층배선 형성방법 |
US6525414B2 (en) * | 1997-09-16 | 2003-02-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device including a wiring board and semiconductor elements mounted thereon |
JP3466443B2 (ja) * | 1997-11-19 | 2003-11-10 | 新光電気工業株式会社 | 多層回路基板 |
JP3355142B2 (ja) | 1998-01-21 | 2002-12-09 | 三菱樹脂株式会社 | 耐熱性積層体用フィルムとこれを用いたプリント配線基板用素板および基板の製造方法 |
US5939782A (en) * | 1998-03-03 | 1999-08-17 | Sun Microsystems, Inc. | Package construction for integrated circuit chip with bypass capacitor |
KR20000059562A (ko) * | 1999-03-05 | 2000-10-05 | 이형도 | 다층 플렉시블 기판 |
US6613413B1 (en) * | 1999-04-26 | 2003-09-02 | International Business Machines Corporation | Porous power and ground planes for reduced PCB delamination and better reliability |
JP2001035960A (ja) * | 1999-07-21 | 2001-02-09 | Mitsubishi Electric Corp | 半導体装置および製造方法 |
JP3865989B2 (ja) * | 2000-01-13 | 2007-01-10 | 新光電気工業株式会社 | 多層配線基板、配線基板、多層配線基板の製造方法、配線基板の製造方法、及び半導体装置 |
EP1990832A3 (en) * | 2000-02-25 | 2010-09-29 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
JP2001244609A (ja) * | 2000-02-25 | 2001-09-07 | Sony Corp | 配線基板の製造方法及びそれにより得られた配線基板 |
US6535398B1 (en) * | 2000-03-07 | 2003-03-18 | Fujitsu Limited | Multichip module substrates with buried discrete capacitors and components and methods for making |
JP2002057467A (ja) * | 2000-08-11 | 2002-02-22 | Kenwood Corp | 多層配線基板 |
JP4329253B2 (ja) | 2000-10-10 | 2009-09-09 | 株式会社村田製作所 | フリップチップ用セラミック多層基板の製造方法 |
JP3819701B2 (ja) * | 2000-11-10 | 2006-09-13 | 三菱樹脂株式会社 | ビルドアップ多層プリント配線基板用コア基板 |
JP2002222895A (ja) * | 2001-01-25 | 2002-08-09 | Sumitomo Bakelite Co Ltd | 半導体装置およびその製造方法 |
US6486534B1 (en) * | 2001-02-16 | 2002-11-26 | Ashvattha Semiconductor, Inc. | Integrated circuit die having an interference shield |
US6512182B2 (en) * | 2001-03-12 | 2003-01-28 | Ngk Spark Plug Co., Ltd. | Wiring circuit board and method for producing same |
JP2003060348A (ja) * | 2001-06-07 | 2003-02-28 | Denso Corp | プリント基板 |
JP3885638B2 (ja) | 2001-07-04 | 2007-02-21 | 株式会社デンソー | プレス工法およびプレス用部材の作製方法 |
JP3861669B2 (ja) * | 2001-11-22 | 2006-12-20 | ソニー株式会社 | マルチチップ回路モジュールの製造方法 |
US6975025B2 (en) * | 2001-12-03 | 2005-12-13 | Intel Corporation | Semiconductor chip package and method of manufacturing same |
JP2003188338A (ja) * | 2001-12-13 | 2003-07-04 | Sony Corp | 回路基板装置及びその製造方法 |
KR20030060268A (ko) * | 2002-01-08 | 2003-07-16 | 주식회사 심텍 | 본딩패드 접속용 비아홀을 이용한 비지에이 반도체패키지의 제조방법 및 그 구조 |
JP2003201364A (ja) * | 2002-01-10 | 2003-07-18 | Nitto Denko Corp | 配線基板用多孔質フィルム、及び配線基板プリプレグ |
JP3855774B2 (ja) | 2002-01-15 | 2006-12-13 | 株式会社デンソー | 多層基板の製造方法 |
JP4181778B2 (ja) * | 2002-02-05 | 2008-11-19 | ソニー株式会社 | 配線基板の製造方法 |
US6941537B2 (en) * | 2002-02-07 | 2005-09-06 | Intel Corporation | Standoff devices and methods of using same |
JP3773896B2 (ja) * | 2002-02-15 | 2006-05-10 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20030170450A1 (en) | 2002-03-05 | 2003-09-11 | Stewart Steven L. | Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive |
JP2003264256A (ja) * | 2002-03-08 | 2003-09-19 | Hitachi Ltd | 半導体装置 |
JP4051989B2 (ja) * | 2002-04-12 | 2008-02-27 | 株式会社デンソー | 多層配線基板の製造方法 |
US6750403B2 (en) * | 2002-04-18 | 2004-06-15 | Hewlett-Packard Development Company, L.P. | Reconfigurable multilayer printed circuit board |
JP3855832B2 (ja) | 2002-04-23 | 2006-12-13 | 株式会社デンソー | プリント基板の製造方法 |
JP2003324280A (ja) | 2002-05-07 | 2003-11-14 | Denso Corp | プリント基板の製造方法 |
JP3945316B2 (ja) * | 2002-05-30 | 2007-07-18 | 株式会社デンソー | 多層配線基板及びその製造方法 |
JP2004031828A (ja) * | 2002-06-27 | 2004-01-29 | Ibiden Co Ltd | 多層プリント配線板 |
JP3918674B2 (ja) | 2002-07-31 | 2007-05-23 | 株式会社デンソー | プリント基板の製造方法 |
JP4121339B2 (ja) | 2002-09-02 | 2008-07-23 | 株式会社フジクラ | 多層配線板の製造方法 |
JP2004158671A (ja) | 2002-11-07 | 2004-06-03 | Eito Kogyo:Kk | 多層基板およびその製造方法 |
TW573332B (en) | 2002-11-29 | 2004-01-21 | Via Tech Inc | Lamination process and structure |
CA2455024A1 (en) * | 2003-01-30 | 2004-07-30 | Endicott Interconnect Technologies, Inc. | Stacked chip electronic package having laminate carrier and method of making same |
JP2004241496A (ja) * | 2003-02-04 | 2004-08-26 | Kyocera Corp | 配線基板およびこれを用いた電子装置 |
JP2004253738A (ja) * | 2003-02-21 | 2004-09-09 | Toshiba Corp | パッケージ基板及びフリップチップ型半導体装置 |
US6781218B1 (en) * | 2003-03-04 | 2004-08-24 | Nptest, Inc. | Method and apparatus for accessing internal nodes of an integrated circuit using IC package substrate |
US7579251B2 (en) * | 2003-05-15 | 2009-08-25 | Fujitsu Limited | Aerosol deposition process |
TW586676U (en) * | 2003-06-16 | 2004-05-01 | Via Tech Inc | Hybrid IC package substrate |
JP4387403B2 (ja) * | 2004-03-19 | 2009-12-16 | 株式会社ルネサステクノロジ | 電子回路 |
-
2004
- 2004-08-31 JP JP2004252568A patent/JP4559163B2/ja not_active Expired - Fee Related
-
2005
- 2005-08-23 TW TW094128798A patent/TWI278972B/zh not_active IP Right Cessation
- 2005-08-30 US US11/213,867 patent/US7378745B2/en active Active
- 2005-08-30 KR KR1020050080072A patent/KR100773461B1/ko active IP Right Grant
- 2005-08-31 CN CN2005100966709A patent/CN1744303B/zh active Active
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Also Published As
Publication number | Publication date |
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KR20060050826A (ko) | 2006-05-19 |
JP4559163B2 (ja) | 2010-10-06 |
TW200620577A (en) | 2006-06-16 |
KR100773461B1 (ko) | 2007-11-05 |
US7378745B2 (en) | 2008-05-27 |
CN1744303B (zh) | 2010-05-05 |
US20060044735A1 (en) | 2006-03-02 |
TWI278972B (en) | 2007-04-11 |
JP2006073622A (ja) | 2006-03-16 |
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