CN1519908A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1519908A CN1519908A CNA200310120446XA CN200310120446A CN1519908A CN 1519908 A CN1519908 A CN 1519908A CN A200310120446X A CNA200310120446X A CN A200310120446XA CN 200310120446 A CN200310120446 A CN 200310120446A CN 1519908 A CN1519908 A CN 1519908A
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Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims description 28
- 238000005520 cutting process Methods 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000012217 deletion Methods 0.000 description 2
- 230000037430 deletion Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000000205 computational method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 229910001751 gemstone Inorganic materials 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Dicing (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP021084/2003 | 2003-01-29 | ||
JP2003021084A JP4136684B2 (ja) | 2003-01-29 | 2003-01-29 | 半導体装置及びそのダミーパターンの配置方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1519908A true CN1519908A (zh) | 2004-08-11 |
CN1316584C CN1316584C (zh) | 2007-05-16 |
Family
ID=32652878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB200310120446XA Expired - Lifetime CN1316584C (zh) | 2003-01-29 | 2003-12-11 | 半导体器件及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6841880B2 (zh) |
EP (1) | EP1443552B1 (zh) |
JP (1) | JP4136684B2 (zh) |
CN (1) | CN1316584C (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100454522C (zh) * | 2005-01-28 | 2009-01-21 | 恩益禧电子股份有限公司 | 半导体器件 |
CN102445864A (zh) * | 2011-10-21 | 2012-05-09 | 上海华力微电子有限公司 | 一种降低光刻对准失效率的方法 |
CN103346129A (zh) * | 2013-05-21 | 2013-10-09 | 北京新雷能科技股份有限公司 | 一种陶瓷封装外壳及其制作方法、芯片封装方法 |
TWI466257B (zh) * | 2010-03-31 | 2014-12-21 | Toshiba Kk | 半導體裝置及其製造方法 |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI222680B (en) * | 2003-11-20 | 2004-10-21 | United Microelectronics Corp | Scribe line structure of wafer |
JP2005252099A (ja) * | 2004-03-05 | 2005-09-15 | Sharp Corp | 高周波用半導体装置 |
JP4471852B2 (ja) * | 2005-01-21 | 2010-06-02 | パナソニック株式会社 | 半導体ウェハ及びそれを用いた製造方法ならびに半導体装置 |
JP4809632B2 (ja) * | 2005-06-01 | 2011-11-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7343581B2 (en) * | 2005-06-27 | 2008-03-11 | Tela Innovations, Inc. | Methods for creating primitive constructed standard cells |
KR100794796B1 (ko) * | 2005-09-08 | 2008-01-15 | 삼성전자주식회사 | 가변 인덕터 |
US7590968B1 (en) | 2006-03-01 | 2009-09-15 | Tela Innovations, Inc. | Methods for risk-informed chip layout generation |
US7908578B2 (en) * | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US8225239B2 (en) * | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
US7446352B2 (en) * | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US7932545B2 (en) | 2006-03-09 | 2011-04-26 | Tela Innovations, Inc. | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US9230910B2 (en) * | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8247846B2 (en) * | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
US7956421B2 (en) * | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US7943967B2 (en) * | 2006-03-09 | 2011-05-17 | Tela Innovations, Inc. | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments |
US8225261B2 (en) * | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
US9563733B2 (en) * | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8245180B2 (en) * | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
JP4302720B2 (ja) * | 2006-06-28 | 2009-07-29 | 株式会社沖データ | 半導体装置、ledヘッド及び画像形成装置 |
US7577049B1 (en) | 2006-08-08 | 2009-08-18 | Tela Innovations, Inc. | Speculative sense enable tuning apparatus and associated methods |
US7696607B2 (en) | 2006-08-10 | 2010-04-13 | Panasonic Corporation | Semiconductor device |
DE102007004953A1 (de) * | 2007-01-26 | 2008-07-31 | Tesa Ag | Heizelement |
US8286107B2 (en) * | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
US7979829B2 (en) | 2007-02-20 | 2011-07-12 | Tela Innovations, Inc. | Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US7799612B2 (en) * | 2007-06-25 | 2010-09-21 | Spansion Llc | Process applying die attach film to singulated die |
KR20090046993A (ko) | 2007-11-07 | 2009-05-12 | 주식회사 동부하이텍 | 반도체 소자 및 그 제조 방법 |
US8648444B2 (en) * | 2007-11-29 | 2014-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer scribe line structure for improving IC reliability |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
JP5309728B2 (ja) * | 2008-06-27 | 2013-10-09 | 富士通セミコンダクター株式会社 | レチクルデータ作成方法及びレチクルデータ作成装置 |
KR101749351B1 (ko) | 2008-07-16 | 2017-06-20 | 텔라 이노베이션스, 인코포레이티드 | 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현 |
US9122832B2 (en) * | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US20100200957A1 (en) | 2009-02-06 | 2010-08-12 | Qualcomm Incorporated | Scribe-Line Through Silicon Vias |
JP5501668B2 (ja) | 2009-06-17 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法、半導体チップ及び半導体ウェハ |
JP5607317B2 (ja) | 2009-06-17 | 2014-10-15 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法及び半導体ウェハ |
US8661392B2 (en) * | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
JP2011134893A (ja) * | 2009-12-24 | 2011-07-07 | Renesas Electronics Corp | 半導体装置 |
US8884402B2 (en) | 2010-04-28 | 2014-11-11 | United Microelectronics Corp. | Circuit layout structure |
JP5516223B2 (ja) * | 2010-08-19 | 2014-06-11 | 富士通株式会社 | ダミーメタル配置評価装置、ダミーメタル配置評価方法及びダミーメタル配置評価プログラム |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
KR20150062556A (ko) * | 2013-11-29 | 2015-06-08 | 삼성전기주식회사 | 휨방지 부재가 구비된 스트립 레벨 기판 및 이의 제조 방법 |
KR102633112B1 (ko) | 2016-08-05 | 2024-02-06 | 삼성전자주식회사 | 반도체 소자 |
KR20200102608A (ko) | 2019-02-21 | 2020-09-01 | 삼성전자주식회사 | Mim 커패시터 및 반도체 소자 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000340568A (ja) * | 1999-03-19 | 2000-12-08 | Toshiba Corp | 半導体装置 |
JP2000286263A (ja) | 1999-03-29 | 2000-10-13 | Nec Corp | 半導体装置及びその製造方法 |
JP2000340529A (ja) * | 1999-05-31 | 2000-12-08 | Mitsubishi Electric Corp | 半導体装置 |
US6528818B1 (en) * | 1999-12-14 | 2003-03-04 | Kla-Tencor | Test structures and methods for inspection of semiconductor integrated circuits |
JP3551877B2 (ja) | 2000-01-18 | 2004-08-11 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JP2001332556A (ja) * | 2000-05-25 | 2001-11-30 | Hitachi Ltd | 半導体装置の製造方法 |
JP2002208676A (ja) | 2001-01-10 | 2002-07-26 | Mitsubishi Electric Corp | 半導体装置、半導体装置の製造方法及び半導体装置の設計方法 |
JP2003045876A (ja) * | 2001-08-01 | 2003-02-14 | Seiko Epson Corp | 半導体装置 |
-
2003
- 2003-01-29 JP JP2003021084A patent/JP4136684B2/ja not_active Expired - Lifetime
- 2003-11-19 US US10/715,503 patent/US6841880B2/en not_active Expired - Lifetime
- 2003-12-11 CN CNB200310120446XA patent/CN1316584C/zh not_active Expired - Lifetime
- 2003-12-12 EP EP03090434A patent/EP1443552B1/en not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100454522C (zh) * | 2005-01-28 | 2009-01-21 | 恩益禧电子股份有限公司 | 半导体器件 |
TWI466257B (zh) * | 2010-03-31 | 2014-12-21 | Toshiba Kk | 半導體裝置及其製造方法 |
CN102445864A (zh) * | 2011-10-21 | 2012-05-09 | 上海华力微电子有限公司 | 一种降低光刻对准失效率的方法 |
CN103346129A (zh) * | 2013-05-21 | 2013-10-09 | 北京新雷能科技股份有限公司 | 一种陶瓷封装外壳及其制作方法、芯片封装方法 |
CN103346129B (zh) * | 2013-05-21 | 2016-07-06 | 北京新雷能科技股份有限公司 | 一种陶瓷封装外壳及其制作方法、芯片封装方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1316584C (zh) | 2007-05-16 |
EP1443552A3 (en) | 2005-04-20 |
US6841880B2 (en) | 2005-01-11 |
JP4136684B2 (ja) | 2008-08-20 |
EP1443552A2 (en) | 2004-08-04 |
EP1443552B1 (en) | 2011-11-16 |
US20040145028A1 (en) | 2004-07-29 |
JP2004235357A (ja) | 2004-08-19 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: RENESAS ELECTRONICS CO., LTD. Free format text: FORMER OWNER: NEC CORP. Effective date: 20101119 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20101119 Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corp. Address before: Kanagawa, Japan Patentee before: NEC ELECTRONICS Corp. |
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CP02 | Change in the address of a patent holder | ||
CP02 | Change in the address of a patent holder |
Address after: Tokyo, Japan Patentee after: Renesas Electronics Corp. Address before: Kanagawa, Japan Patentee before: Renesas Electronics Corp. |
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CX01 | Expiry of patent term |
Granted publication date: 20070516 |
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CX01 | Expiry of patent term |