CN1275246A - 半导体装置及其制造方法、电路基板和电子装置 - Google Patents
半导体装置及其制造方法、电路基板和电子装置 Download PDFInfo
- Publication number
- CN1275246A CN1275246A CN99801439A CN99801439A CN1275246A CN 1275246 A CN1275246 A CN 1275246A CN 99801439 A CN99801439 A CN 99801439A CN 99801439 A CN99801439 A CN 99801439A CN 1275246 A CN1275246 A CN 1275246A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- bonding agent
- semiconductor device
- semiconductor element
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 233
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims description 86
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 239000004020 conductor Substances 0.000 claims abstract description 73
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 10
- 239000007767 bonding agent Substances 0.000 claims description 129
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 19
- 239000002245 particle Substances 0.000 claims description 14
- 208000034189 Sclerosis Diseases 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 238000009434 installation Methods 0.000 claims description 12
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 229920001169 thermoplastic Polymers 0.000 claims description 5
- 239000004416 thermosoftening plastic Substances 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000005304 joining Methods 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 230000005012 migration Effects 0.000 description 7
- 238000013508 migration Methods 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 201000009310 astigmatism Diseases 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000012467 final product Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N Acrylic acid Chemical class OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000002270 dispersing agent Substances 0.000 description 1
- 239000000975 dye Substances 0.000 description 1
- 238000001227 electron beam curing Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
- H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/83095—Temperature settings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83859—Localised curing of parts of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83862—Heat curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83874—Ultraviolet [UV] curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
一种半导体装置的制造方法,包括:使热硬化性的各向异性导电材料16介入到基板12与半导体元件20之间的第1工序;在半导体元件20与基板12之间施加压力和热、使布线图形10与电极22导电性地导通、在各向异性导电材料16从半导体元件20溢出的状态下,在与半导体元件20接触的区域中使各向异性导电材料16硬化的第2工序;以及对各向异性导电材料16的与半导体元件20接触的区域以外的区域进行加热的第3工序。
Description
技术领域
本发明涉及半导体装置及其制造方法、电路基板和电子装置。
背景技术
随着近年来的电子装置的小型化,要求适合于高密度安装的半导体装置的封装。为了适应这一情况,已开发了BGA(球状栅格阵列)及CSP(芯片比例/尺寸封装)那样的表面安装型封装。在表面安装型封装中,有时使用与半导体芯片连接的、形成了布线图形的基板。
在现有的表面安装型封装中,由于有为了保护布线图形等而形成保护膜的工序,故难以提高生产性。
本发明是为了解决该问题而进行的,其目的在于提供在可靠性和生产性方面良好的半导体装置的制造方法和利用该方法制造的半导体装置、电路基板和电子装置。
发明的公开
(1)与本发明有关的半导体装置的制造方法包括:
使粘接剂介入到基板的形成了布线图形的面与半导体元件的形成了电极的面之间的第1工序;
在上述半导体元件与上述基板之间施加能量、使上述布线图形与上述电极导电性地导通、在上述粘接剂从上述半导体元件溢出的状态下,使上述粘接剂的粘接能在与上述半导体元件接触的区域中显现出来的第2工序;以及
在上述粘接剂的与上述半导体元件接触的区域以外的区域中施加能量的第3工序。
(2)在该半导体装置的制造方法中,
上述粘接剂是热硬化性的,
在上述第2工序中施加的上述能量是压力和热,
在上述第3工序中施加的上述能量可以是热。
按照这一点,粘接剂在与半导体元件接触的区域中硬化,其后,对接触区域以外的区域进行加热使之硬化。这样,粘接剂在从半导体元件溢出的区域中也硬化。由此,可防止粘接剂剥落、水分侵入、引起布线图形的迁移(migration)。此外,由于粘接剂硬化,故也可防止含有水分。
(3)在该半导体装置的制造方法中,
导电粒子被分散于上述粘接剂中,可利用上述导电粒子使上述布线图形与上述电极导电性地导通。
按照这一点,由于利用导电粒子使布线图形与电极导电性地导通,故可以在可靠性和生产性方面良好的方法来制造半导体装置。
(4)在该半导体装置的制造方法中,
可在上述第1工序之前预先在上述半导体元件的形成了上述电极的上述面上设置上述粘接剂。
(5)在该半导体装置的制造方法中,
可在上述第1工序之前预先在上述基板的形成了上述布线图形的面上设置上述粘接剂。
(6)在该半导体装置的制造方法中,
在上述第3工序中的施加能量的区域可以是位于上述粘接剂中的在上述第2工序中硬化未结束的部分的区域。
(7)在该半导体装置的制造方法中,
在上述第3工序中,可利用加热夹具来加热上述粘接剂。
(8)在该半导体装置的制造方法中,
可使与上述粘接剂的脱模性高的脱模层介入到上述加热夹具与上述粘接剂之间来加热上述粘接剂。
(9)在该半导体装置的制造方法中,
可将上述脱模层预先设置在上述加热夹具上。
(10)在该半导体装置的制造方法中,
可将上述脱模层预先设置在上述粘接剂上。
(11)在该半导体装置的制造方法中,
在上述第3工序中,可用非接触的方式对上述粘接剂施加能量。
(12)在该半导体装置的制造方法中,
包含在上述基板上形成与上述布线图形连接的焊锡球时的回流(reflow)工序,
可在上述回流工序中进行上述第3工序。
(13)在该半导体装置的制造方法中,
包含将上述半导体元件之外的电子部件导电性地接合到上述布线图形上时的回流工序,
可在上述回流工序中进行上述第3工序。
(14)在该半导体装置的制造方法中,
可在上述第3工序后,在上述粘接剂的与上述半导体元件的接触区域以外的区域中切断上述基板。
(15)在该半导体装置的制造方法中,
在上述第2工序中,可使上述粘接剂绕入到上述半导体元件的侧面的至少一部分上。
按照这一点,由于粘接剂覆盖半导体元件的侧面的至少一部分,故可保护半导体元件免受机械的破坏,除此以外,可防止水分到达电极、可防止电极受到腐蚀。
(16)在该半导体装置的制造方法中,
可在上述第1工序前,以比上述第2工序结束后的上述半导体元件与上述基板的间隔大的厚度来设置上述粘接剂,在上述第2工序中,在上述半导体元件与上述基板之间进行加压,使上述粘接剂从上述半导体元件溢出。
(17)在该半导体装置的制造方法中,
上述粘接剂可含有遮光性材料。
按照这一点,由于粘接剂含有遮光性材料,故可遮住朝向半导体元件的具有电极的面的散光。由此,可防止半导体元件的误操作。
(18)与本发明有关的半导体装置的制造方法包括:
使粘接剂介入到基板的形成了布线图形的面与半导体元件的形成了电极的面之间的第1工序;
使上述布线图形与上述电极导电性地导通、在上述粘接剂从上述半导体元件溢出的状态下,使位于上述粘接剂的至少上述半导体元件与上述基板之间的部分硬化的第2工序;以及
在上述粘接剂的从上述半导体元件溢出的区域中切断上述基板的第3工序。
按照本发明,由于粘接剂从半导体元件溢出而被设置后被切断,故没有必要以与半导体元件的大小对应的大小进行准确的位置重合。此外,由于粘接剂的从半导体元件溢出的区域与基板一起被切断,故基板的整个面被粘接剂所覆盖,可防止布线图形的迁移。
(19)在该半导体装置的制造方法中,
上述粘接剂是热硬化性的粘接剂,可在上述第2工序中对上述粘接剂进行加热。
(20)在该半导体装置的制造方法中,
上述粘接剂是热塑性的粘接剂,可在上述第2工序中对上述粘接剂进行冷却。
(21)在该半导体装置的制造方法中,
导电粒子被分散于上述粘接剂中,可利用上述导电粒子使上述布线图形与上述电极导电性地导通。
(22)在该半导体装置的制造方法中,
可在上述第1工序之前预先在上述半导体元件的形成了上述电极的上述面上设置上述粘接剂。
(23)在该半导体装置的制造方法中,
可在上述第1工序之前预先在上述基板的形成了上述布线图形的面上设置上述粘接剂。
(24)在该半导体装置的制造方法中,
在上述第3工序中的切断位置可在上述基板的上述布线图形的端部的外侧的区域中。
(25)在该半导体装置的制造方法中,
在上述第2工序中,使上述粘接剂的整体硬化,
在上述第3工序中,可切断已硬化的上述粘接剂。
按照这一点,由于切断已硬化的粘接剂,故可容易地进行切断。
(26)在该半导体装置的制造方法中,
在上述第2工序中,可使上述粘接剂绕入到上述半导体元件的侧面的至少一部分上。
按照这一点,由于粘接剂覆盖半导体元件的侧面的至少一部分,故可保护半导体元件免受机械的破坏,除此以外,可防止水分到达电极、可防止电极受到腐蚀。
(27)在该半导体装置的制造方法中,
可在上述第1工序前,以比上述第2工序结束后的上述半导体元件与上述基板的间隔大的厚度来设置上述粘接剂,在上述第2工序中在上述半导体元件与上述基板之间进行加压,使上述粘接剂从上述半导体元件溢出。
(28)在该半导体装置的制造方法中,
上述粘接剂可含有遮光性材料。
按照这一点,由于粘接剂含有遮光性材料,故可遮住朝向半导体元件的具有电极的面的散光。由此,可防止半导体元件的误操作。
(29)与本发明有关的半导体装置包括:具有电极的半导体元件;形成了布线图形的基板;以及热硬化性的粘接剂,
上述电极与上述布线图形导电性地导通,
上述粘接剂介入到上述基板的形成了上述布线图形的面与上述半导体元件的形成了上述电极的面之间,以从上述半导体元件溢出的大小被设置,全部粘接剂硬化了。
按照这一点,由于粘接剂在与半导体元件接触的区域的外侧也硬化了,故可防止粘接剂剥落、水分侵入及引起布线图形的迁移。此外,由于全部粘接剂硬化了,故也可防止含有水分。
(30)在该半导体装置中,
导电粒子可被分散于上述粘接剂中,构成了各向异性导电材料。
按照这一点,由于利用各向异性导电材料来导电性地导通布线图形与电极,故在可靠性和生产性方面良好。
(31)在该半导体装置中,
上述各向异性导电材料可被设置成覆盖整个上述布线图形。
(32)在该半导体装置中,
上述粘接剂可覆盖上述半导体元件的侧面的至少一部分。
按照这一点,由于粘接剂覆盖半导体元件的侧面的至少一部分,故可保护半导体元件免受机械的破坏。此外,由于用粘接剂覆盖从电极到很远的位置,故水分难以到达电极、可防止电极受到腐蚀。
(33)在该半导体装置中,
上述粘接剂可含有遮光性材料。
按照这一点,由于粘接剂含有遮光性材料,故可遮住朝向半导体元件的具有电极的面的散光。由此,可防止半导体元件的误操作。
(34)与本发明有关的半导体装置利用上述方法来制造。
(35)在与本发明有关的电路基板中安装了上述半导体装置。
(36)与本发明有关的电子装置具有上述电路基板。
附图的简单说明
图1A~图1D是示出与第1实施形态有关的半导体装置的制造方法的图,图2A和图2B是示出第1实施形态的变形例的图,图3A和图3B是示出与第2实施形态有关的半导体装置的制造方法的图,图4A和图4B是示出与第3实施形态有关的半导体装置的制造方法的图,图5A和图5B是示出与第4实施形态有关的半导体装置的制造方法的图,图6是示出安装了与本实施形态有关的半导体装置的电路基板的图,图7是示出具备安装了与本实施形态有关的半导体装置的电路基板的电子装置的图。
实施发明用的最佳形态
以下,参照附图说明本发明的优选实施形态。
(第1实施形态)
图1A~图1D是示出与第1实施形态有关的半导体装置的制造方法的图。在本实施形态中,如图1A中所示,使用在至少一个面18上形成了布线图形10的基板12。
基板12可以是柔性基板等的由有机系列材料形成的基板、金属系列基板等的由无机系列材料形成的基板、或将两者组合起来的基板中的任一种。作为柔性基板,可使用带载体(tape carrier)。在基板12的导电性高的情况下,在基板12与布线图形10之间和在通孔14的内侧、或除此以外,在与布线图形10的形成面相反的面上形成绝缘膜。
在基板12上形成了通孔14,布线图形10跨过通孔14之上而被形成。此外,作为布线图形10的一部分,在通孔14上形成了外部电极形成用的接合区(land)17。
如果准备这样的基板12,则作为粘接剂的一例,在基板12上设置各向异性导电材料16。在以下的说明中,各向异性导电材料是粘接剂的一例。各向异性导电材料16是在粘接剂(binder)中分散了导电粒子(导电性填料)的材料,也有添加分散剂的情况。可将各向异性导电材料16预先形成为片状之后粘贴在基板12上,也可以液状直接设置在基板12上。此外,可将各向异性导电材料16设置成比半导体元件20的具有电极22的面24大,但也可设置成比面24小,以通过被挤压而从面24溢出的量来设置。
或者,也可在半导体元件20的面24上以通过被挤压而从面24溢出的量来设置各向异性导电材料16。再有,即使使用不含有导电粒子的粘接剂,也能导电性地连接电极22与布线图形10。
在本实施形态中,可使用热硬化性粘接剂作为各向异性导电材料,再者,各向异性导电材料16可含有遮光性材料。作为遮光性材料,例如可使用使黑色染料或黑色颜料分散在粘接剂树脂中的材料。
作为所使用的粘接剂,可使用以环氧系列为代表例的热硬化型粘接剂,也可使用以环氧系列或丙烯酸系列为代表例的光硬化型粘接剂。再者,也可使用电子束硬化类型、热塑(热粘接)类型的粘接剂。在使用热硬化型以外的粘接剂的情况下,在以下的全部实施形态中,施加能量来代替加热或加压即可。
其次,例如在各向异性导电材料16上放置半导体元件20。详细地说,将半导体元件20的具有电极22的面24朝向各向异性导电材料16来放置半导体元件20。此外,这样来配置半导体元件20,使得电极22位于布线图形10的电极连接用的接合区(未图示)上。再有,可只在半导体元件20的两边上形成了电极22,也可在四边上形成了电极22。关于电极22,大多使用在铝焊区(pad)上设置了金或焊锡等凸起的电极,但也可使用在布线图形10一侧对上述的凸起或布线图形10进行刻蚀而作成的凸起。
利用以上的工序,各向异性导电材料16介入到半导体元件20的形成了电极22的面24与基板12的形成了布线图形10的面18之间。然后,将夹具30压在与形成了电极22的面24相反的面26上,在基板12的方向上对半导体元件20进行加压。或者,在半导体元件20与基板12之间施加压力。作为粘接剂的一例的各向异性导电材料16,即使在被设置在半导体元件20的面24的区域内的情况下,也由于压力而从面24溢出。此外,夹具30内置了加热器32,对半导体元件20进行加热。再有,作为夹具30,如果考虑对各向异性导电材料16的已溢出的部分也打算尽可能地施加热量,则最好使用具有比半导体元件20的平面面积大的平面面积的夹具。通过这样做,热量容易施加到半导体元件20的周围。
这样,如图1B中所示,半导体元件20的电极22与布线图形10通过各向异性导电材料16的导电粒子导电性地连接。按照本实施形态,由于利用各向异性导电材料16使布线图形10与电极22导电性地导通,故可用在可靠性和生产性方面良好的方法来制造半导体装置。
此外,由于利用夹具30来加热半导体元件20,故各向异性导电材料16在与半导体元件20接触的区域中硬化。但是,在该状态下,由于在没有与半导体元件20接触的区域或离开半导体元件20的区域中,热量不能到达各向异性导电材料16上,故没有完全硬化。用以下的工序来进行该区域的硬化。
如图1C中所示,在基板12的通孔14内及其附近,设置了焊锡34。焊锡34例如可采用膏状焊锡、利用印刷法来设置。此外,也可在上述位置上放置预先形成的焊锡球。
接着,在回流(reflow)工序中加热焊锡34,如图1D中所示,形成焊锡球36。焊锡球36成为外部电极。在该回流工序中,不仅对焊锡34进行加热,也对各向异性导电材料16进行加热。利用该热量,使各向异性导电材料16的未硬化的区域也硬化了。即,在各向异性导电材料16中,没有与半导体元件20接触的区域或离开半导体元件20的区域利用形成焊锡球36用的回流工序进行硬化。
按照这样得到的半导体装置1,由于全部各向异性导电材料16已硬化,故可防止在半导体元件20的外周部处各向异性导电材料16从基板12剥落、水分侵入而引起布线图形10的迁移(migration)。此外,由于整个各向异性导电材料16硬化了,故也可防止各向异性导电材料16中含有水分。
再者,在半导体装置1中,由于利用含有遮光性材料的各向异性导电材料16来覆盖半导体元件20的具有电极22的面24,故可遮住朝向面24的散光。由此,可防止半导体元件20的误操作。
图2A和图2B是示出第1实施形态的变形例的图。在该变形例中,对于与第1实施形态相同的结构采用相同的符号,省略关于该结构和起因于该结构的效果的说明。这一点在以下的实施形态中也是同样的。
图2A中示出的工序在图1B的工序后及图1C的工序前进行。具体地说,利用加热夹具38加热各向异性导电材料16中的没有与半导体元件20接触的区域或离开半导体元件20的区域。最好在夹具38上设置由与作为粘接剂的一例的各向异性导电材料16的脱模性高的聚四氟乙烯等构成的脱模层39,使得未硬化的各向异性导电材料16难以附着于该加热夹具38上。或者,也可将脱模层39设置在作为粘接剂的一例的各向异性导电材料16上。再者,也可以不与作为粘接剂的一例的各向异性导电材料16接触的方式对其进行加热。通过这样做,可使各向异性导电材料16中的没有与半导体元件20接触的区域或离开半导体元件20的区域硬化。此外,也可不使用夹具,而是使用能部分地进行加热的热风或光加热器。
或者,如图2B中所示,也可在图1B的工序后及图1C的工序前进行将与半导体元件20有区别的电子部件40导电性地接合到布线图形10上用的回流工序。利用该回流工序,各向异性导电材料16中的没有与半导体元件20接触的区域或离开半导体元件20的区域被加热而硬化。再有,作为电子部件40,例如有电阻器、电容器、线圈、振荡器、滤波器、温度传感器、热敏电阻、变阻器、电位器或熔断器等。
由于利用这些变形例也能使全部各向异性导电材料16硬化,故可防止各向异性导电材料16从基板12剥落、水分侵入而引起布线图形10的迁移。此外,由于整个各向异性导电材料16硬化了,故也可防止含有水分。
此外,在上述工序后,可在作为粘接剂的一例的各向异性导电材料16从半导体元件20溢出的区域中切断基板12。
在本实施形态中,叙述了使用单面布线基板作为基板12的例子,但不限于此,也可使用两面布线板或多层布线板。此时,可在通孔中不形成焊锡,而在与半导体元件放置面相反的面上设置的接合区上来形成焊锡球。此外,也可使用其它的导电性凸起来代替焊锡球。再者,也可利用引线键合来进行半导体元件与基板的连接。这些在以后的实施形态中也是同样的。
此外,在本实施形态中,不仅可使用热硬化性的粘接剂也可使用作为热塑性的粘接剂的一例的各向异性导电材料16。热塑性的粘接剂冷却后可使其硬化。或者,也可使用由紫外线等的放射线进行硬化的粘接剂。这一点在以下的实施形态中也是同样的。
(第2实施形态)
图3A和图3B是示出与第2实施形态有关的半导体装置的制造方法的图。本实施形态接着第1实施形态来进行。
即,在本实施形态中,接着图1D的工序,如图3A中所示,在用固定刃41压住的同时利用可动刃42以比半导体元件20稍大的的尺寸来切断各向异性导电材料16和基板12,得到如图3B中示出的半导体装置2。切断的装置不限于此,如果有其它的切断装置和固定装置,则也可应用。在半导体装置2中,由于与各向异性导电材料16一起切断基板12,故两者的切断面为同一面,各向异性导电材料16覆盖基板12的整个面。而且,由于布线图形10不露出,故水分不到达布线图形10,可防止迁移现象。
此外,按照本实施形态,由于各向异性导电材料16被切断,故也没有必要预先以与半导体元件20相等或稍大的尺寸进行切断,没有必要准确地进行位置重合以便与半导体元件20的位置对应。
再有,本实施形态是在形成了焊锡球36之后切断各向异性导电材料16和基板12的例子,但只要是在各向异性导电材料16上至少放置了半导体元件20之后,则切断的时期可以是与焊锡球36的形成无关的任何时间。但是,各向异性导电材料16最好至少在与半导体元件20的接触区域中硬化。此时,可防止半导体元件20与布线图形10的位置偏移。此外,各向异性导电材料16在切断部位处与处于未硬化的状态相比,处于硬化状态的切断工序比较容易。
再有,如果切断基板12,则可一度使作为粘接剂的一例的各向异性导电材料16的整体硬化。例如,在导电性地连接半导体元件20的电极22与布线图形10时,对于作为粘接剂的一例的各向异性导电材料16的整体,或是加热或是冷却即可。在使用热硬化性的粘接剂时,具体地说,也可使用与半导体元件20和从半导体元件20溢出的粘接剂这两者接触的夹具。或者,也可利用烘箱来加热。
(第3实施形态)
图4A和图4B是示出与第3实施形态有关的半导体装置的制造方法的图。在本实施形态中,使用第1实施形态的基板12,在基板12上形成保护层50。保护层50是要覆盖布线图形10使其不接触水分的层,例如可使用焊剂抗蚀剂。
在除了比将半导体元件20安装在基板12上用的区域宽的区域52之外,形成了保护层50。即,区域52比半导体元件20的具有电极22的面24大,在该区域52内,在布线图形10上形成了与半导体元件20的电极22连接用的接合区(未图示)。或者,也可至少避开与半导体元件20的电极22的导电性的连接部来形成保护层50。
在这样的基板12上,作为第1实施形态的各向异性导电材料16设置由可选择的材料构成的各向异性导电材料54(粘接剂)。再有,各向异性导电材料54不必含有遮光性材料,但如果含有遮光性材料,则可得到与第1实施形态同样的效果。
在本实施形态中,从半导体元件20的安装区到保护层50设置各向异性导电材料54。即,各向异性导电材料54在不形成保护层50的区域52中覆盖布线图形10和基板12,同时,重叠在形成保护层50的区域52的端部上而被形成。或者,也可在半导体元件20一侧设置作为粘接剂的一例的各向异性导电材料54。详细地说,可应用在第1实施形态中已说明的内容。
然后,如图4A中所示,通过夹具30在基板12的方向上将半导体元件20加压并加热。或者,至少在半导体元件20与基板12之间施加压力。这样,如图4B中所示,半导体元件20的电极22与布线图形10导电性地导通。其后,利用与图1C和图1D中示出的同样的工序,形成焊锡球,可得到半导体装置。
按照本实施形态,各向异性导电材料54不仅在不形成保护层50的区域52中形成,而且重叠在形成保护层50的区域52的端部上而被形成。因而,由于在各向异性导电材料54与保护层50之间不形成间隙,故布线图形10不露出,可防止迁移现象。
再有,在本实施形态中,最好也在从半导体元件20溢出的区域中使各向异性导电材料54硬化。该硬化的工序可应用与第1实施形态同样的工序。
(第4实施形态)
图5A和图5B是示出与第4实施形态有关的半导体装置的制造方法的图。在本实施形态中,使用第1实施形态的基板12,在基板12上设置各向异性导电材料56(粘接剂)。在本实施形态中,与第1实施形态不同之点在于各向异性导电材料56的厚度。即,如图5A中所示,在本实施形态中,各向异性导电材料56的厚度比图1A中示出的各向异性导电材料16的厚度厚。具体地说,各向异性导电材料56的厚度比半导体元件20的具有电极22的面24与在基板12上形成的布线图形10的间隔厚。此外,各向异性导电材料56至少比半导体元件20大一些。再有,关于该厚度和大小的条件,至少满足某一方即可。
然后,如图5A中所示,例如,通过夹具30在基板12的方向上将半导体元件20加压并加热。如果这样做,则如图5B中所示,各向异性导电材料56绕入到半导体元件20的侧面28的一部分或全部上。其后,利用与图1C和图1D中示出的同样的工序,形成焊锡球,可得到半导体装置。
按照本实施形态,由于半导体元件20的侧面28的至少一部分被各向异性导电材料56覆盖,故可保护半导体元件20免受机械的破坏,除此以外,由于各向异性导电材料56覆盖到离电极22远的位置,故可防止电极22等受到腐蚀。
上述的实施形态以FDB(倒装键合)的CSP(芯片尺寸/比例封装)为中心进行了记述,但即使在应用了FDB的半导体装置、例如应用了COF(在膜上的芯片)及COB(在板上的芯片)的半导体装置等中,也可应用本发明。
在图6中,示出了安装了利用与上述的实施形态有关的方法制造的半导体装置1100的电路基板1000。一般使用例如玻璃环氧基板等的有机系列基板作为电路基板1000。在电路基板1000上以成为所希望的电路的方式形成了例如由铜构成的布线图形。而且,通过以机械方式连接布线图形与半导体装置1100的外部电极,来谋求它们的导电性的导通。
再有,由于可使半导体装置1100的安装面积减小到用裸芯片安装的面积,故如果在电子装置中使用该电路基板1000,就可谋求电子装置本身的小型化。此外,在同一面积内可确保更大的安装空间,还可谋求高功能化。
而且,作为具备该电路基板1000的电子装置,在图7中示出了笔记本型个人计算机1200。
再有,也可将本发明应用于各种面安装用的电子部件,不管其是有源部件还是无源部件。作为电子部件,例如有电阻器、电容器、线圈、振荡器、滤波器、温度传感器、热敏电阻、变阻器、电位器或熔断器等。
Claims (36)
1.一种半导体装置的制造方法,其特征在于,包括:
使粘接剂介入到基板的形成了布线图形的面与半导体元件的形成了电极的面之间的第1工序;
在上述半导体元件与上述基板之间施加能量、使上述布线图形与上述电极导电性地导通、在上述粘接剂从上述半导体元件溢出的状态下,使上述粘接剂的粘接能在与上述半导体元件接触的区域中显现出来的第2工序;以及
在上述粘接剂的与上述半导体元件接触的区域以外的区域中施加能量的第3工序。
2.如权利要求1中所述的半导体装置的制造方法,其特征在于:
上述粘接剂是热硬化性的,
在上述第2工序中施加的上述能量是压力和热,
在上述第3工序中施加的上述能量是热。
3.如权利要求1中所述的半导体装置的制造方法,其特征在于:
导电粒子被分散于上述粘接剂中,利用上述导电粒子使上述布线图形与上述电极导电性地导通。
4.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第1工序之前,预先在上述半导体元件的形成了上述电极的上述面上设置上述粘接剂。
5.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第1工序之前,预先在上述基板的形成了上述布线图形的面上设置上述粘接剂。
6.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第3工序中的施加能量的区域是位于上述粘接剂中的在上述第2工序中硬化未结束的部分的区域。
7.如权利要求2中所述的半导体装置的制造方法,其特征在于:
在上述第3工序中,利用加热夹具来加热上述粘接剂。
8.如权利要求7中所述的半导体装置的制造方法,其特征在于:
使与上述粘接剂的脱模性高的脱模层介入到上述加热夹具与上述粘接剂之间来加热上述粘接剂。
9.如权利要求8中所述的半导体装置的制造方法,其特征在于:
将上述脱模层预先设置在上述加热夹具上。
10.如权利要求8中所述的半导体装置的制造方法,其特征在于:
将上述脱模层预先设置在上述粘接剂上。
11.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第3工序中,用非接触的方式对上述粘接剂施加能量。
12.如权利要求1中所述的半导体装置的制造方法,其特征在于:
包含在上述基板上形成与上述布线图形连接的焊锡球时的回流工序,
在上述回流工序中进行上述第3工序。
13.如权利要求1中所述的半导体装置的制造方法,其特征在于:
包含将上述半导体元件之外的电子部件导电性地接合到上述布线图形上时的回流工序,
在上述回流工序中进行上述第3工序。
14.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第3工序后,在上述粘接剂的与上述半导体元件的接触区域以外的区域中切断上述基板。
15.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第2工序中,使上述粘接剂绕入到上述半导体元件的侧面的至少一部分上。
16.如权利要求15中所述的半导体装置的制造方法,其特征在于:
在上述第1工序前,以比上述第2工序结束后的上述半导体元件与上述基板的间隔大的厚度来设置上述粘接剂,在上述第2工序中,在上述半导体元件与上述基板之间进行加压,使上述粘接剂从上述半导体元件溢出。
17.如权利要求1中所述的半导体装置的制造方法,其特征在于:
上述粘接剂含有遮光性材料。
18.一种半导体装置的制造方法,其特征在于,包括:
使粘接剂介入到基板的形成了布线图形的面与半导体元件的形成了电极的面之间的第1工序;
使上述布线图形与上述电极导电性地导通、在上述粘接剂从上述半导体元件溢出的状态下,使位于上述粘接剂的至少上述半导体元件与上述基板之间的部分硬化的第2工序;以及
在上述粘接剂的从上述半导体元件溢出的区域中切断上述基板的第3工序。
19.如权利要求18中所述的半导体装置的制造方法,其特征在于:
上述粘接剂是热硬化性的粘接剂,在上述第2工序中对上述粘接剂进行加热。
20.如权利要求18中所述的半导体装置的制造方法,其特征在于:
上述粘接剂是热塑性的粘接剂,在上述第2工序中对上述粘接剂进行冷却。
21.如权利要求18中所述的半导体装置的制造方法,其特征在于:
导电粒子被分散于上述粘接剂中,利用上述导电粒子使上述布线图形与上述电极导电性地导通。
22.如权利要求18中所述的半导体装置的制造方法,其特征在于:
在上述第1工序之前预先在上述半导体元件的形成了上述电极的上述面上设置上述粘接剂。
23.如权利要求18中所述的半导体装置的制造方法,其特征在于:
在上述第1工序之前预先在上述基板的形成了上述布线图形的面上设置上述粘接剂。
24.如权利要求18中所述的半导体装置的制造方法,其特征在于:
在上述第3工序中的切断位置在上述基板的上述布线图形的端部的外侧的区域中。
25.如权利要求18中所述的半导体装置的制造方法,其特征在于:
在上述第2工序中,使上述粘接剂的整体硬化,
在上述第3工序中,切断已硬化的上述粘接剂。
26.如权利要求18中所述的半导体装置的制造方法,其特征在于:
在上述第2工序中,使上述粘接剂绕入到上述半导体元件的侧面的至少一部分上。
27.如权利要求26中所述的半导体装置的制造方法,其特征在于:
在上述第1工序前,以比上述第2工序结束后的上述半导体元件与上述基板的间隔大的厚度来设置上述粘接剂,在上述第2工序中在上述半导体元件与上述基板之间进行加压,使上述粘接剂从上述半导体元件溢出。
28.如权利要求18中所述的半导体装置的制造方法,其特征在于:
上述粘接剂含有遮光性材料。
29.一种半导体装置,其特征在于:
包括:具有电极的半导体元件;形成了布线图形的基板;以及热硬化性的粘接剂,
上述电极与上述布线图形导电性地导通,
上述粘接剂介入到上述基板的形成了上述布线图形的面与上述半导体元件的形成了上述电极的面之间,以从上述半导体元件溢出的大小被设置,全部粘接剂硬化了。
30.如权利要求29中所述的半导体装置,其特征在于:
导电粒子被分散于上述粘接剂中,构成了各向异性导电材料。
31.如权利要求30中所述的半导体装置,其特征在于:
上述各向异性导电材料被设置成覆盖整个上述布线图形。
32.如权利要求29中所述的半导体装置,其特征在于:
上述粘接剂覆盖上述半导体元件的侧面的至少一部分。
33.如权利要求29中所述的半导体装置,其特征在于:
上述粘接剂含有遮光性材料。
34.一种半导体装置,其特征在于:
利用权利要求1至权利要求28的任一项的方法来制造。
35.一种电路基板,其特征在于:
安装了如权利要求29至权利要求33的任一项中所述的半导体装置。
36.一种电子装置,其特征在于:
具有如权利要求35中所述的电路基板。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP201246/1998 | 1998-07-01 | ||
JP201246/98 | 1998-07-01 | ||
JP20124698 | 1998-07-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1275246A true CN1275246A (zh) | 2000-11-29 |
CN1143375C CN1143375C (zh) | 2004-03-24 |
Family
ID=16437769
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB998010650A Expired - Fee Related CN1143373C (zh) | 1998-07-01 | 1999-06-25 | 半导体装置及其制造方法、电路基板和电子装置 |
CNB998014397A Expired - Fee Related CN1143375C (zh) | 1998-07-01 | 1999-06-25 | 半导体装置及其制造方法、电路基板和电子装置 |
CNB998010669A Expired - Fee Related CN1143374C (zh) | 1998-07-01 | 1999-06-25 | 半导体装置及其制造方法、电路基板和电子装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB998010650A Expired - Fee Related CN1143373C (zh) | 1998-07-01 | 1999-06-25 | 半导体装置及其制造方法、电路基板和电子装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB998010669A Expired - Fee Related CN1143374C (zh) | 1998-07-01 | 1999-06-25 | 半导体装置及其制造方法、电路基板和电子装置 |
Country Status (8)
Country | Link |
---|---|
US (9) | US6462284B1 (zh) |
JP (3) | JP4448617B2 (zh) |
KR (3) | KR100510387B1 (zh) |
CN (3) | CN1143373C (zh) |
HK (3) | HK1032671A1 (zh) |
SG (1) | SG102032A1 (zh) |
TW (3) | TW454278B (zh) |
WO (3) | WO2000002243A1 (zh) |
Families Citing this family (74)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3815149B2 (ja) * | 1999-11-04 | 2006-08-30 | セイコーエプソン株式会社 | 部品実装方法および電気光学装置の製造方法 |
US6713854B1 (en) | 2000-10-16 | 2004-03-30 | Legacy Electronics, Inc | Electronic circuit module with a carrier having a mounting pad array |
US6487078B2 (en) * | 2000-03-13 | 2002-11-26 | Legacy Electronics, Inc. | Electronic module having a three dimensional array of carrier-mounted integrated circuit packages |
US7102892B2 (en) * | 2000-03-13 | 2006-09-05 | Legacy Electronics, Inc. | Modular integrated circuit chip carrier |
DE10019443A1 (de) * | 2000-04-19 | 2001-10-31 | Texas Instruments Deutschland | Vorrichtung zum Befestigen eines Halbleiter-Chips auf einem Chip-Träger |
US6395326B1 (en) * | 2000-05-31 | 2002-05-28 | Advanced Cardiovascular Systems, Inc. | Apparatus and method for depositing a coating onto a surface of a prosthesis |
DE10046296C2 (de) * | 2000-07-17 | 2002-10-10 | Infineon Technologies Ag | Elektronisches Chipbauteil mit einer integrierten Schaltung und Verfahren zu seiner Herstellung |
JP2002076589A (ja) * | 2000-08-31 | 2002-03-15 | Hitachi Ltd | 電子装置及びその製造方法 |
US7103970B2 (en) * | 2001-03-14 | 2006-09-12 | Legacy Electronics, Inc. | Method for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
US7337522B2 (en) * | 2000-10-16 | 2008-03-04 | Legacy Electronics, Inc. | Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
JP3653460B2 (ja) * | 2000-10-26 | 2005-05-25 | 三洋電機株式会社 | 半導体モジュールおよびその製造方法 |
JP2004520722A (ja) * | 2001-05-17 | 2004-07-08 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 基体及び当該基体に付属するチップを有する製品 |
JP2002353369A (ja) * | 2001-05-28 | 2002-12-06 | Sharp Corp | 半導体パッケージおよびその製造方法 |
US20030059520A1 (en) | 2001-09-27 | 2003-03-27 | Yung-Ming Chen | Apparatus for regulating temperature of a composition and a method of coating implantable devices |
JP4137551B2 (ja) * | 2002-08-09 | 2008-08-20 | 日東電工株式会社 | 透明導電性基板用表面保護フィルム及び表面保護フィルム付き透明導電性基板 |
JP2004134646A (ja) * | 2002-10-11 | 2004-04-30 | Seiko Epson Corp | バンプ付き半導体素子の実装構造、バンプ付き半導体素子の実装方法、及び電気光学装置、並びに電子機器 |
US20050012225A1 (en) * | 2002-11-15 | 2005-01-20 | Choi Seung-Yong | Wafer-level chip scale package and method for fabricating and using the same |
US7338557B1 (en) * | 2002-12-17 | 2008-03-04 | Advanced Cardiovascular Systems, Inc. | Nozzle for use in coating a stent |
KR100510518B1 (ko) * | 2003-01-30 | 2005-08-26 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 패키지 방법 |
US7087115B1 (en) | 2003-02-13 | 2006-08-08 | Advanced Cardiovascular Systems, Inc. | Nozzle and method for use in coating a stent |
TW587325B (en) * | 2003-03-05 | 2004-05-11 | Advanced Semiconductor Eng | Semiconductor chip package and method for manufacturing the same |
US7104224B2 (en) * | 2003-03-25 | 2006-09-12 | Plasmadrive, Inc. | System for improving the fuel efficiency of an engine |
KR100918528B1 (ko) * | 2003-03-31 | 2009-09-21 | 도쿄엘렉트론가부시키가이샤 | 처리부재 상에 인접한 코팅을 결합시키는 방법 |
US7341630B1 (en) | 2003-06-26 | 2008-03-11 | Advanced Cardiovascular Systems, Inc. | Stent coating system |
US7381361B2 (en) | 2003-06-26 | 2008-06-03 | Intel Corporation | Fabricating structures in micro-fluidic channels based on hydrodynamic focusing |
JP2005019815A (ja) * | 2003-06-27 | 2005-01-20 | Seiko Epson Corp | 半導体装置およびその製造方法、回路基板ならびに電子機器 |
US7294533B2 (en) * | 2003-06-30 | 2007-11-13 | Intel Corporation | Mold compound cap in a flip chip multi-matrix array package and process of making same |
JP3921459B2 (ja) * | 2003-07-11 | 2007-05-30 | ソニーケミカル&インフォメーションデバイス株式会社 | 電気部品の実装方法及び実装装置 |
US7672872B2 (en) * | 2003-08-22 | 2010-03-02 | Smurfit-Stone Container Enterprises, Inc. | Point-of-purchase display with RFID inventory control |
US7198675B2 (en) | 2003-09-30 | 2007-04-03 | Advanced Cardiovascular Systems | Stent mandrel fixture and method for selectively coating surfaces of a stent |
US6983884B2 (en) * | 2004-02-19 | 2006-01-10 | Neoteric Technology, Limited | Method and apparatus for monitoring transfusion of blood |
JP3943096B2 (ja) * | 2004-03-31 | 2007-07-11 | シャープ株式会社 | 半導体装置、及びその電気的検査方法、並びにそれを備えた電子機器 |
JP4426900B2 (ja) * | 2004-05-10 | 2010-03-03 | 三井金属鉱業株式会社 | プリント配線基板、その製造方法および半導体装置 |
JP4737370B2 (ja) * | 2004-10-29 | 2011-07-27 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
KR100610144B1 (ko) * | 2004-11-03 | 2006-08-09 | 삼성전자주식회사 | 플립 칩 조립 구조를 가지는 칩-온-보드 패키지의 제조 방법 |
US7632307B2 (en) * | 2004-12-16 | 2009-12-15 | Advanced Cardiovascular Systems, Inc. | Abluminal, multilayer coating constructs for drug-delivery stents |
WO2006076381A2 (en) | 2005-01-12 | 2006-07-20 | Legacy Electronics, Inc. | Radial circuit board, system, and methods |
EP1686512A1 (fr) * | 2005-02-01 | 2006-08-02 | NagraID S.A. | Procédé de placement d'un ensemble électronique sur un substrat et dispositif de placement d'un tel ensemble |
US7785932B2 (en) * | 2005-02-01 | 2010-08-31 | Nagraid S.A. | Placement method of an electronic module on a substrate and device produced by said method |
US8119458B2 (en) * | 2005-02-01 | 2012-02-21 | Nagraid S.A. | Placement method of an electronic module on a substrate |
DE102005013500A1 (de) * | 2005-03-23 | 2006-10-05 | Infineon Technologies Ag | Halbleiteranordnung und Verfahren zum Herstellen einer Halbleiteranordnung |
JP2006286798A (ja) * | 2005-03-31 | 2006-10-19 | Toray Eng Co Ltd | 実装方法および装置 |
JP4544143B2 (ja) | 2005-06-17 | 2010-09-15 | セイコーエプソン株式会社 | 半導体装置の製造方法、半導体装置、回路基板及び電子機器 |
CN100433250C (zh) * | 2005-06-17 | 2008-11-12 | 精工爱普生株式会社 | 半导体装置制造方法、半导体装置、电路基板 |
JP2007123413A (ja) * | 2005-10-26 | 2007-05-17 | Elpida Memory Inc | 半導体装置の製造方法 |
KR100753393B1 (ko) * | 2005-11-03 | 2007-09-13 | 아이엔지플렉스(주) | 박판적층 연성회로기판 및 그 제조방법 |
US20070117268A1 (en) * | 2005-11-23 | 2007-05-24 | Baker Hughes, Inc. | Ball grid attachment |
US7867547B2 (en) | 2005-12-19 | 2011-01-11 | Advanced Cardiovascular Systems, Inc. | Selectively coating luminal surfaces of stents |
TW200740320A (en) * | 2006-04-04 | 2007-10-16 | Chicony Electronic Co Ltd | Method of adhering electronic element and apparatus using the method |
JP2007302864A (ja) * | 2006-04-11 | 2007-11-22 | Hitachi Chem Co Ltd | 接着フィルム、これを用いた回路部材の接続構造 |
US8069814B2 (en) | 2006-05-04 | 2011-12-06 | Advanced Cardiovascular Systems, Inc. | Stent support devices |
US8603530B2 (en) | 2006-06-14 | 2013-12-10 | Abbott Cardiovascular Systems Inc. | Nanoshell therapy |
US8048448B2 (en) | 2006-06-15 | 2011-11-01 | Abbott Cardiovascular Systems Inc. | Nanoshells for drug delivery |
US8017237B2 (en) | 2006-06-23 | 2011-09-13 | Abbott Cardiovascular Systems, Inc. | Nanoshells on polymers |
JP5020629B2 (ja) * | 2006-12-28 | 2012-09-05 | パナソニック株式会社 | 電子部品の接続方法 |
JP5029026B2 (ja) * | 2007-01-18 | 2012-09-19 | 富士通株式会社 | 電子装置の製造方法 |
KR100891330B1 (ko) * | 2007-02-21 | 2009-03-31 | 삼성전자주식회사 | 반도체 패키지 장치와, 반도체 패키지의 제조방법과,반도체 패키지 장치를 갖는 카드 장치 및 반도체 패키지장치를 갖는 카드 장치의 제조 방법 |
US8048441B2 (en) | 2007-06-25 | 2011-11-01 | Abbott Cardiovascular Systems, Inc. | Nanobead releasing medical devices |
KR20090041756A (ko) * | 2007-10-24 | 2009-04-29 | 삼성전자주식회사 | 접착층을 갖는 프린트 배선 기판 및 이를 이용한 반도체패키지 |
US8390115B2 (en) * | 2008-04-03 | 2013-03-05 | Sharp Kabushiki Kaisha | Wiring board and semiconductor device using the wiring board |
WO2009154464A1 (en) * | 2008-06-20 | 2009-12-23 | Polymer Vision Limited | An integrated circuit comprising light absorbing adhesive |
FR2943849B1 (fr) * | 2009-03-31 | 2011-08-26 | St Microelectronics Grenoble 2 | Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur |
JP2010239022A (ja) * | 2009-03-31 | 2010-10-21 | Mitsui Mining & Smelting Co Ltd | フレキシブルプリント配線基板及びこれを用いた半導体装置 |
JP5533199B2 (ja) * | 2010-04-28 | 2014-06-25 | ソニー株式会社 | 素子の基板実装方法、および、その基板実装構造 |
JP5066231B2 (ja) * | 2010-07-28 | 2012-11-07 | 日東電工株式会社 | フリップチップ型半導体裏面用フィルム、短冊状半導体裏面用フィルムの製造方法、及び、フリップチップ型半導体装置 |
TWI453872B (zh) * | 2011-06-23 | 2014-09-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
WO2013153745A1 (ja) * | 2012-04-10 | 2013-10-17 | パナソニック株式会社 | 電極接合方法、電極接合構造体の製造方法、および電極接合構造体の製造システム |
US10522444B2 (en) | 2013-03-11 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface treatment method and apparatus for semiconductor packaging |
WO2015131185A1 (en) * | 2014-02-28 | 2015-09-03 | Intellipaper, Llc | Integrated circuitry and methods for manufacturing same |
DE102015112023B3 (de) * | 2015-07-23 | 2016-09-01 | Infineon Technologies Ag | Verfahren zum positionieren eines halbleiterchips auf einem träger und verfahren zum stoffschlüssigen verbinden eines halbleiterchips mit einem träger |
US10249515B2 (en) * | 2016-04-01 | 2019-04-02 | Intel Corporation | Electronic device package |
EP3471135A4 (en) * | 2016-06-08 | 2019-05-01 | Fuji Corporation | CIRCUIT FORMING METHOD |
CN108427520A (zh) * | 2018-04-02 | 2018-08-21 | 业成科技(成都)有限公司 | 触控面板与其制造方法 |
CN113571430A (zh) * | 2020-04-28 | 2021-10-29 | 西部数据技术公司 | 具有减小的底部填充面积的倒装芯片封装体 |
Family Cites Families (77)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5650546A (en) * | 1979-09-29 | 1981-05-07 | Sharp Corp | Semiconductor device |
JPS61156239A (ja) | 1984-12-28 | 1986-07-15 | Canon Inc | 閃光撮影装置 |
JPS61156239U (zh) * | 1985-03-19 | 1986-09-27 | ||
JPS62190342U (zh) * | 1986-05-26 | 1987-12-03 | ||
US4749120A (en) * | 1986-12-18 | 1988-06-07 | Matsushita Electric Industrial Co., Ltd. | Method of connecting a semiconductor device to a wiring board |
US4811081A (en) * | 1987-03-23 | 1989-03-07 | Motorola, Inc. | Semiconductor die bonding with conductive adhesive |
JPH01129431A (ja) * | 1987-11-16 | 1989-05-22 | Sharp Corp | 半導体チップ実装方式 |
JPH0715087B2 (ja) | 1988-07-21 | 1995-02-22 | リンテック株式会社 | 粘接着テープおよびその使用方法 |
JP2780293B2 (ja) | 1988-12-19 | 1998-07-30 | 松下電器産業株式会社 | 半導体装置 |
US5115545A (en) * | 1989-03-28 | 1992-05-26 | Matsushita Electric Industrial Co., Ltd. | Apparatus for connecting semiconductor devices to wiring boards |
JPH0521655A (ja) * | 1990-11-28 | 1993-01-29 | Mitsubishi Electric Corp | 半導体装置および半導体装置用パツケージ |
US5128746A (en) * | 1990-09-27 | 1992-07-07 | Motorola, Inc. | Adhesive and encapsulant material with fluxing properties |
US5136365A (en) * | 1990-09-27 | 1992-08-04 | Motorola, Inc. | Anisotropic conductive adhesive and encapsulant material |
JPH04292803A (ja) * | 1991-03-20 | 1992-10-16 | Hitachi Ltd | 異方導電性フィルム |
JP2722857B2 (ja) | 1991-04-30 | 1998-03-09 | 日本ビクター株式会社 | レンズ板の製作方法 |
JP2702839B2 (ja) * | 1991-11-20 | 1998-01-26 | シャープ株式会社 | 配線基板の電極構造 |
JP3050345B2 (ja) | 1992-06-29 | 2000-06-12 | 東京応化工業株式会社 | 集積回路素子の接続方法 |
US5318651A (en) * | 1991-11-27 | 1994-06-07 | Nec Corporation | Method of bonding circuit boards |
JP2678958B2 (ja) * | 1992-03-02 | 1997-11-19 | カシオ計算機株式会社 | フィルム配線基板およびその製造方法 |
US5532101A (en) * | 1992-06-15 | 1996-07-02 | Canon Kabushiki Kaisha | Image forming method |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
WO1994018701A1 (en) * | 1993-02-05 | 1994-08-18 | W.L. Gore & Associates, Inc. | Stress-resistant semiconductor chip-circuit board interconnect |
JPH0749413A (ja) | 1993-08-05 | 1995-02-21 | Toray Ind Inc | カラーフィルタの製造方法 |
KR0171438B1 (ko) * | 1993-09-29 | 1999-10-15 | 모리시따 요오이찌 | 반도체 장치를 회로 기판상에 장착하는 방법 및 반도체 장치가 장착된 회로 기판 |
JPH07225391A (ja) | 1994-02-14 | 1995-08-22 | Toshiba Corp | 液晶表示モジュール |
JPH07312377A (ja) | 1994-05-19 | 1995-11-28 | Fujitsu Ltd | 半導体チップの実装方法と実装装置 |
US5677246A (en) * | 1994-11-29 | 1997-10-14 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
US5864178A (en) * | 1995-01-12 | 1999-01-26 | Kabushiki Kaisha Toshiba | Semiconductor device with improved encapsulating resin |
KR0181615B1 (ko) * | 1995-01-30 | 1999-04-15 | 모리시다 요이치 | 반도체 장치의 실장체, 그 실장방법 및 실장용 밀봉재 |
DE69618458T2 (de) * | 1995-05-22 | 2002-11-07 | Hitachi Chemical Co., Ltd. | Halbleiterteil mit einem zu einem verdrahtungsträger elektrisch verbundenem chip |
ID19377A (id) | 1995-06-12 | 1998-07-09 | Matsushita Electric Ind Co Ltd | Paket unit semikonduktor, metode pemaketan unit semikonduktor, dan bahan pengkapsul untuk penggunaan dalam pemaketan unit semikonduktor (pecahan dari p-961658) |
US5578527A (en) | 1995-06-23 | 1996-11-26 | Industrial Technology Research Institute | Connection construction and method of manufacturing the same |
US5627405A (en) * | 1995-07-17 | 1997-05-06 | National Semiconductor Corporation | Integrated circuit assembly incorporating an anisotropic elecctrically conductive layer |
JP3435925B2 (ja) * | 1995-08-25 | 2003-08-11 | ソニー株式会社 | 半導体装置 |
JP2970491B2 (ja) * | 1995-09-20 | 1999-11-02 | ソニー株式会社 | 半導体パッケージ及びその製造方法 |
JP3544990B2 (ja) * | 1995-10-31 | 2004-07-21 | イビデン株式会社 | 電子部品モジュール及びその製造方法 |
JPH09219579A (ja) | 1996-02-13 | 1997-08-19 | Oki Electric Ind Co Ltd | 電子部品の接続方法及び接続装置 |
JP2806348B2 (ja) * | 1996-03-08 | 1998-09-30 | 日本電気株式会社 | 半導体素子の実装構造及びその製造方法 |
JP2828021B2 (ja) * | 1996-04-22 | 1998-11-25 | 日本電気株式会社 | ベアチップ実装構造及び製造方法 |
EP0807980B1 (en) | 1996-05-17 | 2006-06-21 | Canon Kabushiki Kaisha | Photovoltaic device and process for the production thereof |
JP2891184B2 (ja) * | 1996-06-13 | 1999-05-17 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH104126A (ja) * | 1996-06-14 | 1998-01-06 | Sony Corp | 実装基板、電子部品実装方法及び半導体装置 |
JPH104122A (ja) * | 1996-06-14 | 1998-01-06 | Hitachi Ltd | 半導体装置 |
JP3261981B2 (ja) * | 1996-06-17 | 2002-03-04 | 松下電器産業株式会社 | バンプ付きワークのボンディング方法およびボンディング構造 |
JPH1041615A (ja) * | 1996-07-19 | 1998-02-13 | Matsushita Electric Ind Co Ltd | 半導体チップ実装用基板、及び半導体チップの実装方法 |
JPH1084014A (ja) * | 1996-07-19 | 1998-03-31 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH1041694A (ja) * | 1996-07-25 | 1998-02-13 | Sharp Corp | 半導体素子の基板実装構造及びその実装方法 |
JP3928753B2 (ja) | 1996-08-06 | 2007-06-13 | 日立化成工業株式会社 | マルチチップ実装法、および接着剤付チップの製造方法 |
US6020047A (en) | 1996-09-04 | 2000-02-01 | Kimberly-Clark Worldwide, Inc. | Polymer films having a printed self-assembling monolayer |
JPH1098076A (ja) * | 1996-09-24 | 1998-04-14 | Oki Electric Ind Co Ltd | 半導体素子の実装方法 |
JPH10116855A (ja) | 1996-10-09 | 1998-05-06 | Oki Electric Ind Co Ltd | 半導体部品の実装装置および実装方法 |
JPH10125725A (ja) | 1996-10-18 | 1998-05-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2800806B2 (ja) * | 1996-10-31 | 1998-09-21 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH10168411A (ja) | 1996-12-06 | 1998-06-23 | Seiko Epson Corp | 異方性導電接着剤、液晶表示装置及び電子機器 |
JPH10173003A (ja) * | 1996-12-13 | 1998-06-26 | Sharp Corp | 半導体装置とその製造方法およびフィルムキャリアテープとその製造方法 |
US5814401A (en) * | 1997-02-04 | 1998-09-29 | Motorola, Inc. | Selectively filled adhesive film containing a fluxing agent |
AUPO515297A0 (en) | 1997-02-19 | 1997-04-11 | Future Fibre Technologies Pty Ltd | A method of providing in-situ chirped gratings in waveguides and waveguides made by that method |
TW442693B (en) * | 1997-02-24 | 2001-06-23 | Seiko Epson Corp | Color filter and its manufacturing method |
JPH10270496A (ja) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法 |
US5783465A (en) * | 1997-04-03 | 1998-07-21 | Lucent Technologies Inc. | Compliant bump technology |
US6077382A (en) * | 1997-05-09 | 2000-06-20 | Citizen Watch Co., Ltd | Mounting method of semiconductor chip |
US6175345B1 (en) | 1997-06-02 | 2001-01-16 | Canon Kabushiki Kaisha | Electroluminescence device, electroluminescence apparatus, and production methods thereof |
US6281450B1 (en) * | 1997-06-26 | 2001-08-28 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
US6407461B1 (en) * | 1997-06-27 | 2002-06-18 | International Business Machines Corporation | Injection molded integrated circuit chip assembly |
JPH1167795A (ja) * | 1997-08-08 | 1999-03-09 | Nec Corp | 半導体チップ搭載装置及び半導体チップ搭載方法並びに半導体装置 |
JPH1167979A (ja) * | 1997-08-13 | 1999-03-09 | Citizen Watch Co Ltd | フリップチップ半導体パッケージの実装構造及びその製造方法 |
US6353182B1 (en) * | 1997-08-18 | 2002-03-05 | International Business Machines Corporation | Proper choice of the encapsulant volumetric CTE for different PGBA substrates |
US6049124A (en) * | 1997-12-10 | 2000-04-11 | Intel Corporation | Semiconductor package |
US6157085A (en) * | 1998-04-07 | 2000-12-05 | Citizen Watch Co., Ltd. | Semiconductor device for preventing exfoliation from occurring between a semiconductor chip and a resin substrate |
KR100352865B1 (ko) * | 1998-04-07 | 2002-09-16 | 신꼬오덴기 고교 가부시키가이샤 | 반도체 장치 및 그 제조방법 |
JP2000012609A (ja) * | 1998-06-17 | 2000-01-14 | Shinko Electric Ind Co Ltd | 回路基板への半導体チップの実装方法 |
JP2000022329A (ja) | 1998-06-29 | 2000-01-21 | Toshiba Corp | 配線基板および電子ユニットおよび電子部品実装方法 |
JP3951462B2 (ja) | 1998-06-30 | 2007-08-01 | カシオ計算機株式会社 | 電子部品実装体及びその製造方法 |
JP3278055B2 (ja) * | 1998-06-30 | 2002-04-30 | セイコーインスツルメンツ株式会社 | 電子回路装置 |
KR100629923B1 (ko) | 1998-09-30 | 2006-09-29 | 돗빤호무즈가부시기가이샤 | 도전성페이스트와 도전성페이스트의 경화방법, 및 도전성페이스트를 이용한 비접촉형 데이터송수신체용 안테나의 형성방법과, 비접촉형 데이터송수신체 |
US6040631A (en) * | 1999-01-27 | 2000-03-21 | International Business Machines Corporation | Method of improved cavity BGA circuit package |
US6225704B1 (en) * | 1999-02-12 | 2001-05-01 | Shin-Etsu Chemical Co., Ltd. | Flip-chip type semiconductor device |
-
1999
- 1999-06-25 CN CNB998010650A patent/CN1143373C/zh not_active Expired - Fee Related
- 1999-06-25 SG SG200200598A patent/SG102032A1/en unknown
- 1999-06-25 CN CNB998014397A patent/CN1143375C/zh not_active Expired - Fee Related
- 1999-06-25 WO PCT/JP1999/003417 patent/WO2000002243A1/ja active IP Right Grant
- 1999-06-25 JP JP2000558550A patent/JP4448617B2/ja not_active Expired - Fee Related
- 1999-06-25 KR KR10-2000-7002052A patent/KR100510387B1/ko not_active IP Right Cessation
- 1999-06-25 KR KR10-2000-7001923A patent/KR100509874B1/ko not_active IP Right Cessation
- 1999-06-25 US US09/486,317 patent/US6462284B1/en not_active Expired - Lifetime
- 1999-06-25 CN CNB998010669A patent/CN1143374C/zh not_active Expired - Fee Related
- 1999-06-25 WO PCT/JP1999/003420 patent/WO2000002245A1/ja active IP Right Grant
- 1999-06-25 JP JP2000558551A patent/JP3702788B2/ja not_active Expired - Fee Related
- 1999-06-25 KR KR10-2000-7002056A patent/KR100514559B1/ko not_active IP Right Cessation
- 1999-06-25 US US09/486,561 patent/US6995476B2/en not_active Expired - Fee Related
- 1999-06-25 JP JP2000558549A patent/JP3692935B2/ja not_active Expired - Fee Related
- 1999-06-25 WO PCT/JP1999/003418 patent/WO2000002244A1/ja active IP Right Grant
- 1999-06-29 TW TW088111021A patent/TW454278B/zh not_active IP Right Cessation
- 1999-06-29 TW TW088111010A patent/TW452896B/zh not_active IP Right Cessation
- 1999-06-30 TW TW088111123A patent/TW414985B/zh not_active IP Right Cessation
-
2001
- 2001-05-07 HK HK01103203A patent/HK1032671A1/xx not_active IP Right Cessation
- 2001-05-11 HK HK01103293A patent/HK1032672A1/xx not_active IP Right Cessation
- 2001-05-28 HK HK01103675A patent/HK1033201A1/xx not_active IP Right Cessation
-
2002
- 2002-07-09 US US10/190,580 patent/US6763994B2/en not_active Expired - Lifetime
- 2002-07-09 US US10/190,515 patent/US6972381B2/en not_active Expired - Fee Related
-
2004
- 2004-07-20 US US10/893,993 patent/US20040256739A1/en not_active Abandoned
-
2005
- 2005-11-15 US US11/272,698 patent/US7198984B2/en not_active Expired - Fee Related
-
2006
- 2006-03-29 US US11/391,559 patent/US7332371B2/en not_active Expired - Fee Related
-
2007
- 2007-02-15 US US11/675,561 patent/US7560819B2/en not_active Expired - Fee Related
- 2007-12-21 US US12/003,367 patent/US7868466B2/en not_active Expired - Fee Related
Also Published As
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1143375C (zh) | 半导体装置及其制造方法、电路基板和电子装置 | |
CN1154178C (zh) | 半导体装置及其制造方法、电路基板和电子装置 | |
CN1076872C (zh) | 载片及其制造方法和安装方法 | |
CN1291467C (zh) | 电子器件的制造方法 | |
CN1098617C (zh) | 电路基板上安装带粘接剂的电子元器件的方法 | |
CN1251560C (zh) | 零件内藏模块及其制造方法 | |
CN1110078C (zh) | 半导体元件的安装方法 | |
CN1290389C (zh) | 有内构电子元件的电路板及其制造方法 | |
CN1185698C (zh) | 半导体装置及其制造方法、电路板以及电子设备 | |
CN1591861A (zh) | 电路元件内置模块及其制造方法 | |
CN1767177A (zh) | 半导体器件以及电子设备 | |
CN1529544A (zh) | 倒装芯片连接用电路板及其制造方法 | |
CN1510745A (zh) | 半导体器件及其制造方法 | |
CN1956183A (zh) | 电子部件内置式基板及其制造方法 | |
CN1790651A (zh) | 芯片集成基板的制造方法 | |
CN1823409A (zh) | 电气部件的安装方法和安装装置 | |
CN1463040A (zh) | 具有从密封树脂暴露出来的散热器的半导体器件 | |
CN1805657A (zh) | 配线电路基板 | |
CN1319636A (zh) | 电极连接用粘结剂及使用该粘结剂的连接方法 | |
CN1838859A (zh) | 柔性印刷线路板及其制造方法、和半导体装置 | |
CN1826688A (zh) | 半导体器件的制造方法 | |
CN1220774A (zh) | 半导体装置、薄膜载带及其制造方法 | |
CN1424756A (zh) | 金属布线基板和半导体装置及其制造方法 | |
CN1254856C (zh) | 电路装置的制造方法 | |
CN1294652C (zh) | 半导体器件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040324 Termination date: 20170625 |
|
CF01 | Termination of patent right due to non-payment of annual fee |