CN1196264C - 时钟与数据恢复电路 - Google Patents
时钟与数据恢复电路 Download PDFInfo
- Publication number
- CN1196264C CN1196264C CNB011447303A CN01144730A CN1196264C CN 1196264 C CN1196264 C CN 1196264C CN B011447303 A CNB011447303 A CN B011447303A CN 01144730 A CN01144730 A CN 01144730A CN 1196264 C CN1196264 C CN 1196264C
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- circuit
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- 230000010363 phase shift Effects 0.000 abstract description 20
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Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Abstract
Description
Claims (2)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP389526/2000 | 2000-12-21 | ||
JP2000389526A JP3636657B2 (ja) | 2000-12-21 | 2000-12-21 | クロックアンドデータリカバリ回路とそのクロック制御方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100686385A Division CN1303758C (zh) | 2000-12-21 | 2001-12-21 | 时钟与数据恢复电路及其时钟控制方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1360396A CN1360396A (zh) | 2002-07-24 |
CN1196264C true CN1196264C (zh) | 2005-04-06 |
Family
ID=18856054
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100686385A Expired - Fee Related CN1303758C (zh) | 2000-12-21 | 2001-12-21 | 时钟与数据恢复电路及其时钟控制方法 |
CNB011447303A Expired - Fee Related CN1196264C (zh) | 2000-12-21 | 2001-12-21 | 时钟与数据恢复电路 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100686385A Expired - Fee Related CN1303758C (zh) | 2000-12-21 | 2001-12-21 | 时钟与数据恢复电路及其时钟控制方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7187727B2 (zh) |
JP (1) | JP3636657B2 (zh) |
KR (1) | KR100401321B1 (zh) |
CN (2) | CN1303758C (zh) |
DE (1) | DE10161054B4 (zh) |
TW (1) | TWI289976B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101657966B (zh) * | 2007-03-20 | 2012-05-30 | 株式会社爱德万测试 | 时钟数据恢复电路、方法及测试装置 |
Families Citing this family (114)
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JP2003304225A (ja) * | 2002-04-09 | 2003-10-24 | Mitsubishi Electric Corp | データリカバリ回路 |
US20030210758A1 (en) * | 2002-04-30 | 2003-11-13 | Realtek Semiconductor Corp. | Recovered clock generator with high phase resolution and recovered clock generating method |
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KR100448707B1 (ko) * | 2002-08-20 | 2004-09-13 | 삼성전자주식회사 | 클럭 및 데이터 복원 회로 및 방법 |
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2000
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- 2001-11-26 TW TW090129176A patent/TWI289976B/zh not_active IP Right Cessation
- 2001-12-12 DE DE10161054A patent/DE10161054B4/de not_active Expired - Fee Related
- 2001-12-17 US US10/022,551 patent/US7187727B2/en not_active Expired - Fee Related
- 2001-12-20 KR KR10-2001-0081723A patent/KR100401321B1/ko not_active IP Right Cessation
- 2001-12-21 CN CNB2004100686385A patent/CN1303758C/zh not_active Expired - Fee Related
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CN101657966B (zh) * | 2007-03-20 | 2012-05-30 | 株式会社爱德万测试 | 时钟数据恢复电路、方法及测试装置 |
Also Published As
Publication number | Publication date |
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KR100401321B1 (ko) | 2003-10-10 |
US7187727B2 (en) | 2007-03-06 |
DE10161054A1 (de) | 2002-09-26 |
TWI289976B (en) | 2007-11-11 |
US20020079938A1 (en) | 2002-06-27 |
DE10161054B4 (de) | 2004-04-08 |
CN1360396A (zh) | 2002-07-24 |
KR20020050730A (ko) | 2002-06-27 |
CN1303758C (zh) | 2007-03-07 |
JP2002190724A (ja) | 2002-07-05 |
CN1592105A (zh) | 2005-03-09 |
JP3636657B2 (ja) | 2005-04-06 |
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