CN1185715C - 一种集成电路及其制造方法 - Google Patents

一种集成电路及其制造方法 Download PDF

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CN1185715C
CN1185715C CNB998164623A CN99816462A CN1185715C CN 1185715 C CN1185715 C CN 1185715C CN B998164623 A CNB998164623 A CN B998164623A CN 99816462 A CN99816462 A CN 99816462A CN 1185715 C CN1185715 C CN 1185715C
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CN1338119A (zh
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小R·J·扎夫里尔
D·C·鲍曼
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Atmel Corp
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Abstract

在一种IC封装方案中，一种多层基片(114)由导电互连层(120，122，124)组成，被环氧树脂或陶瓷绝缘层分隔开并被通路连接。无源元件(102，104，106)可以通过应用于基片的材料技术来加强有源电路芯片的电气性能，达到最大程度。封装的材料选择可对给定的电路设计创造最佳无源集成。典型的应用包括电源旁路电容器、射频调谐和抗阻匹配。封装基片中无源元件的引入创造出新颖的电气可裁IC封装方法，能对任意给定芯片设计获得比原有方法更佳的性能。

Description

一种集成电路及其制造方法
技术领域
本发明主要涉及半导体器件的封装，特别是针对于在这样的封装中制造高Q电抗元件。
背景技术
本发明涉及到高Q无源元件的结构，这些元件通常指例如在射频设备中所使用的元件。这些元件在半导体芯片中引入的困难性是众所周知的：集总和分散电抗部分的品质因素(Q)主要取决于金属的电阻、介质耗损以及寄生电抗。集总元件的电感和电容的真实值大大受限于半导体芯片可以利用的面积。类似的，分布传输线谐振器很难按期望频率配置在半导体芯片上的原因也在于受空间的限制。常用的惯例是将集总电抗放置在PC板上。然而，传统封装技术所带来的寄生电抗常常严重降低功能电路的性能。例如，在功率放大器设备中，封装导线的寄生电抗常常接近或超出有源半导体器件的输出阻抗。在很多情况下，封装电抗排除了用硅或硅-锗工艺制造可以接受的功率放大器的可能性。类似地，在小信号设备中也存在着相同的问题。
集成电路通常安装在塑料或陶瓷封装内，该封装将半导体芯片与随后焊接在PCB上的导线或焊球相连接。有些封装类型包含了多种金属层，例如，倒装-球栅阵列，以便确定I/O焊片的线路，并且利用焊片来和封装外部接触。
图11例举了一种典型的球栅封装。半导体芯片1102放置在基片1112上，并由未填满的环氧树脂化合物1106固定。基片包括一组金属互连层，在芯片的焊球(或“块”)1104和基片的焊球1114之间提供一条电通路。模制环氧树脂1110被用来包裹在芯片外面，从而构成球栅封装。图12是基片1112一部分的放大视图，该基片在图11中已说明。可以看见基片由叠层结构的金属交互层1212组成。这些金属层通过绝缘材料层1210，例如环氧树脂或陶瓷而彼此绝缘。这些金属层在半导体芯片1102上的键合片或“块”之间提供了互连。这些金属层由互连(未图示)和通路1202组成图案，通路1202提供金属层之间的互连性。
我们所需要的是一种能够在IC器件中不必使用分立元件就能提供高Q元件的方案。希望将这样的器件与IC器件自身结合在一起，从而能节省PCB上的空间，同时获得使用高Q元件的好处。
发明内容
根据本发明，一种半导体器件，包括：至少一块在其上构成电路的半导体芯片；和叠层基片，具有将所述芯片放置其上的表面，所述基片具有单层或多层金属层和单层或多层绝缘层，所述金属层和绝缘层彼此交错放置，所述芯片和一些所述的金属层电耦合，所述金属层包括多个互连以及多个将所述互连与其他互连以及所述半导体芯片相电耦合的通路；和一种无源元件，完全从所述基片内部的互连中构造出来，并且与所述半导体芯片电耦合。
根据本发明的另一方面，一种集成电路，包括：其中装有第一电路的半导体芯片；上面放置着所述芯片的基片，所述基片包括交替的金属互连层和绝缘材料层，所述芯片具有与单层或多层金属互连层的电连接；第二电路，包括单个或多个完全从所述基片内部的单层或多层金属互连层中构造出来的无源元件，所述第二电路与所述芯片的第一电路电通信；和放置在所述芯片和所述基片顶部的封装，因而对所述芯片提供一种保护包装；所述第二电路进一步包括外部电接触，而所述电接触和所述第二电路上的一些所述的金属互连电接触。
根据本发明的又一方面，一种制造集成电路的方法，包括以下步骤：(a)在一半导体芯片上制造电路，包括构成多个用于传送和接收信号和提供单个或多个电压电势的焊片；(b)以绝缘层形式制造绝缘材料的基片，包括在所述的基片中构成至少一层导电互连的金属层，并且在所述至少一层导电互连的金属层中构造出来至少一个无源元件；(c)将所述半导体芯片放置在所述基片上并且固定起来；(d)在所述半导体芯片和所述至少一层导电互连的金属层之间通过通路建立电连接；并且(e)在所述半导体芯片和所述至少一个无源元件之间建立电连接。
附图说明
图1是展示本发明的IC基片中互连的排列和无源元件的顶视图。
图2和图3是两种电容器元件的侧视图。
图4A和4B是一种螺旋电感器的顶视图和侧视图。
图5A-5C是一种螺旋电感器的顶视图、正视图和侧视图。
图6是一种谐振器的透视图。
图7A和7B是一种电阻器的顶视图和侧视图。
图8和9是IC基片中构成的两种典型电路的横截面视图。
图10是本发明处理步骤的流程图。
图11和12展示了一种典型的原有IC封装方案。
具体实施方式
图11展示了一种典型的球栅IC封装，包括芯片1102，它装配在基片1112上并被密封剂1110密封。转过来看图1，根据本发明较好模式配置的叠层基片114包括单层或多层互连金属层，每层都被一层绝缘材料分隔开。图1展示的最上互连层包括多条互连轨迹120和无源元件102-106。具体而言，元件102和104是电容器，而元件106是一个电感器。可以看见电感器106包括轨迹122和124。这层互连层被安置在基片114的上表面112上。
参照图2，图1中沿线2-2截取的电容器102的侧视图展示了基片114的一部分。在绝缘层202上部安置着一金属层200，该绝缘层按顺序也被放置在另一金属层204上。展示的电容器102由两块金属板220和222组成。每块板都形成在金属层200和204中被绝缘层202分隔开。绝缘层被当做电介质。典型的绝缘材料包括环氧树脂或可以是陶瓷材料。由于材料的选择取决于很多因素，例如期望的电气特性、期望的物理特性、制造成本以及其他因素，因此没有一种较好的材料。本发明的IC器件的特殊应用将决定使用的具体材料。
参照图3，图1中沿线3-3截取的电容器104的侧视图展示了基片114的附加金属和绝缘层306-312。电容器104是一种多层板极电容器。在这个实例中，电容器的结构横跨了四层互连金属层200、204、308和312。四层板极320、322、324和326各自在金属层200、204、308和312中构成。这些板极按照交迭方式垂直排列。绝缘层构成了电容器的电介质。通路330将板极320和324耦合在一起，另一通路332将板极322和326耦合在一起。层202、306和310的绝缘材料被当做电容器104的电介质材料。
必须注意的是，电容器102和104可以被耦合到芯片焊片(例如芯片902，图9)作为芯片电路的元件，或位于芯片焊片和一根IC封装的外部引脚(焊球)之间。这样的耦合可以在通过在下层金属层互连中期望提供连通性的情况下，使用通路来完成。还必须注意的是，电容器可以被安置在基片114内部的金属层上。例如，图2所示的板极电容器可以由图3中的金属层204和308组成。实际上，清楚地说，任意无源元件都可以被安置在基片任意金属层中。最终，电容器板极的连接可以使用许多方法中的任意一种完成。互连轨迹可以从板极发散出去来构图，并且通路被用来和其他金属层上的互连耦合在一起。这种特殊的连接结构依赖于无源元件如何耦合和与什么耦合。
转回首看图4A和4B，展示了一种安置在绝缘层414表面412上的螺旋电感器402的实例。螺旋的外部端点和互连轨迹420相连。螺旋的内部端点与在下层金属层上构成并通过通路424耦合在一起的轨迹422相耦合。虽然一种空中桥梁可以被用来提供与螺旋内部端点的连通性，但这样的结构通常很难制造，所以本实施例图4A和4B中所示的是较佳的方案。互连轨迹420和422如图所示可以在相对的金属层上，或者安置在同一螺旋金属层上，或者可以在其他一些金属层上，这取决于该元件是如何连接的。
参照图5A-5C，展示了一种螺旋电感器502的实例。该元件由放置在第一金属层上并且沿一对角线相互并行排列的第一组金属段550、552和554组成。第二组金属段540、542、544和546放置在第二金属层上，并且沿与第一金属段相对的对角线方向相互平行排列。一组通路522-532以端对端的方式连接第一段和第二段。结果从上面看下去就如图5A所示成为锯齿状配置，虽然螺旋结构的外规是一种正方的螺旋结构。末段540和546通过通路520和534与互连轨迹506和504耦合在一起。或者，轨迹506和504可以在末段540和546同一金属层上构成，这样可以消除对通路的需求。这样的具体结构取决于在哪里完成和无源元件的连接。
转到图6，一种传输线谐振器602的透视图展示了放置在第一金属层610中的第一板极620和放置在第二金属层614中的第二板极624。金属层被绝缘材料622分隔开。夹在两板极间的是一金属片626，放置在第三金属层612中。板极的宽度W2比金属片的宽度W1宽。另外，谐振器能只用两块板极620和624中的一块构成。
作为根据本发明制造的无源元件的最后一个实例，图7A和7B展示了一种放置在绝缘层714的表面712上的金属层上的电阻器702。从先前的实例可见，其他无源元件可以按上述同样的方法配入IC封装叠层基片中。本发明的一种优点在于封装基片的互连层通常和半导体芯片中的基片密集程度不同。因此，这使得构建低值电阻器成为可能，因为有更多的空间蚀刻较宽的轨迹，并且封装金属互连比在芯片上的金属轨迹厚。同样，使用本发明可以减小电感器和电容器金属的电阻，并且使得制造高Q器件成为可能。
现在，将把话题转移到可能配在IC封装基片中的典型电路。图8展示了一种作为振荡器，例如VOC(电压控制振荡器)的谐振器的振荡回路800，包括一个电感器802和电容器804的并行组合。该振荡回路通常经端子810与812和半导体芯片上的电路耦合，构成振荡器电路。
图8的横截面视图展示了一种安置在叠层基片822上的半导体芯片820。芯片的焊球828和顶层基片822上的互连840-810耦合在一起。通路850-854提供了一条到下层金属层824和826的电通路。定义电容器804的板极860和862分别放置在金属层824和826上。电感器802被放置在金属层824中的螺旋结构870所限定，更详细的细节已经在图4A和4B中给出。通路850将电容器804的一块板极和互连轨迹840耦合在一起，而通路852将螺旋结构870的外部端点872和轨迹840相连。可以看见，轨迹840相当于电路端子810。
接着，横截面视图还进一步展示了工作于电容器板极862到接至上述金属层螺旋结构870内部端点874的通路858之间的互连轨迹880。通路854将轨迹880和焊片842相耦合。轨迹880因而相当于电路端子812。完成了图8的讨论，可以了解芯片820通过焊片844、通路856和焊片846与外部可到达的焊球830直接相连，说明了半导体芯片如何接收和发送外部信号。
转到图9看另一个电路实例。所展示的电路是一个低通滤波器900，包括电阻器902和电容器904。端子914和916接收外部信号，而端子910和912与半导体芯片上的电路相连。横截面视图展示了安置在叠层基片922上的半导体芯片920。放置在金属层924上的是电阻器970。电阻器的横截面视图是从图7A中的视图线970-970中截取的。电阻器970的一端点和依次与电容器904中一板极960相连的轨迹980耦合，电容器的另一板极962放置在金属层926上。
通路952沿基片922的绝缘材料延伸，并且与和半导体芯片焊球928相连的焊片940接触。可以了解垫片940相当于电路端子910。轨迹982与电容器904的板极962相连。通路954和956分别与焊片942和946相连。可以了解，焊片942和946分别相当于端子914和916。最终，通路950提供了一条从焊片944(相当于端子914)到电阻器970另一端的电通路。
这些示范电路说明了多种根据本发明实现的无源电路。之前所揭示的这种无源结构有几个重要的优点。如果适合地构造在半导体芯片上，电抗值(C或L)和用这样的方法制造的谐振器的谐振频率可以被设计为大大超出通常可获得的值。IC封装的基片通常具有比芯片本身更大的面积，因此，允许更大的物理尺寸和相应更大的电容器和电感器值。在电容器情况下，多层金属层的出现使得制造多板极电容器成为可能。电容器、电感器和谐振器的Q值能被做得更高，因为陶瓷或环氧树脂的特性比得上半导体材料且有更大的金属导体。没有额外的金属被消耗，因为无源结构是从同样的互连金属层中构图的，唯一的不同在于更少的金属被蚀刻掉。因为封装中的金属是“自由”的，所以这种器件的成本也很低。按所揭示的方法在封装基片中配入无源元件创造出一种可以使任意给定芯片设计的性能比原有方法更好的电气可裁IC封装。
另外的典型电路包括(但不受限于)电源旁路电容器，其特征在于，从半导体基片到旁路电容器的多根旁路导线允许在基片中使用高电阻率材料，导致芯片上的基片更高的绝缘性。两个或更多的电感器可以被配置在被绝缘层隔离的邻近金属层上以提供相互耦合而构成一个变压器。谐振器可以通过使用短传输线(当使用高电介质的绝缘材料，例如陶瓷时，特别有用)来构建。这种类型的谐振器可以被用于带通滤波器、带阻滤波器、VCO或自由振荡振荡器的谐振器，和射频功能调谐。在多芯片模块(MCM)应用中，耦合电路可以将装在基片上的多个半导体芯片耦合在一起。
转到图10来讨论一下将无源元件配到IC封装基片中去的处理方法。可以了解，相同的步骤被用来制造无源元件来构成多互连层。第一步，绝缘材料层构成，步骤1010。在这一步中，通路可能穿过绝缘层而构成，并且被填充，来获得通向绝缘层外部表面的导电路径，以便在半导体芯片上构成电连接。接着，导电材料(典型使用的如铜、金、钨和相关合金)沉积在绝缘层中，步骤1012。绘制一个或更多的图案来定义金属层互连，步骤1014。同时，绘制附加的图案来定义放置在金属层中的无源元件的结构。图案接着被蚀刻，并且进行光刻胶处理来除去不想要的金属，留下需要的图案。在步骤1016中，下一绝缘层在顶层的金属层上构成。为了提供下层金属层连通性，必须在绝缘层中钻出通路并填充金属，步骤1018。在步骤1020，如果需要附加层，那么重复上述步骤，直到制造出一个叠层基片。最终步骤包括在基片上放置和固定半导体芯片，并且在BGA情况下，将焊球附加在芯片的多层基片封装上。前述处理步骤在IC封装技术领域众所周知。任何一种技术都能实现本发明。任意给定技术的选择取决于某些因素，例如材料的使用、期望的操作条件、封装要求、生产成本等等。

Claims (25)

1、一种半导体器件，其特征在于，包括：
至少一块在其上构成电路的半导体芯片；和
叠层基片，具有将所述芯片放置其上的表面，所述基片具有单层或多层金属层和单层或多层绝缘层，所述金属层和绝缘层彼此交错放置，所述芯片和一些所述的金属层电耦合，所述金属层包括多个互连以及多个将所述互连与其他互连以及所述半导体芯片相电耦合的通路；和
一种无源元件，完全从所述基片内部的互连中构造出来，并且与所述半导体芯片电耦合。
2、如权利要求1所述的半导体器件，其特征在于，所述单层或多层的绝缘层是环氧树脂材料。
3、如权利要求1所述的半导体器件，其特征在于，所述单层或多层的绝缘层是陶瓷材料。
4、如权利要求1所述的半导体器件，其特征在于，所述无源元件是电容器，所述电容器具有第一板极，它放置在所述多层金属层中的第一层，以及第二板极，它放置在所述多层金属层中的第二层，所述第一和第二板极被所述单层或多层绝缘层中的一层分隔开。
5、如权利要求1所述的半导体器件，其特征在于，所述无源元件是电容器，所述电容器包括多块板极，每一所述板极放置在所述多层金属层中分隔开的某一层中，所述板极以交迭方式垂直排列，所述板极的奇数层通过通路相互电耦合，所述板极的偶数层也通过通路相互电耦合。
6、如权利要求1所述的半导体器件，其特征在于，所述无源器件是电感器，所述电感器是一放置在所述单层或多层金属层中某一层中的金属螺旋结构。
7、如权利要求1所述的半导体器件，其特征在于，所述无源元件是电感器；所述电感器包括第一组段，它放置在所述多层金属层中的第一层，以及第二组段，它放置在所述多层金属层中的第二层；所述多层金属层中的第一层和第二层被所述单层或多层绝缘层中的一层分隔开；所述电感器进一步包括多条将所述第一段和第二段电耦合的被金属填充的通路。
8、如权利要求1所述的半导体器件，其特征在于，所述无源元件是谐振器；所述谐振器具有放置在所述多层金属层的第一层中的第一板极和放置在所述多层金属层的第二层中的金属片；所述第一板极具有比所述金属片尺寸更加宽的尺寸。
9、如权利要求8所述的半导体器件，其特征在于，所述谐振器包括放置在所述多层金属层的第三层中的第二板极。
10、如权利要求1所述的半导体器件，其特征在于，所述无源元件是电阻器，所述电阻器放置在所述单层或多层金属层中的某层中。
11、一种集成电路，其特征在于，包括：
其中装有第一电路的半导体芯片；
上面放置着所述芯片的基片，所述基片包括交替的金属互连层和绝缘材料层，所述芯片具有与单层或多层金属互连层的电连接；
第二电路，包括单个或多个完全从所述基片内部的单层或多层金属互连层中构造出来的无源元件，所述第二电路与所述芯片的第一电路电通信；和
放置在所述芯片和所述基片顶部的封装，因而对所述芯片提供一种保护包装；
所述第二电路进一步包括外部电接触，而所述电接触和所述第二电路上的一些所述的金属互连电接触。
12、如权利要求11所述的集成电路，其特征在于，所述集成电路进一步包括第二半导体芯片。
13、如权利要求11所述的集成电路，其特征在于，所述绝缘材料层是环氧树脂。
14、如权利要求11所述的集成电路，其特征在于，所述绝缘材料层是陶瓷材料。
15、如权利要求11所述的集成电路，其特征在于，所述的第二电路是一滤波电路，该滤波电路具有与两个所述外部电接触相耦合的第一对端子和与所述半导体芯片耦合的第二对端子。
16、如权利要求11所述的集成电路，其特征在于，所述的第二电路是包括一电感器和一电容器的振荡电路，所述振荡电路包括一对与所述半导体芯片耦合的端子。
17、如权利要求11所述的集成电路，其特征在于，所述外部电接触中的一个用来耦合电源，并且所述第二电路包括与所述外部电接触中的一个相耦合的电源旁路电容器。
18、如权利要求11所述的集成电路，其特征在于，所述单个或多个无源元件包括电感器、电容器、电阻器和变压器中的一个。
19、一种制造集成电路的方法，其特征在于，包括以下步骤：
(a)在一半导体芯片上制造电路，包括构成多个用于传送和接收信号和提供单个或多个电压电势的焊片；
(b)以绝缘层形式制造绝缘材料的基片，包括在所述的基片中构成至少一层导电互连的金属层，并且在所述至少一层导电互连的金属层中构造出来至少一个无源元件；
(c)将所述半导体芯片放置在所述基片上并且固定起来；
(d)在所述半导体芯片和所述至少一层导电互连的金属层之间通过通路建立电连接；并且
(e)在所述半导体芯片和所述至少一个无源元件之间建立电连接。
20、如权利要求19所述的方法，其特征在于，所述步骤(e)包括在所述元件和所述焊片之一之间构成一导电通路。
21、如权利要求19所述的方法，其特征在于，所述至少一个无源元件是电容器。
22、如权利要求19所述的方法，其特征在于，所述至少一个无源元件是电感器。
23、如权利要求19所述的方法，其特征在于，所述至少一个无源元件是谐振器。
24、如权利要求19所述的方法，其特征在于，所述至少一个无源元件是电阻器。
25、如权利要求19所述的方法，其特征在于，所述至少一个无源元件是变压器。
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US6218729B1 (en) 2001-04-17
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