TW475196B - Apparatus and method for an integrated circuit having high Q reactive components - Google Patents

Apparatus and method for an integrated circuit having high Q reactive components Download PDF

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Publication number
TW475196B
TW475196B TW088122622A TW88122622A TW475196B TW 475196 B TW475196 B TW 475196B TW 088122622 A TW088122622 A TW 088122622A TW 88122622 A TW88122622 A TW 88122622A TW 475196 B TW475196 B TW 475196B
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integrated circuit
patent application
item
substrate
scope
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TW088122622A
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Robert J Zavrel Jr
Dan C Baumann
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Atmel Corp
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
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    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
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    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
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    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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Description

475196 五、發明說明（1) 發明_^後農复邊 括關於半導體裝置封裝，尤指製 中之间g(。口質因子）反應型組件。 可展 背景技藝 明係關於構造一般例如使用於射頻應用之〜 =)被動裝置。$所周知地，此f裝置因叩貝 而難以合併入半導體晶粒中集 # 口素， 質因子（Q)，主要由金屬布反應型組件之品 决疋。在集總組件之實際電感及電 2所 體晶粒之可利用面鈐。π接 ' > 人為％限於半導 空間限制，而難以：構在半導：曰：：線：振器，也因為 :。通常作法為將集總電抗=;=:=希？頻 :支=關之寄生電抗常嚴重降低 ：：？，封裝 ，率放大11應用中’封裝引線之寄 例如， 半導體裝置之輸出阻抗。在很多情；中或超 在硬或石夕-錯過程構建可接受功率放大哭中封t衣電抗 '、讯諕應用如也可能有類相之爭論。 °。 σ忐性。
’其將半雙 有些封裝 ’以便將I Τ體電路-般予以安裝在塑膠： 以ϊ?=Γ焊接·之引線或球' /0塾片及公用墊片定路徑至封；：;;：：陣列 例如，圖η示-代表性球外部一觸點。， 予以安裴，藉由一底層填料j = 半導體晶粒丨丨〇 2 基片包括-組‘屬真；；„物11〇6固著基 連層’以在晶粒之焊接球（或 立、贫叨說明（2) :模起1^11-°1與基片之焊接球1114之間提供電路_。 ^壞亀旨⑴〇可用以包封晶粒，：-上 L 在圖llt所標記之基片⑴2之—部 ":# ，基片由數相間金屬層Ϊ 21 2之一聂声紝M ί。此4金屬層藉絕緣材料層mo，諸如所紐 竞’彼此絕緣。在半導體晶粒1102上之諸接=曰或陶 起之間，此等金屬層可提供互連。金口片凸 及通f202作成圖案，其在金屬層之間提s供互連 1未示） 所需要者為一種方案，供在IC裝置提。 必使用不連續之組件。宜於 、，且件，而不 以内，並因此在PCB節省*門，、、置/併在1C裝置本身 可能之優點。 h間’而同時獲得使用則組件所 登明之概Μ
根據本發明，一種改進之I 併至1C之封裝中。一Ic安获其/ f方案、，包括被動裝置合 至屬互連之璺層結構，用以提供 卫有 2及公用墊片，諸如電源及接地。被動穿置：：：二0墊 連層，其直接或藉由通道，二十又：為金屬互 半導體晶粒提供另外之電功能以對 件，係自封裝金屬層本體所製造口 ：：：=應f組 夫幺诂你儿士 u未厚之晶片上金屬，電阻可 大為減低。代表性應用包括但不限於 叮 波之濾波器電路、電源供應旁容：輸或：出訊號遽 譜振器等等。本發明也適用於將=多裝 五、發明說明（3) 粒之=谁^封衣之多晶片模組。被動裝置可用以# 寸立之間進仃之訊號。 夏」用Μ轉合在 一種製造本發明之美 、 之 層。每-金屬層予以作成^ :法並：括沈積絕緣層及金屬 驟。作成圖案包括界定成:，二' 至一光阻劑麵刻步 結構與互連同時作 ’艮跡。構成被動裝置 f互連之同-金屬層作成圖案，故不耗：^、、、“冓，係自 有之差異為蝕刻掉較少金屬。 之金屬；僅 圖11示代表性球柵Ic封裝，包含安裝至 包封劑1110所封閉之晶粒11〇2。 1片112、並被 ，，彼此被-層、絕緣材料所分開。圖示—最上層互=， 已δ複數個互連痕跡J 2 〇及被動組件J 〇 2 — J 〇 6。: 、:件102及1〇4為電容器’及組件1〇6為電感器。可寺看出疋電 感器1〇6包括痕跡122及124。此層之互連予以配 114之頂面112。 I &片 請參照圖2,圖1之電容器1〇2沿視線2 — 2所取之侧視圖， 顯不基片11 4之一部份。有一金屬層2 〇 〇配置在絕緣層2 〇 2 之頂上，其復予以配置在另一金屬層2〇4之頂上。電容器 102顯示由二金屬板220及222所組成。每一板形成在一單 獨之金屬層20 0及204，並被絕緣層2 0 2所分開。絕緣層因 此作用如一種電介質。代表性絕緣材料包括一種環氧樹脂 ，或可為一種陶瓷材料。並無一種較佳材料，因為選擇將 88122622.ptd 第7頁 475196 五、發明說明（4) 依所希望之電特徵、所希望之物理特徵、製造成本等等因 素而定。本發明之1C裝置，其特定應用將會限定所使用之 特定材料。 請參照圖3，圖1之電容器1〇2沿視線3 —3所取之侧視圖， 顯示基片114之另外金屬及絕緣層3〇6_31 2。電容器1〇4為 多層板電容裔。在此實例中，電容器之結構跨越四金屬 互連層20 0,204,3 08及312。四板32 0,322,324及32 6分別形 成在金屬-層200, 204, 308及312中。板以重疊方式垂直對 準。絕緣層形成電容器之電介質。一通道330將板32〇及 324耦合在一起，同時另一通道33 2將板322及3 2 6耦合在一 起。層2 0 2, 3 0 6及310之絕緣材料用作電容器1〇4之 材料。 貝 請察知，電容器1〇2及104可輕合至晶粒之 圖9)，作為在晶粒之電路中、或⑽^ 電二互了連予的情況，此等連讀^ 彳丨ί ο二配置在基片114之内金屬層内 204及308中。”上，將合電:白二可形成於圖3之金屬層 在基片之任何金屬層。最後，可能以夂配置 電容器之板。互連痕跡可作成圖# 方式作成連接至 且通道可用以麵合至在其：J屬圖；之=接 構將依被動裝置之耦合方式及對^而定。、疋、接性結 現請回至圖4Α及4Β，其顯示一螺線；電感器4〇2配置在
88122622.ptd 第8頁 475196 五、發明說明（5) 絕緣層414之表面412上之實例。螺線形之外端連接 連痕跡42 0。螺線形之内端耦合至一形成在下面金 互 痕跡422，並藉一通道424耦合至此層。雖然氣橋可胃之 供連接性至螺線形之内端，但此種結構通常較難以制1曰 因此以圖4A及4B中所示之實施例為較佳。依裝置如二=桩 而定，互連痕跡420及422可如圖中所示在相反之金屬層， 或其可在相同金屬層可為螺線形，或其可配置在某其^丄 屬層。_ ^ 凊芩照圖5A-5C，顯示一螺旋狀電感器5〇2之實例。此裝 置由第一複數個金屬分段55〇, 5 5 2及554配置在第一金屬衣 層，亚沿對角線彼此平行設置所組成。第二複數個金屬分 段540, 542, 544及546配置在第二金屬層，並在一相反於第 一金屬分段者之對角方向彼此平行設置。一組通道5 22 一 5 3 2以首尾相連方式’將第一分段連接至第二分段。結果 為：種自頂部觀之，如圖5A中所示之曲折構形，產生一種 螺旋狀、、^構，雖然為正方形螺旋狀結構之外觀。末端分段 540及546藉由通這5 2 0及534耦合至互連痕跡5 0 6及5〇4。或 者，痕跡50 6及5 04可形成在同一金屬層，作為末端分段 540及546，其可不需要通道。所使用之特定結構，將依在 何處將作成至被動裝置之連接而定。 請回至圖6，傳輸線諧振器6〇2之透視圖，顯示一第一板 620配置在第一金屬層61〇中，及一第二板624配置在第二 至，6 1 4中。金屬層被絕緣材料6 2 2所隔開。一配置在另 第一盃屬層612中之金屬條626，夾在二板之間。板之寬 47Μ^〇 五、發明說明（6) 大於金屬條之寬度'。或者，諧振器 624之一構成。 1里从一板620及 ^作土康士發明所作成之被動裝置之最後實例，圖 二自：Γ二：置在絕緣層714之表面712上的金屬 :斛-！i ί 該明白，可將其他被動裝置，以盥以 上斤不凡王相同方式，併入至供IC封裝之疊層基片。太 :月Ϊ:項優點為，封裝基片之互連層通常不如在半導體曰s 2門集。因此可構成較低值電阻器，由於有較； =二χ較寬之痕跡，並且封裝金屬互連為厚於晶粒上金 屬痕跡、。㈤樣，可藉本發明降低電感器及f容器之 之> 電阻’並且因此可實現較高Q之裝置。 討論現將回至代表性電路，其可予以併入至“封裴之美 片。圖8示一儲能電路80()，使用作為諧 ς controned oscillate/；^ ，vco)，包含電感器802及電容器8〇4之一種並聯組合。儲 能電路一般將藉由端子81 〇及81 2耦合至半導體晶粒上之電 路，以完成振盪器電路。 圖8中之剖面圖顯示一半導體晶粒g 2 〇安裝至一疊層基片 822 °晶粒之焊接凸起828耦合至形成在基片822頂上之 互連840-8 1 0。通道85〇_854提供電路徑至下面金屬層824 及826。電容器8〇4係由分別配置在金屬層824及826之板 86 0及862所界定。電感器802係由一配置在金屬層824之螺 線形結構870所界定，圖4A及4B中更詳細列示其細節。 通道850將電容器8〇4之一板耦合至互連痕跡84〇，同時通 第10頁 88122622.ptd 475196 五、發明說明（7) 這852將螺線形結構87〇之外端8 72耦合至痕跡84〇。如 出，痕跡8 4 0對應於電路之端子8 1 〇。 繼之，剖面圖另顯示一互連痕跡88 0，自電容器之板m 延伸至一通道858，其在以上之金屬層連接至螺線形結構 870之内端874。通道854將痕跡880耦合至墊片842。_跡 _因此?應於電路之端子δ12。完成圖8之討U: 晶粒820藉由墊片844、通道8 5 6及墊片846而具有—直接、車 外部可通達之焊接球δ3〇，例示半導體晶粒可如 接收或發出外部訊號。 、，請回至電路實例之圖9。所示之電路為—低通 波器90 0 ’包含電阻器9〇2及電容器9〇4。端子914及;； ^卜^訊號，同時端子910及91⑼合至在半導體晶粒之電 路。d面圖顯示半導體晶粒92〇安裝至一疊層基 一 ::器970配置在金屬層924。電阻器之剖面圖係取自圖μ
In i之視線97〇一9 70。電阻器9 70之一端耦合至-痕跡 98 0，其復耦合至電容器9〇4之一板96 962配置在金屬層92 6。 电令m之另板 曰粒^ 延伸通過基片922之絕緣材料，並接觸半導體 ;: = Ϊί凸起9 28所轉合之墊片94◦。可看出，塾片94〇 9 2雨^端子91()°—痕_2輕合至電容器904之板 。通遏954及9 56分別連接至墊片942及946。如可看 二〇接塾上942及946分別對應於端子914及916。最後，，通道 m電賴墊片944 (其對應於端子9⑷至電阻器97〇 之另一端。 88122622.ptd 第11頁 475190 五、發明說明（8) 此等例證性電路，例示可根 一 置電路。如在上述所揭示 5明貫施之各種被動裝 子重要優點。以此方式所作成動襄置之構造，具有若 及諧振頻率，可設計為】士 ^❼振器，其電抗值（C或L) 本體通常所可利用之值! c : J ::果構成在半導體晶粒 本身之面胃，因此允許較大之物理：：-般具有大於晶粒 器及電感器值。在電容哭主：寸及對應較大之電容 得可能製造多板電容器：較半=金屬層之存在’使 金屬導體，因為陶究或環氧樹腊材：：及較大之 與供互連之同一金屬層作成安 力衣置之'、、〇構，係自 僅有之日作成圖木’故不耗用另外之金屬. 11 Λ ^ °^ v, 合併在封裝/片Λ °被動裝置以所揭示之方式 獲得優於供：何既一新：別之電可定做ic封裝，其可 盆I二t 晶粒設計之現有方法之改進性能。 2代表性電路包括但不限於：電源旁路電| 5? Α φ > 重旁路自"體基片通至旁路電容器二電:用：其：多 ϊ ί;::電阻率材料，導致較高之晶粒上基片隔離丁。二用 提：：互輕合，並因此形成一變壓器。譜振= 有放）。此類型之諧振器可供帶通濾波器、帶阻濾、 ,ν曰co之諧振器、或自激振盪器，及射頻功能調諧；用'、 夕曰曰片杈組（multi 〜chip moduie，簡稱MCM)應用，耦合電路 第12頁 88122622.ptd 4V5196 ί 案號88122^ 五、發明說明（9) 可予以實施為將安萝名莫Η 、一一〜^ 起。 、土 之多重半導體晶粒耦合在 現請回至圖1 〇，討认妯叙社 片之處理步驟。如可；出，；=可併入至κ封裝之基 之步驟，供作成被動裝置：與供形成多重互連層相同 :101°。在此刻可形成通道通匕一層絕緣材料，步 蛤電路徑通至絕緣層之外底^、吧緣層亚且填滿，以提供 體晶粒。其次，將一声雷’因而可作成電連接至半導 關合金）沈積在絕緣層θ上面料（一般使用銅，金，鎢及相 個圖案，以界定供金屬之^012。然後纷成-個或多 =外之圖案，以界定配；同時可綠成 後使圖案經歷鞋刻及 二屬層之被動裝置之結構。然 留下所希望之圖案。不想要之金屬， 絕緣層。為提供連接性 016在孟屬層頂上形成次一 通道，並填滿金屬，步 孟，=，在絕緣層必須鑽成 外數層，則上述步驟；：1 重如果需要另 工步驟包括安裝產生—疊層基片。完 理步驟在I c封裝技藝為孰去。 θ 土片封裝。上述處 明。任何既定技術之選=，σ將扩諸1用任何技術實施本發 望之操作狀況、封褒1 所使用之材料、所希 元件編號說¥ "、求、生產成本等等因素而定。 10 2 5 10 4 電容器 · 106 電感器 曰
J 年 9〇· 8. 15
88122622.ptc 第13頁 475196 案號 88122622 年 月 曰 修正 90. 8. 15 五、發明說明（10) 112 頂面 114 疊層基片 120, 122, 124 互連痕跡 200 金屬層 202 絕緣層 204 金屬層 220,222 金屬板 306 金屑及絕緣層 308 金屬互連層 310 金屬及絕緣層 312 金屬互連層 320, 32 2, 3 24, 32 6 板 330, 332 通道 402 螺線形電感器 412 表面 414 絕緣層 420,42 2 互連痕跡 424 通道 502 螺旋狀電感器 506, 504 互連痕跡 520-534 通道 540, 542, 544, 546 金屬分 5 50, 5 5 2, 5 54 金屬分段 602 傳輸線諧振器
88122622.ptc 第14頁 475196 案號88122622_年月日_修正 90. 8. 15 五、發明說明（11) 610 第 一 金 屬 層 612 第 二 金 屬 層 614 第 二 金 屬 層 620 第 一 板 622 絕 緣 材 料 624 第 二 板 626 金 屬 條 702 電 阻 器 712 表 面 714 絕 緣 層 800 儲 能 電 路 802 電 感 器 804 電 容 器 810, 812 端 子 820 半 導 體 晶 粒 822 安 疊 層 基 片 824,826 下 面 金 屬 層 828 焊 接 凸 起 830 焊 接 球 840 互 連 842, 844, 846 塾 片 850-854 通 道 856,858 通 道 860,862 板
88122622.ptc 第15頁 475196 案號 88122622 年 月 曰 修正 90. 8. 15 五、發明說明（12) 870 螺線形結構 872 外端 874 内端 880 互連痕跡 900 低通濾波器 902 電阻器 904 電容器 910-916 端子 920 半導體晶粒 922 疊層基片 924,926 金屬層 928 焊接凸起 940-946 墊片 950-956 通道 960,962 板 970 電阻器 980, 982 痕跡 1010-1022 步驟 1102 半導體晶粒 1104 焊接球（或π凸起π ) 1106 底層填料環氧樹脂化合物 1110 上部模製環氧樹脂 1112 固著基片 1114 焊接球
88122622.ptc 第16頁 475196 90. 8, 15
88122622.ptc 第17頁 • 15 475196 • 15
裝 圖1為一 ic基片之頂視圖，顯示本發明之互連及被 置之一種配置。 圖2及3為二電容器裝置之側視圖。 圖4A及4B分別為一螺線形電感器之頂視及侧視圖。 圖5A〜5C為一螺旋狀電感器之視圖，分別顯示頂視e 正面視圖及侧視圖。 圖6為一諧振器之透視圖。 圖7Α及7Β為一電阻器之頂視及側視圖。 圖8及9為二形成在I c基片之代表性電路之剖面圖。 圖1 0為本發明之過程步驟之流程圖。 圖11及1 2顯示一種代表性先前技藝I ◦封妒方案。
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Claims (1)

  1. 475196 _案號88122622_年月 六、申請專利範圍 曰 r
    90. 8. 15 修正本 1. 一種積體電路，包含： 一半導體晶粒，具有第一電路配置在其中； 一基片，該晶粒安裝在其上，該基片包括相間之金屬互 連層及絕緣材料層，該晶粒具有電連接至該一層或多層金 屬互連層；以及 一封裝圍繞該晶粒及在基片頂上配置，藉此提供一供該 晶粒之保護罩殼； ， 該基片又包括外部電觸點，該電觸點與若干該金屬互連 電接觸； 該基片又包括第二電路，包含一個或多個被動裝置，配 置在該一層或多層金屬互連層，該電路與在該晶粒之該等 電子裝置之一電連通。 2. 如申請專利範圍第1項之積體電路，其中，又包括一 第二半導體晶粒。 3. 如申請專利範圍第1項之積體電路，其中，該絕緣材 料為一種環氧樹脂。 4. 如申請專利範圍第1項之積體電路，其中，該絕緣材 料為一種陶瓷材料。 5. 如申請專利範圍第1項之積體電路，其中，該第二電 路為一濾波器電路，具有第一對端子、耦合至二該外部電 觸點，及具有第二對端子、耦合至該半導體晶粒。 6 ·如申請專利範圍第1項之積體電路，其中，該第二電 路為一儲能電路，包括一電感器及一電容器，該儲能電路 具有一對端子耦合至該半導體晶粒。
    88122622.ptc 第19頁 475196 _案號88122622_年月日__ 六、申請專利範圍 7. 如申請專利範圍第1項之積體電路，其中，該等外部 電觸點之一係供耦合至電源，及該第二電路包括一功率旁 路電容器耦合至該等外部電觸點之一。 8. 如申請專利範圍第1項之積體電路，其中，該一個或 多個被動裝置包括電感器、電容器、電阻器、及變壓器其 中 ~ 〇 9. 一種積體電路製造方法，包含下列步驟： (a) 在一半導體晶粒上製成電路，包括形成複數個墊片 供傳輸及接收訊號，並提供一個或多個電壓電位； (b) 製成一絕緣材料之基片，包括在基片形成至少一層 導電互連層，及在該至少一層導電互連層内形成至少一被 動裝置； (c )將該半導體晶粒安裝並固著在該基片上； (d) 在該半導體晶粒與該至少一層導電互連層之間作成 電連接；以及 (e) 在該半導體晶粒與該至少一被動裝置之間作成電連 接。 1 0.如申請專利範圍第9項之積體電路製造方法，其中， 步驟（e)包括在該裝置與該墊片之一之間形成一導電通 道。 11.如申請專利範圍第9項之積體電路製造方法，其中， 該至少一被動裝置為一電容器。 ^ 1 2.如申請專利範圍第9項之積體電路製造方法，其中， 該至少一被動裝置為一電感器。
    88122622.ptc 第20頁 475196 案號88122622 年月日 修正 六、申請專利範圍 1 3.如申請專利範圍第9項之積體電路製造方法，其中， 該至少一被動裝置為一諧振器。 1 4.如申請專利範圍第9項之積體電路製造方法，其中， 該至少一被動裝置為一電阻器。 1 5.如申請專利範圍第9項之積體電路製造方法，其中， 該至少一被動裝置為一變壓器。
    88122622.ptc 第21頁
TW088122622A 1999-03-11 1999-12-22 Apparatus and method for an integrated circuit having high Q reactive components TW475196B (en)

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