CN111753478B - 利用有源硅连接层实现内置模拟电路的多裸片fpga - Google Patents

利用有源硅连接层实现内置模拟电路的多裸片fpga Download PDF

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CN111753478B
CN111753478B CN202010622764.XA CN202010622764A CN111753478B CN 111753478 B CN111753478 B CN 111753478B CN 202010622764 A CN202010622764 A CN 202010622764A CN 111753478 B CN111753478 B CN 111753478B
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fpga
circuit structure
silicon
port
bare chip
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CN111753478A (zh
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单悦尔
徐彦峰
范继聪
张艳飞
闫华
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Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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Priority to CN202010622764.XA priority Critical patent/CN111753478B/zh
Publication of CN111753478A publication Critical patent/CN111753478A/zh
Priority to PCT/CN2020/141168 priority patent/WO2022001062A1/zh
Priority to US17/421,460 priority patent/US12009307B2/en
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    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • G—PHYSICS
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    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract

本申请公开了一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，涉及FPGA技术领域，该多裸片FPGA可以支持多个小规模小面积的裸片级联实现大规模大面积的FPGA产品，减少加工难度，提高芯片生产良率；同时由于有源硅连接层的存在，因此一些在裸片内部难以实现的电路结构和/或会占用较大裸片面积的电路结构和/或一些对加工工艺要求较低的电路结构都可以布设在硅连接层，解决现有直接在裸片上制作这些电路结构存在的问题，可以将部分电路结构在硅连接层实现，其余放在裸片内实现，有利于优化FPGA产品的性能、提高***稳定性、减小***面积。

Description

利用有源硅连接层实现内置模拟电路的多裸片FPGA
技术领域
本发明涉及FPGA技术领域，尤其是一种利用有源硅连接层实现内置模拟电路的多裸片FPGA。
背景技术
FPGA(Field Programmable Gate Array，现场可编程逻辑门阵列)是一种硬件可编程的逻辑器件，广泛应用于移动通信、数据中心、导航制导和自动驾驶等领域。随着新型应用对带宽、存储和数据处理能力的需求不断提高，FPGA的规模不断增加、对功能性和稳定性的要求也越来越高，但是，FPGA规模的增加代表芯片面积增大，面积的增加会导致芯片加工难度的提高以及芯片生产良率的降低。而为了实现更优的功能性和稳定性，FPGA往往需要配合相应的模拟电路，但直接在FPGA芯片上制作这些模拟电路的难度较大，即便能够制作也会存在占用很大的宝贵的芯片面积以及其他问题，比如在FPGA芯片内制作电阻的困难虽然较小，但会占用较多芯片面积而且会造成芯片热损耗增大、芯片温度升高或分布不均等问题，所以目前往往会将这些模拟电路作为FPGA的***电路使用，但会导致***结构复杂、集成度低。
发明内容
本发明人针对上述问题及技术需求，提出了一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，本发明的技术方案如下：
一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，该多裸片FPGA包括基板、层叠设置在基板上的硅连接层以及层叠设置在硅连接层上的若干个FPGA裸片，硅连接层覆盖所有的FPGA裸片；
每个FPGA裸片内包括若干个可配置功能模块、环于各个可配置功能模块分布的互连资源模块以及连接点引出端，FPGA裸片内的可配置功能模块至少包括可编程逻辑单元、硅堆叠连接模块和输入输出端口，硅堆叠连接模块内包括若干个硅堆叠连接点，FPGA裸片内的可编程逻辑单元分别与硅堆叠连接点和输入输出端口通过互连资源模块相连，硅堆叠连接点通过重布线层内的顶层金属线与相应的连接点引出端相连；每个FPGA裸片中的连接点引出端通过硅连接层内的跨裸片连线与其他FPGA裸片中相应的连接点引出端相连，每个FPGA裸片可通过硅连接层内的跨裸片连线与其他任意一个FPGA裸片相连；FPGA裸片内的输入输出端口通过硅连接层上的硅通孔连接至基板；
FPGA裸片内还包括第一电路结构，第一电路结构的端口通过互连资源模块连接到相应的硅堆叠连接点后通过重布线层内的顶层金属线连接到相应的连接点引出端；
硅连接层内布设有第二电路结构，第二电路结构包括若干个模拟电路元件，FPGA裸片上与第一电路结构的端口相连的连接点引出端通过硅连接层内的硅连接层连线连接到第二电路结构的端口，第一电路结构和第二电路结构相连形成多裸片FPGA内部的内置模拟电路，硅连接层上的输入输出端口也连接至基板。
其进一步的技术方案为，第二电路结构的电路参数规格大于预定参数规格，预定参数规格为相同电路结构在FPGA裸片内可实现的最大电路参数规格。
其进一步的技术方案为，第二电路结构包括电容器件，电容器件的电容量大于电容量预定参数规格，电容量预定参数规格是FPGA裸片内可实现的最大电容量，电容器件的电容量达到uF以上级别。
其进一步的技术方案为，第二电路结构包括电感器件，电感器件通过硅连接层上的绕线实现，电感器件的电感量大于电感量预定参数规格，电感量预定参数规格是FPGA裸片内可实现的最大电感量，电感器件的电感量达到100nH以上级别。
其进一步的技术方案为，第二电路结构的电路尺寸大于预定尺寸。
其进一步的技术方案为，第二电路结构包括电阻器件、双极性晶体管、运算放大器、锁相环、延迟锁相环、振荡器和射频采集电路中的至少一种。
其进一步的技术方案为，硅连接层和FPGA裸片采用不同的工艺节点，FPGA裸片采用的工艺节点优于硅连接层采用的工艺节点，则第二电路结构对工艺水平的需求低于预定工艺水平。
其进一步的技术方案为，第一电路结构的端口和第二电路结构的端口之间传输模拟信号时，第一电路结构的端口直接通过硅连接层连线连接到第二电路结构的端口。
其进一步的技术方案为，第一电路结构的端口和第二电路结构的端口之间传输数字信号时，第一电路结构的端口与第二电路结构的端口之间的硅连接层连线上还设置有缓冲器。
其进一步的技术方案为，第一电路结构的端口和第二电路结构的端口之间传输差分信号时，则第一电路结构的端口包括第一差分口和第二差分口，第二电路结构的端口也包括第一差分口和第二差分口，两个第一差分口对应连接、两个第二差分口对应连接，且两个第一差分口之间的信号线与两个第二差分口之间的信号线完全相同。
本发明的有益技术效果是：
本申请的多裸片FPGA利用硅连接层集成多个FPGA裸片，可以将多个小规模小面积的FPGA裸片级联实现大规模大面积的FPGA产品，减少加工难度，提高芯片生产良率，加快设计速度；同时由于有源硅连接层的存在，因此一些在裸片内部难以实现的电路结构和/或会占用较大裸片面积的电路结构和/或一些对加工工艺要求较低的电路结构都可以布设在硅连接层，解决现有直接在裸片上制作电路结构存在的问题，可以将部分电路结构在硅连接层实现，其余放在FPGA裸片内实现，通过硅连接层内的连线实现两部分的连接最终在FPGA产品内部集成所需的电路结构，有利于优化FPGA产品的性能、提高***稳定性、减小***面积。
附图说明
图1是本申请的多裸片FPGA的结构剖视图。
图2是本申请的多裸片FPGA的一种内部电路结构示意图。
图3是本申请的多裸片FPGA的另一种内部电路结构示意图。
图4是本申请的多裸片FPGA的另一种部分结构剖视示意图。
图5是本申请的多裸片FPGA的另一种内部电路结构示意图。
具体实施方式
下面结合附图对本发明的具体实施方式做进一步说明。
本申请公开了一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，请参考图1，该多裸片FPGA包括从下至上依次层叠设置的基板1、硅连接层2和若干个FPGA裸片，分别以裸片1、裸片2等表示，依次类推。在实际实现时，该FPGA还包括封装在基板1、硅连接层2和FPGA裸片外部的用于保护各个组件的封装外壳，以及还包括与基板相连的用于信号引出的管脚等，图1中未详细示出这些常规结构。
本申请的FPGA并不是采用单一FPGA裸片结构，而是包含多个FPGA裸片，这多个FPGA裸片均层叠设置在同一个硅连接层2上。这多个FPGA裸片可以在硅连接层2上沿着一维方向排布，如图2所示的俯视图。也可以在硅连接层2上按照二维堆叠方式排布，也即在水平面上沿着横、纵两个方向排布，如图3所示，这多个FPGA裸片在硅连接层2可以合理布局，根据各个FPGA裸片的形状和面积紧凑排布在硅连接层2上使得整个FPGA的整体面积较小且裸片之间的互连性能较好。
本申请对FPGA裸片的内部结构以及FPGA裸片与硅连接层2的连接方式进行了调整和精心设计。接下来，本申请对FPGA裸片与硅连接层2之间的具体连接结构以及实现方式进行介绍：
本申请中的FPGA裸片与常规FPGA裸片有所不同，常规FPGA裸片有多种功能的可配置功能模块组成，常见的可配置功能模块主要包括可编程逻辑单元(CLB或PLBs)和输入输出端口(IOB)，有时还包括一些其他功能模块，比如BRAM、DSP、PC等。每个可配置功能模块具有一个结构相同的环于该可配置功能模块分布的互连资源模块(INT)，各个可配置功能模块之间的水平或垂直连线皆经由INT模块相连。而本申请中的FPGA裸片在该常规结构的基础上，除了包含CLB、IOB和其他功能模块这些常规可配置功能模块之外，还包括根据裸片间信号互连需求专门在裸片内部设计的硅堆叠连接模块，每个硅堆叠连接模块内包括若干个硅堆叠连接点3，硅堆叠连接模块是一种新增的专用于裸片信号引出的可配置功能模块，本申请中的FPGA裸片是将常规FPGA裸片中的某些常规可配置功能模块替换设置成了硅堆叠连接模块。且根据信号互连需求可以对任意位置的常规可配置功能模块进行替换，比如针对现有常规的Column-Based的FPGA架构为例，既可以将硅堆叠连接模块设置在可编程逻辑单元所在的行列结构中，也可以将硅堆叠连接模块设置在其他功能模块所在的行列结构中以得到本申请中的FPGA裸片。
本申请中的FPGA裸片中的每个硅堆叠连接模块也具有一个环于该硅堆叠连接模块分布的互连资源模块，因此本申请中的FPGA裸片的绕线结构可以与常规FPGA裸片保持一致，无需做改变。硅堆叠连接模块与其他各个可配置功能模块之间的水平或垂直连线皆经由INT模块相连，硅堆叠连接模块LNK直接与其对应的互连资源模块INT中的互连开关相连，是互连线的一部分。硅堆叠连接模块LNK与互连开关之间根据连通度需要可以是全互连或部分互连。
本申请中的FPGA裸片还包括与内部硅堆叠连接点3对应的连接点引出端4，FPGA裸片内的硅堆叠连接点3通过重布线层(RDL层)内的顶层金属线5与相应的连接点引出端4相连，需要说明的是，图2和3为了示意硅堆叠连接点3和连接点引出端4的连接关系将两者展示在同一平面上，但请参考图1，硅堆叠连接点3和连接点引出端4实际是处于不同平面的。连接点引出端4通常根据堆叠互连需要沿着第一方向和第二方向按行列结构布设。另外为了实现更高的连通带宽可以布设多行/多列连接点引出端4，也即每个FPGA裸片中沿着第一方向布设有若干行连接点引出端4，和/或，沿着第二方向布设有若干列连接点引出端4，从而实现多行多列的高效二维级联。沿着每个方向布设多行/多列连接点引出端4时，可以是间隔均匀布设，也可以是随机布设。
本申请中的FPGA裸片内还包括第一电路结构，第一电路结构可以是模拟电路、数字电路以及模数混合电路等。第一电路结构的端口通过互连资源模块也连接到相应的硅堆叠连接点3后通过重布线层内的顶层金属线5连接到相应的连接点引出端4。图1仅示出了裸片1内部的第一电路结构，实际多个FPGA裸片内都可以存在相同或不同的第一电路结构。
硅连接层2内布设有跨裸片连线6，FPGA裸片与可编程逻辑单元相连的连接点引出端4通过硅连接层2内的跨裸片连线6即可连接到其他FPGA裸片中相应的连接点引出端4，实现FPGA裸片之间的互连。且由于跨裸片连线6分层布置互不影响，连线跨度和方向都可灵活布设，因此每个FPGA裸片可通过硅连接层2内的跨裸片连线6与其他任意一个FPGA裸片相连。比如在图2中裸片1可以与相邻的裸片2相连，也可以与间隔的裸片3相连。再比如在图3中，裸片4可以与同行的裸片5相连，也可以与同列的裸片6相连，也可以与不同行且不同列的裸片7相连。连接点引出端4与硅连接层2的连接方式具体可以是：FPGA裸片上生长有微凸球，连接点引出端4通过微凸球与硅连接层2连接并通过硅连接层2内部的跨裸片连线6连接至其他FPGA裸片，图1可以看出FPGA裸片底部的微凸球结构，本申请不再详细标示。FPGA裸片内的输入输出端口通过硅连接层2上的硅通孔7连接至基板1。
本申请中的硅连接层2为有源硅连接层，硅连接层2内除了布设有跨裸片连线6之外，还布设有第二电路结构，第二电路结构为模拟电路、包括若干个模拟电路元件。硅连接层2上的输入输出端口也连接至基板1。第二电路结构具体可以实现为多种电路结构，主要有如下三类：
1、第二电路结构是FPGA裸片内不易实现的电路结构。受限于芯片面积和加工难度，FPGA裸片内的某些模拟电路元件往往只能做到较小的电路参数规格，而本申请可以将这些电路参数规格受限的模拟电路元件布设在硅连接层2上以达到较大的电路参数规格，因此硅连接层2上的第二电路结构的电路参数规格大于预定参数规格，该预定参数规格为相同电路结构在FPGA裸片内可实现的最大电路参数规格。这一类模拟电路元件主要有电容和电感：
当为电容器件时，可以由NMOS管实现，第二电路结构包括的电容器件的电容量大于电容量预定参数规格，该电容量预定参数规格是FPGA裸片内可实现的最大电容量。常规的FPGA裸片内的电容通常大小只能在pF级，而本申请第二电路结构中的电容器件的电容量可以达到uF以上级别。比如常规的应用如图4所示，在电源接口VCC处连接电容器件并接地GND可以实现供电降噪滤波的作用，无需外部封装电容，减小封装尺寸。
当为电感器件时，通过硅连接层2上的绕线实现，如图5所示。第二电路结构包括的电感器件的电感量大于电感量预定参数规格，电感量预定参数规格是FPGA裸片内可实现的最大电感量。常规的FPGA裸片内的电感通常大小只能在nH级，而本申请第二电路结构中的电感器件的电感量可以达到100nH以上级别。
2、第二电路结构是规模较大、占用面积较大的电路结构，也即第二电路结构的电路尺寸大于预定尺寸，该预定尺寸为预设的参数。这一类第二电路结构包括电阻器件、双极性晶体管、运算放大器、锁相环、延迟锁相环、振荡器和射频采集电路中的至少一种。这一类大尺寸的电路结构布设在硅连接层内，可以有效减少FPGA裸片的面积，并提高数字逻辑规模。
比如第二电路结构可以是LVDS的终端匹配电阻。
比如第二电路结构可以是锁相环，如图3所示，由鉴相鉴频器、低通滤波器、压控振荡器和分频器构成锁相环，参考时钟经过该锁相环输入FPGA裸片。
比如第二电路结构可以是射频采集电路，则此时可以快速实现支持射频直采的FPGA产品，使得FPGA产品具有低功率、高可靠的优势。
3、第二电路结构是对加工工艺要求较低的电路结构，第二电路结构对工艺水平的需求低于预定工艺水平，该预定工艺水平为一个预定的衡量指标。硅连接层和FPGA裸片采用不同的工艺节点，FPGA裸片采用的工艺节点优于硅连接层采用的工艺节点，通常FPGA裸片采用最先进的工艺节点，以提高逻辑资源规模和***工作频率，而硅连接层的工艺节点则较低，因此可以将对加工工艺要求较低的电路结构布设在硅连接层，提高加工效率。不同元件对工艺水平度需求为业内公知，常见的对加工工艺要求较低的第二电路结构具体可以是电阻、电感、电容等，本申请不详细赘述。
FPGA裸片内与第一电路结构的端口相连的连接点引出端4通过硅连接层内的硅连接层连线连接到第二电路结构的端口，第一电路结构和第二电路结构相连形成多裸片FPGA内部的完整的内置模拟电路。需要说明的是，跨裸片连线连接在FPGA裸片之间，硅连接层连线连接在FPGA裸片和第二电路结构之间，本申请为了对两者的连接关系进行区分才使用了两个不同的名称，但硅连接层连线和跨裸片连线一样实际均为金属线，所以附图中未再单独对硅连接层连线进行标注。
无论第二电路结构具体为何种电路结构，第一电路结构的端口和第二电路结构的端口之间传输的可能是模拟信号、数字信号和差分信号中的任意一种：
当第一电路结构的端口和第二电路结构的端口之间传输的是模拟信号时，第一电路结构的端口直接通过硅连接层连线连接到第二电路结构的端口，也即通过金属线直连。
当第一电路结构的端口和第二电路结构的端口之间传输的是数字信号时，第一电路结构的端口与第二电路结构的端口之间的硅连接层连线上还设置有缓冲器BUF，BUF通常也布设在硅连接层中。
当第一电路结构的端口和第二电路结构的端口之间传输差分信号时，则第一电路结构的端口包括第一差分口和第二差分口，第二电路结构的端口也包括第一差分口和第二差分口，两个第一差分口对应连接、两个第二差分口对应连接，且两个第一差分口之间的信号线与两个第二差分口之间的信号线完全相同。两个差分口之间的信号线包括第一电路结构的差分口-硅堆叠连接点-连接点引出端-第二电路结构的差分口之间的各段线路。完全相同表示必须全程Matched，具有相同布线、形状、距离和接口。
以上所述的仅是本申请的优选实施方式，本发明不限于以上实施例。可以理解，本领域技术人员在不脱离本发明的精神和构思的前提下直接导出或联想到的其他改进和变化，均应认为包含在本发明的保护范围之内。

Claims (7)

1.一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，其特征在于，所述多裸片FPGA包括基板、层叠设置在所述基板上的硅连接层以及层叠设置在所述硅连接层上的若干个FPGA裸片，所述硅连接层覆盖所有的FPGA裸片；
每个FPGA裸片内包括若干个可配置功能模块、环于各个可配置功能模块分布的互连资源模块以及连接点引出端，所述FPGA裸片内的可配置功能模块至少包括可编程逻辑单元、硅堆叠连接模块和输入输出端口，所述硅堆叠连接模块内包括若干个硅堆叠连接点，所述FPGA裸片内的可编程逻辑单元分别与硅堆叠连接点和输入输出端口通过互连资源模块相连，所述硅堆叠连接点通过重布线层内的顶层金属线与相应的连接点引出端相连；每个FPGA裸片中的连接点引出端通过所述硅连接层内的跨裸片连线与其他FPGA裸片中相应的连接点引出端相连，每个FPGA裸片可通过所述硅连接层内的跨裸片连线与其他任意一个FPGA裸片相连；FPGA裸片内的输入输出端口通过所述硅连接层上的硅通孔连接至所述基板；
所述FPGA裸片内还包括第一电路结构，所述第一电路结构的端口通过所述互连资源模块连接到相应的硅堆叠连接点后通过重布线层内的顶层金属线连接到相应的连接点引出端；
所述硅连接层内布设有第二电路结构，所述第二电路结构包括若干个模拟电路元件，所述FPGA裸片上与所述第一电路结构的端口相连的连接点引出端通过所述硅连接层内的硅连接层连线连接到所述第二电路结构的端口，所述第一电路结构和所述第二电路结构相连形成所述多裸片FPGA内部的内置模拟电路，所述硅连接层上的输入输出端口也连接至所述基板；
其中，所述第二电路结构的电路参数规格大于预定参数规格，所述预定参数规格为相同电路结构在FPGA裸片内可实现的最大电路参数规格；和/或，所述第二电路结构的电路尺寸大于预定尺寸；和/或，所述硅连接层和FPGA裸片采用不同的工艺节点，FPGA裸片采用的工艺节点优于所述硅连接层采用的工艺节点，则所述第二电路结构对工艺水平的需求低于预定工艺水平。
2.根据权利要求1所述的多裸片FPGA，其特征在于，
所述第二电路结构包括电容器件，所述电容器件的电容量大于电容量预定参数规格，所述电容量预定参数规格是FPGA裸片内可实现的最大电容量，所述电容器件的电容量达到uF以上级别。
3.根据权利要求1所述的多裸片FPGA，其特征在于，所述第二电路结构包括电感器件，所述电感器件通过所述硅连接层上的绕线实现，所述电感器件的电感量大于电感量预定参数规格，所述电感量预定参数规格是FPGA裸片内可实现的最大电感量，所述电感器件的电感量达到100nH以上级别。
4.根据权利要求1所述的多裸片FPGA，其特征在于，所述第二电路结构包括电阻器件、双极性晶体管、运算放大器、锁相环、延迟锁相环、振荡器和射频采集电路中的至少一种。
5.根据权利要求1-4任一所述的多裸片FPGA，其特征在于，
所述第一电路结构的端口和所述第二电路结构的端口之间传输模拟信号时，所述第一电路结构的端口直接通过硅连接层连线连接到所述第二电路结构的端口。
6.根据权利要求1-4任一所述的多裸片FPGA，其特征在于，
所述第一电路结构的端口和所述第二电路结构的端口之间传输数字信号时，所述第一电路结构的端口与所述第二电路结构的端口之间的硅连接层连线上还设置有缓冲器。
7.根据权利要求1-4任一所述的多裸片FPGA，其特征在于，所述第一电路结构的端口和所述第二电路结构的端口之间传输差分信号时，则所述第一电路结构的端口包括第一差分口和第二差分口，所述第二电路结构的端口也包括第一差分口和第二差分口，两个第一差分口对应连接、两个第二差分口对应连接，且两个第一差分口之间的信号线与两个第二差分口之间的信号线完全相同。
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