WO2022001062A1 - 利用有源硅连接层实现内置模拟电路的多裸片fpga - Google Patents

利用有源硅连接层实现内置模拟电路的多裸片fpga Download PDF

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Publication number
WO2022001062A1
WO2022001062A1 PCT/CN2020/141168 CN2020141168W WO2022001062A1 WO 2022001062 A1 WO2022001062 A1 WO 2022001062A1 CN 2020141168 W CN2020141168 W CN 2020141168W WO 2022001062 A1 WO2022001062 A1 WO 2022001062A1
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Prior art keywords
fpga
die
circuit structure
silicon
circuit
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PCT/CN2020/141168
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English (en)
French (fr)
Inventor
单悦尔
徐彦峰
范继聪
张艳飞
闫华
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无锡中微亿芯有限公司
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Priority to US17/421,460 priority Critical patent/US12009307B2/en
Publication of WO2022001062A1 publication Critical patent/WO2022001062A1/zh

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    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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    • H01L2924/143—Digital devices
    • H01L2924/14335—Digital signal processor [DSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Definitions

  • the invention relates to the technical field of FPGA, in particular to a multi-die FPGA which utilizes an active silicon connection layer to realize a built-in analog circuit.
  • FPGA Field Programmable Gate Array
  • Field Programmable Gate Array is a hardware programmable logic device, which is widely used in mobile communications, data centers, navigation and guidance, and autonomous driving.
  • the scale of FPGAs continues to increase, and the requirements for functionality and stability are also getting higher and higher.
  • the increase in chip processing will lead to an increase in the difficulty of chip processing and a decrease in chip production yield.
  • FPGAs often need to cooperate with corresponding analog circuits, but it is difficult to fabricate these analog circuits directly on the FPGA chip, and even if they can be fabricated, it will occupy a lot of precious chip area.
  • the present inventor proposes a multi-die FPGA that utilizes an active silicon connection layer to realize a built-in analog circuit.
  • the technical solution of the present invention is as follows:
  • a multi-die FPGA utilizing an active silicon connection layer to realize a built-in analog circuit comprising a substrate, a silicon connection layer stacked on the substrate, and several FPGA bare chips stacked on the silicon connection layer, Silicon connection layer covers all FPGA die;
  • Each FPGA die includes several configurable functional modules, interconnection resource modules distributed around each configurable functional module, and connection point terminals.
  • the configurable functional modules in the FPGA die at least include programmable logic units, silicon Stacking connection module and input and output ports.
  • the silicon stacking connection module includes several silicon stacking connection points.
  • the programmable logic units in the FPGA die are respectively connected with the silicon stacking connection point and the input and output ports through the interconnection resource module.
  • the silicon stacking connection The point is connected to the corresponding connection point terminal through the top metal wire in the redistribution layer; the connection point terminal in each FPGA die is connected to the corresponding connection in other FPGA die through the cross-die connection in the silicon connection layer.
  • Each FPGA die can be connected to any other FPGA die through the cross-die connection in the silicon connection layer; the input and output ports in the FPGA die are connected to the through-silicon via on the silicon connection layer. substrate;
  • a first circuit structure is formed in the FPGA bare chip, and the port of the first circuit structure is connected to the corresponding silicon stack connection point through the interconnection resource module and then connected to the corresponding connection point lead-out terminal through the top metal wire in the redistribution layer;
  • a second circuit structure is arranged in the silicon connection layer, the second circuit structure includes several analog circuit elements, and the connection point terminals on the FPGA die that are connected to the ports of the first circuit structure are connected through the silicon connection layer in the silicon connection layer.
  • the first circuit structure and the second circuit structure are connected to form a built-in analog circuit inside the multi-die FPGA, and the input and output ports on the silicon connection layer are also connected to the substrate.
  • a further technical solution is that the circuit parameter specification of the second circuit structure is greater than the predetermined parameter specification, and the predetermined parameter specification is the maximum circuit parameter specification that the same circuit structure can realize in the FPGA bare chip.
  • the second circuit structure includes a capacitor device, the capacitance of the capacitor device is greater than the predetermined parameter specification of the capacitance, the predetermined parameter specification of the capacitance is the maximum capacitance that can be realized in the FPGA bare chip, and the capacitance of the capacitor device reaches Above uF level.
  • the second circuit structure includes an inductance device, the inductance device is realized by winding on the silicon connection layer, the inductance of the inductance device is greater than the predetermined parameter specification of the inductance, and the predetermined parameter of the inductance is available in the FPGA bare chip.
  • the maximum inductance achieved, the inductance of the inductive device reaches the level of more than 100nH.
  • a further technical solution thereof is that the circuit size of the second circuit structure is larger than a predetermined size.
  • the second circuit structure includes at least one of a resistance device, a bipolar transistor, an operational amplifier, a phase-locked loop, a delay-locked loop, an oscillator and a radio frequency acquisition circuit.
  • a further technical solution is that the silicon connection layer and the FPGA bare chip use different process nodes, and the process node used by the FPGA bare chip is superior to the process node used by the silicon connection layer, and the second circuit structure requires a lower process level than a predetermined process. craftsmanship level.
  • a further technical solution is that when analog signals are transmitted between the port of the first circuit structure and the port of the second circuit structure, the port of the first circuit structure is directly connected to the port of the second circuit structure through a silicon connection layer connection.
  • a further technical solution is that when a differential signal is transmitted between the port of the first circuit structure and the port of the second circuit structure, the port of the first circuit structure includes a first differential port and a second differential port, and the port of the second circuit structure
  • the port also includes a first differential port and a second differential port, the two first differential ports are correspondingly connected, the two second differential ports are correspondingly connected, and the signal lines between the two first differential ports are connected to the two second differential ports.
  • the signal lines between are exactly the same.
  • a further technical solution thereof is that the first circuit structure formed in at least one FPGA die in the multi-die FPGA is a digital circuit, and/or the first circuit structure formed in at least one FPGA die is an analog circuit, And/or, the first circuit structure formed in at least one FPGA die is an analog-digital hybrid circuit.
  • the multi-die FPGA further includes other die stacked on the silicon connection layer, and a third circuit structure of an analog circuit structure is formed inside the other die, and the port of the third circuit structure is connected to the corresponding silicon.
  • the top metal wires in the redistribution layer are connected to the corresponding connection point terminals, and are connected to the ports of the second circuit structure through the silicon connection layer in the silicon connection layer; the third circuit structure is connected to the first circuit structure.
  • the circuit structure and the second circuit structure are connected to form a built-in analog circuit inside the multi-die FPGA.
  • a further technical solution thereof is that the circuit parameters of the second circuit structure are adjusted and configured by a configuration circuit inside the multi-die FPGA.
  • the configuration circuit inside the multi-die FPGA is a configuration chain inside the FPGA die.
  • a further technical solution is that the configuration circuit inside the multi-die FPGA is a dynamically reconfigurable port inside the FPGA die.
  • the first circuit structure is constructed based on programmable logic units in the FPGA bare chip, and the programmable logic units constructed to form the first circuit structure include at least one of CLB, BRAM and DSP.
  • a further technical solution thereof is that the programmable logic unit used to construct and form the first circuit structure is dynamically configured by the dynamic programmable port of the FPGA bare chip where it is located.
  • the multi-die FPGA of the present application utilizes a silicon connection layer to integrate multiple FPGA die, which can cascade multiple small-scale and small-area FPGA die to realize large-scale and large-area FPGA products, reduce processing difficulty, and improve chip production yield. , to speed up the design; at the same time, due to the existence of the active silicon connection layer, some circuit structures that are difficult to realize inside the die and/or those that occupy a larger die area and/or some circuit structures that require less processing technology
  • the circuit structure can be laid on the silicon connection layer, which solves the existing problems of directly fabricating the circuit structure on the bare chip. Part of the circuit structure can be realized in the silicon connection layer, and the rest can be realized in the FPGA bare chip.
  • the connection realizes the connection of the two parts and finally integrates the required circuit structure in the FPGA product, which is beneficial to optimize the performance of the FPGA product, improve the system stability, and reduce the system area.
  • FIG. 1 is a cross-sectional view of the structure of the multi-die FPGA of the present application.
  • FIG. 2 is a schematic diagram of an internal circuit structure of the multi-die FPGA of the present application.
  • FIG. 3 is a schematic diagram of another internal circuit structure of the multi-die FPGA of the present application.
  • FIG. 4 is another partial structural cross-sectional schematic diagram of the multi-die FPGA of the present application.
  • FIG. 5 is a schematic diagram of another internal circuit structure of the multi-die FPGA of the present application.
  • FIG. 6 is a schematic diagram of another internal circuit structure of the multi-die FPGA of the present application.
  • the present application discloses a multi-die FPGA that utilizes an active silicon connection layer to realize a built-in analog circuit. Please refer to FIG. 1 .
  • the multi-die FPGA includes a substrate 1 , a silicon connection layer 2 , and several The FPGA die are represented by die 1, die 2, etc., and so on.
  • the FPGA also includes a package casing that is packaged on the substrate 1, the silicon connection layer 2 and the outside of the FPGA die for protecting each component, and also includes pins connected to the substrate for signal extraction, etc. These conventional structures are not shown in detail in 1.
  • the FPGA of the present application does not use a single FPGA die structure, but includes multiple FPGA die, and the multiple FPGA die are stacked on the same silicon connection layer 2 .
  • the plurality of FPGA die can be arranged along a one-dimensional direction on the silicon connection layer 2 , as shown in the top view in FIG. 2 . It can also be arranged in a two-dimensional stacking manner on the silicon connection layer 2, that is, arranged in the horizontal and vertical directions on the horizontal plane. As shown in FIG. Reasonable layout, according to the shape and area of each FPGA die, is compactly arranged on the silicon connection layer 2 so that the overall area of the entire FPGA is small and the interconnection performance between the die is better.
  • This application adjusts and carefully designs the internal structure of the FPGA die and the connection method between the FPGA die and the silicon connection layer 2 .
  • this application introduces the specific connection structure and implementation method between the FPGA die and the silicon connection layer 2:
  • the FPGA die in this application is different from the conventional FPGA die.
  • the conventional FPGA die is composed of configurable functional modules with various functions.
  • the common configurable functional modules mainly include programmable logic units (CLB or PLBs) and input Output port (IOB), and sometimes include some other functional modules, such as BRAM, DSP, PC, etc.
  • Each configurable function module has an interconnection resource module (INT) distributed around the configurable function module with the same structure, and the horizontal or vertical connections between the configurable function modules are all connected through the INT module.
  • INT interconnection resource module
  • the FPGA die in this application in addition to the conventional configurable functional modules such as CLB, IOB and other functional modules, also includes a special design inside the die according to the signal interconnection requirements between the die.
  • the silicon stack connection module is a new silicon stack connection module, and each silicon stack connection module includes several silicon stack connection points 3.
  • the silicon stack connection module is a newly added configurable function module dedicated to the signal extraction of the bare chip.
  • the FPGA bare in this application The chip is the replacement of some conventional configurable functional blocks in the conventional FPGA die with silicon stack connection blocks. And according to the signal interconnection requirements, the conventional configurable functional modules at any position can be replaced.
  • the silicon stack connection module can be set in the row and column where the programmable logic unit is located. In the structure, the silicon stack connection module can also be arranged in the row-column structure where other functional modules are located to obtain the FPGA bare chip in the present application.
  • Each silicon stack connection module in the FPGA die in this application also has an interconnection resource module distributed around the silicon stack connection module, so the wiring structure of the FPGA die in this application can be similar to that of a conventional FPGA die Be consistent, no changes are required.
  • the horizontal or vertical connections between the silicon stack connection module and other configurable functional modules are all connected through the INT module.
  • the silicon stack connection module LNK is directly connected to the interconnect switch in the corresponding interconnect resource module INT, which is an interconnect line. a part of.
  • the interconnection between the silicon stack connection module LNK and the interconnection switch may be fully interconnected or partially interconnected according to the need for connectivity.
  • the FPGA die in this application also includes connection point terminals 4 corresponding to the internal silicon stack connection points 3, and the silicon stack connection points 3 in the FPGA die are connected to the corresponding top metal lines 5 in the redistribution layer (RDL layer).
  • RDL layer redistribution layer
  • connection point terminals 4 can be arranged, that is, each FPGA die is arranged with several rows of connection point terminals 4 along the first direction, and/or, along the Several columns of connection point lead-out ends 4 are arranged in the second direction, so as to realize efficient two-dimensional cascading of multiple rows and multiple columns.
  • connection point terminal 4 When arranging multiple rows/columns of connection point terminal 4 along each direction, it may be evenly arranged at intervals, or may be arranged randomly.
  • a first circuit structure is formed in the FPGA bare chip in the present application, and the first circuit structure may be an analog circuit, a digital circuit, an analog-digital hybrid circuit, or the like.
  • the first circuit structure may be constructed based on programmable logic units inside the FPGA die, and the programmable logic units constructed to form the first circuit structure include at least one of CLB, BRAM, and DSP.
  • the programmable logic unit used to construct and form the first circuit structure can be dynamically configured by the dynamic programmable port of the FPGA die where it is located.
  • the port of the first circuit structure is also connected to the corresponding silicon stack connection point 3 through the interconnection resource module and then connected to the corresponding connection point terminal 4 through the top metal wire 5 in the redistribution layer.
  • FIG. 1 only shows the first circuit structure inside the die 1, and actually, the same or different first circuit structures may exist in multiple FPGA die.
  • a cross-die connection 6 is arranged in the silicon connection layer 2, and the connection point terminal 4 connecting the FPGA die to the programmable logic unit can be connected to other FPGA die through the cross-die connection 6 in the silicon connection layer 2
  • the corresponding connection point in the terminal 4 realizes the interconnection between the FPGA bare chips.
  • the layered arrangement of the cross-die connection 6 does not affect each other, the span and direction of the connection can be flexibly laid out, so each FPGA die can be connected to any other FPGA through the cross-die connection 6 in the silicon connection layer 2.
  • Die connected for example, in FIG. 2 , the die 1 may be connected to the adjacent die 2 , or may be connected to the spaced die 3 .
  • FIG. 2 the die 1 may be connected to the adjacent die 2 , or may be connected to the spaced die 3 .
  • the die 4 can be connected to the die 5 in the same row, can also be connected to the die 6 in the same column, and can also be connected to the die 7 in different rows and columns.
  • the connection method between the connection point terminal 4 and the silicon connection layer 2 may specifically be as follows: micro-convex balls are grown on the FPGA bare chip, the connection point terminal 4 is connected to the silicon connection layer 2 through the micro-convex balls, and passes through the cross-section inside the silicon connection layer 2.
  • the die connection line 6 is connected to other FPGA die.
  • Fig. 1 shows the micro-convex ball structure at the bottom of the FPGA die, which is not indicated in detail in this application.
  • the input and output ports in the FPGA die are connected to the substrate 1 through the through silicon vias 7 on the silicon connection layer 2 .
  • the silicon connection layer 2 in this application is an active silicon connection layer.
  • the silicon connection layer 2 is also provided with a second circuit structure.
  • the second circuit structure is an analog circuit, including several an analog circuit element.
  • the input and output ports on the silicon connection layer 2 are also connected to the substrate 1 .
  • the second circuit structure can be specifically implemented as a variety of circuit structures, mainly in the following three categories:
  • the second circuit structure is a circuit structure that is not easy to implement in the FPGA die. Limited by the chip area and processing difficulty, some analog circuit components in the FPGA die can often only achieve smaller circuit parameter specifications, and this application can arrange these analog circuit components with limited circuit parameter specifications on the silicon connection. In order to achieve a larger circuit parameter specification on layer 2, the circuit parameter specification of the second circuit structure on the silicon connection layer 2 is larger than a predetermined parameter specification, and the predetermined parameter specification is the maximum circuit that the same circuit structure can realize in the FPGA die. Specifications.
  • This type of analog circuit components mainly include capacitors and inductors:
  • the capacitance in a conventional FPGA die is usually only at the pF level, while the capacitance of the capacitive device in the second circuit structure of the present application can reach the uF level or above.
  • connecting a capacitor device at the power interface VCC and grounding GND can realize the function of noise reduction and filtering of the power supply, without external packaging capacitors and reducing the package size.
  • the inductance of the inductance device included in the second circuit structure is greater than the predetermined parameter specification of the inductance, and the predetermined parameter of the inductance is the maximum inductance that can be realized in the FPGA bare chip.
  • the inductance in a conventional FPGA die is usually only in the nH level, while the inductance of the inductance device in the second circuit structure of the present application can reach the level of more than 100nH.
  • the second circuit structure is a circuit structure with a larger scale and a larger occupation area, that is, the circuit size of the second circuit structure is larger than a predetermined size, and the predetermined size is a preset parameter.
  • This type of second circuit structure includes at least one of a resistive device, a bipolar transistor, an operational amplifier, a phase-locked loop, a delay-locked loop, an oscillator, and a radio frequency acquisition circuit.
  • This type of large-scale circuit structure is arranged in the silicon connection layer, which can effectively reduce the area of FPGA die and increase the scale of digital logic.
  • the second circuit structure may be a terminal matching resistor of LVDS.
  • the second circuit structure can be a phase-locked loop.
  • a phase-locked loop is formed by a phase- and frequency-discriminator, a low-pass filter, a voltage-controlled oscillator and a frequency divider.
  • the reference clock is input through the phase-locked loop.
  • FPGA die FPGA die.
  • the second circuit structure may be a radio frequency acquisition circuit.
  • an FPGA product that supports direct radio frequency acquisition can be quickly implemented, so that the FPGA product has the advantages of low power and high reliability.
  • the second circuit structure is a circuit structure with lower requirements on the processing technology, and the second circuit structure requires a technology level lower than a predetermined technology level, and the predetermined technology level is a predetermined measurement index.
  • the silicon connection layer and the FPGA die use different process nodes.
  • the process node used by the FPGA die is superior to the process node used by the silicon connection layer.
  • the FPGA die adopts the most advanced process node to improve the scale of logic resources and system operating frequency.
  • the process node of the silicon connection layer is lower, so the circuit structure that requires less processing technology can be arranged on the silicon connection layer, and the processing efficiency is improved.
  • It is well known in the industry that different components have requirements on process level, and a common second circuit structure with lower requirements on processing technology may specifically be a resistor, an inductor, a capacitor, etc., which will not be described in detail in this application.
  • connection point terminal 4 connected to the port of the first circuit structure in the FPGA bare chip is connected to the port of the second circuit structure through the silicon connection layer connection line in the silicon connection layer, and the first circuit structure and the second circuit structure are connected to form a multi-circuit structure.
  • the cross-die connection is connected between the FPGA die, and the silicon connection layer connection is connected between the FPGA die and the second circuit structure, which is used in this application to distinguish the connection relationship between the two. Two different names, but the silicon connection layer connection and the cross-die connection are actually metal wires, so the silicon connection layer connection is not separately marked in the attached drawing.
  • the built-in analog circuit in a multi-die FPGA mainly includes the analog part and the corresponding the required number part.
  • the analog part of the built-in analog circuit is all arranged on the silicon connection layer, that is, the analog part is only realized by the second circuit structure.
  • a part of the analog part of the built-in analog circuit is arranged in the silicon connection layer, and a part is arranged in the FPGA die.
  • the first circuit structure formed in at least one FPGA die in the multi-die FPGA is an analog circuit
  • the silicon connection The second circuit structure within the layer forms an analog portion together with the first circuit structure within the at least one FPGA die.
  • the analog part of the built-in analog circuit is partly arranged in the silicon connection layer and partly in other bare chips.
  • the multi-die FPGA also includes other bare chips stacked on the silicon connection layer.
  • the structures of other die are similar to the structures of the FPGA die in this application, and all include silicon stack connection modules.
  • the port of the third circuit structure is connected to the corresponding connection point of the silicon stack and then connected to the corresponding connection point terminal through the top metal wire in the redistribution layer, and is connected to the second circuit through the connection of the silicon connection layer in the silicon connection layer
  • the port of the structure is similar to the way in which the first circuit structure is connected to the second circuit structure, which will not be repeated in this application. Please refer to FIG.
  • the die 4 is an FPGA die. Other dies are also laid out.
  • the third circuit structure is connected with the first circuit structure and the second circuit structure to form a built-in analog circuit inside the multi-die FPGA.
  • the second circuit structure in the silicon connection layer is formed as an analog part together with the third circuit structure in the other die.
  • the multi-die FPGA includes one or more other dice inside, and the third circuit structure inside each other dice is connected by the silicon connection layer wiring in the silicon connection layer to form a larger-scale third circuit structure. Circuit configuration.
  • the digital part of the built-in analog circuit is arranged in the silicon connection layer, or the digital part is arranged in at least one FPGA die, or the digital part is arranged in the silicon connection layer and at least one FPGA die.
  • the first circuit structure formed in at least one FPGA die in the multi-die FPGA is a digital circuit.
  • the analog-digital hybrid circuit in the FPGA die forms an analog part together with the second circuit structure in the silicon connection layer, and on the other hand, it also forms an analog part. together form the digital part.
  • any one of analog signals, digital signals and differential signals may be transmitted between the port of the first circuit structure and the port of the second circuit structure:
  • the port of the first circuit structure is directly connected to the port of the second circuit structure through a silicon connection layer connection, that is, through a metal wire Direct connection.
  • a buffer is also provided on the silicon connection layer connection between the port of the first circuit structure and the port of the second circuit structure BUFs, BUFs are usually also routed in the silicon connection layer.
  • the port of the first circuit structure includes the first differential port and the second differential port
  • the port of the second circuit structure also includes the first differential port port and second differential port
  • the two first differential ports are connected correspondingly
  • the two second differential ports are connected correspondingly
  • the signal lines between the two first differential ports and the signal lines between the two second differential ports are completely same.
  • the signal line between the two differential ports includes each segment of line between the differential port of the first circuit structure-silicon stack connection point-connection point lead-out terminal-the differential port of the second circuit structure. Identical representations must be Matched throughout, with the same routing, shape, distance, and interface.
  • circuit parameters of the second circuit structure in the present application can be adjusted and configured by a configuration circuit inside the multi-die FPGA, where the configuration circuit is a configuration chain inside the FPGA die, or is dynamically reconfigurable inside the FPGA die port. same,

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Abstract

一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，涉及FPGA技术领域，该多裸片FPGA可以支持多个小规模小面积的裸片级联实现大规模大面积的FPGA产品，减少加工难度，提高芯片生产良率；同时由于有源硅连接层的存在，因此一些在裸片内部难以实现的电路结构和/或会占用较大裸片面积的电路结构和/或一些对加工工艺要求较低的电路结构都可以布设在硅连接层，解决现有直接在裸片上制作这些电路结构存在的问题，可以将部分电路结构在硅连接层实现，其余放在裸片内实现，有利于优化FPGA产品的性能、提高***稳定性、减小***面积。

Description

利用有源硅连接层实现内置模拟电路的多裸片FPGA 技术领域
本发明涉及FPGA技术领域，尤其是一种利用有源硅连接层实现内置模拟电路的多裸片FPGA。
背景技术
FPGA(Field Programmable Gate Array，现场可编程逻辑门阵列)是一种硬件可编程的逻辑器件，广泛应用于移动通信、数据中心、导航制导和自动驾驶等领域。随着新型应用对带宽、存储和数据处理能力的需求不断提高，FPGA的规模不断增加、对功能性和稳定性的要求也越来越高，但是，FPGA规模的增加代表芯片面积增大，面积的增加会导致芯片加工难度的提高以及芯片生产良率的降低。而为了实现更优的功能性和稳定性，FPGA往往需要配合相应的模拟电路，但直接在FPGA芯片上制作这些模拟电路的难度较大，即便能够制作也会存在占用很大的宝贵的芯片面积以及其他问题，比如在FPGA芯片内制作电阻的困难虽然较小，但会占用较多芯片面积而且会造成芯片热损耗增大、芯片温度升高或分布不均等问题，所以目前往往会将这些模拟电路作为FPGA的***电路使用，但会导致***结构复杂、集成度低。
发明内容
本发明人针对上述问题及技术需求，提出了一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，本发明的技术方案如下：
一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，该多裸片FPGA包括基板、层叠设置在基板上的硅连接层以及层叠设置在硅连接层上的若干个FPGA裸片，硅连接层覆盖所有的FPGA裸片；
每个FPGA裸片内包括若干个可配置功能模块、环于各个可配置功能模块分布的互连资源模块以及连接点引出端，FPGA裸片内的可配置功能模块至少包括可编程逻辑单元、硅堆叠连接模块和输入输出端口，硅堆叠连接模块内包括若干个硅堆叠连接点，FPGA裸片内的可编程逻辑单元分别与硅堆叠连接点和输入输出端口通过互连资源模块相连，硅堆叠连接点通过重布线层内的顶层 金属线与相应的连接点引出端相连；每个FPGA裸片中的连接点引出端通过硅连接层内的跨裸片连线与其他FPGA裸片中相应的连接点引出端相连，每个FPGA裸片可通过硅连接层内的跨裸片连线与其他任意一个FPGA裸片相连；FPGA裸片内的输入输出端口通过硅连接层上的硅通孔连接至基板；
FPGA裸片内形成有第一电路结构，第一电路结构的端口通过互连资源模块连接到相应的硅堆叠连接点后通过重布线层内的顶层金属线连接到相应的连接点引出端；
硅连接层内布设有第二电路结构，第二电路结构包括若干个模拟电路元件，FPGA裸片上与第一电路结构的端口相连的连接点引出端通过硅连接层内的硅连接层连线连接到第二电路结构的端口，第一电路结构和第二电路结构相连形成多裸片FPGA内部的内置模拟电路，硅连接层上的输入输出端口也连接至基板。
其进一步的技术方案为，第二电路结构的电路参数规格大于预定参数规格，预定参数规格为相同电路结构在FPGA裸片内可实现的最大电路参数规格。
其进一步的技术方案为，第二电路结构包括电容器件，电容器件的电容量大于电容量预定参数规格，电容量预定参数规格是FPGA裸片内可实现的最大电容量，电容器件的电容量达到uF以上级别。
其进一步的技术方案为，第二电路结构包括电感器件，电感器件通过硅连接层上的绕线实现，电感器件的电感量大于电感量预定参数规格，电感量预定参数规格是FPGA裸片内可实现的最大电感量，电感器件的电感量达到100nH以上级别。
其进一步的技术方案为，第二电路结构的电路尺寸大于预定尺寸。
其进一步的技术方案为，第二电路结构包括电阻器件、双极性晶体管、运算放大器、锁相环、延迟锁相环、振荡器和射频采集电路中的至少一种。
其进一步的技术方案为，硅连接层和FPGA裸片采用不同的工艺节点，FPGA裸片采用的工艺节点优于硅连接层采用的工艺节点，则第二电路结构对工艺水平的需求低于预定工艺水平。
其进一步的技术方案为，第一电路结构的端口和第二电路结构的端口之间传输模拟信号时，第一电路结构的端口直接通过硅连接层连线连接到第二电路结构的端口。
其进一步的技术方案为，第一电路结构的端口和第二电路结构的端口之间 传输数字信号时，第一电路结构的端口与第二电路结构的端口之间的硅连接层连线上还设置有缓冲器。
其进一步的技术方案为，第一电路结构的端口和第二电路结构的端口之间传输差分信号时，则第一电路结构的端口包括第一差分口和第二差分口，第二电路结构的端口也包括第一差分口和第二差分口，两个第一差分口对应连接、两个第二差分口对应连接，且两个第一差分口之间的信号线与两个第二差分口之间的信号线完全相同。
其进一步的技术方案为，所述多裸片FPGA中至少一个FPGA裸片内形成的第一电路结构为数字电路，和/或，至少一个FPGA裸片内形成的第一电路结构为模拟电路，和/或，至少一个FPGA裸片内形成的第一电路结构为模数混合电路。
其进一步的技术方案为，多裸片FPGA还包括层叠设置在硅连接层上的其他裸片，其他裸片内部形成模拟电路结构的第三电路结构，第三电路结构的端口连接到相应的硅堆叠连接点后通过重布线层内的顶层金属线连接到相应的连接点引出端、并通过硅连接层内的硅连接层连线连接到第二电路结构的端口；第三电路结构与第一电路结构和第二电路结构相连形成多裸片FPGA内部的内置模拟电路。
其进一步的技术方案为，第二电路结构的电路参数由多裸片FPGA内部的配置电路调节配置。
其进一步的技术方案为，多裸片FPGA内部的配置电路为FPGA裸片内部的配置链。
其进一步的技术方案为，多裸片FPGA内部的配置电路为FPGA裸片内部的动态可重配端口。
其进一步的技术方案为，第一电路结构基于FPGA裸片内的可编程逻辑单元构建形成，构建形成第一电路结构的可编程逻辑单元包括CLB、BRAM和DSP中的至少一种。
其进一步的技术方案为，用于构建形成第一电路结构的可编程逻辑单元由所在的FPGA裸片的动态可编程端口进行动态配置。
本发明的有益技术效果是：
本申请的多裸片FPGA利用硅连接层集成多个FPGA裸片，可以将多个小规模小面积的FPGA裸片级联实现大规模大面积的FPGA产品，减少加工难度， 提高芯片生产良率，加快设计速度；同时由于有源硅连接层的存在，因此一些在裸片内部难以实现的电路结构和/或会占用较大裸片面积的电路结构和/或一些对加工工艺要求较低的电路结构都可以布设在硅连接层，解决现有直接在裸片上制作电路结构存在的问题，可以将部分电路结构在硅连接层实现，其余放在FPGA裸片内实现，通过硅连接层内的连线实现两部分的连接最终在FPGA产品内部集成所需的电路结构，有利于优化FPGA产品的性能、提高***稳定性、减小***面积。
附图说明
图1是本申请的多裸片FPGA的结构剖视图。
图2是本申请的多裸片FPGA的一种内部电路结构示意图。
图3是本申请的多裸片FPGA的另一种内部电路结构示意图。
图4是本申请的多裸片FPGA的另一种部分结构剖视示意图。
图5是本申请的多裸片FPGA的另一种内部电路结构示意图。
图6是本申请的多裸片FPGA的另一种内部电路结构示意图。
具体实施方式
下面结合附图对本发明的具体实施方式做进一步说明。
本申请公开了一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，请参考图1，该多裸片FPGA包括从下至上依次层叠设置的基板1、硅连接层2和若干个FPGA裸片，分别以裸片1、裸片2等表示，依次类推。在实际实现时，该FPGA还包括封装在基板1、硅连接层2和FPGA裸片外部的用于保护各个组件的封装外壳，以及还包括与基板相连的用于信号引出的管脚等，图1中未详细示出这些常规结构。
本申请的FPGA并不是采用单一FPGA裸片结构，而是包含多个FPGA裸片，这多个FPGA裸片均层叠设置在同一个硅连接层2上。这多个FPGA裸片可以在硅连接层2上沿着一维方向排布，如图2所示的俯视图。也可以在硅连接层2上按照二维堆叠方式排布，也即在水平面上沿着横、纵两个方向排布，如图3所示，这多个FPGA裸片在硅连接层2可以合理布局，根据各个FPGA裸片的形状和面积紧凑排布在硅连接层2上使得整个FPGA的整体面积较小且裸片之间的互连性能较好。
本申请对FPGA裸片的内部结构以及FPGA裸片与硅连接层2的连接方式 进行了调整和精心设计。接下来，本申请对FPGA裸片与硅连接层2之间的具体连接结构以及实现方式进行介绍：
本申请中的FPGA裸片与常规FPGA裸片有所不同，常规FPGA裸片有多种功能的可配置功能模块组成，常见的可配置功能模块主要包括可编程逻辑单元(CLB或PLBs)和输入输出端口(IOB)，有时还包括一些其他功能模块，比如BRAM、DSP、PC等。每个可配置功能模块具有一个结构相同的环于该可配置功能模块分布的互连资源模块(INT)，各个可配置功能模块之间的水平或垂直连线皆经由INT模块相连。而本申请中的FPGA裸片在该常规结构的基础上，除了包含CLB、IOB和其他功能模块这些常规可配置功能模块之外，还包括根据裸片间信号互连需求专门在裸片内部设计的硅堆叠连接模块，每个硅堆叠连接模块内包括若干个硅堆叠连接点3，硅堆叠连接模块是一种新增的专用于裸片信号引出的可配置功能模块，本申请中的FPGA裸片是将常规FPGA裸片中的某些常规可配置功能模块替换设置成了硅堆叠连接模块。且根据信号互连需求可以对任意位置的常规可配置功能模块进行替换，比如针对现有常规的Column-Based的FPGA架构为例，既可以将硅堆叠连接模块设置在可编程逻辑单元所在的行列结构中，也可以将硅堆叠连接模块设置在其他功能模块所在的行列结构中以得到本申请中的FPGA裸片。
本申请中的FPGA裸片中的每个硅堆叠连接模块也具有一个环于该硅堆叠连接模块分布的互连资源模块，因此本申请中的FPGA裸片的绕线结构可以与常规FPGA裸片保持一致，无需做改变。硅堆叠连接模块与其他各个可配置功能模块之间的水平或垂直连线皆经由INT模块相连，硅堆叠连接模块LNK直接与其对应的互连资源模块INT中的互连开关相连，是互连线的一部分。硅堆叠连接模块LNK与互连开关之间根据连通度需要可以是全互连或部分互连。
本申请中的FPGA裸片还包括与内部硅堆叠连接点3对应的连接点引出端4，FPGA裸片内的硅堆叠连接点3通过重布线层(RDL层)内的顶层金属线5与相应的连接点引出端4相连，需要说明的是，图2和3为了示意硅堆叠连接点3和连接点引出端4的连接关系将两者展示在同一平面上，但请参考图1，硅堆叠连接点3和连接点引出端4实际是处于不同平面的。连接点引出端4通常根据堆叠互连需要沿着第一方向和第二方向按行列结构布设。另外为了实现更高的连通带宽可以布设多行/多列连接点引出端4，也即每个FPGA裸片中沿着第一方向布设有若干行连接点引出端4，和/或，沿着第二方向布设有若干列 连接点引出端4，从而实现多行多列的高效二维级联。沿着每个方向布设多行/多列连接点引出端4时，可以是间隔均匀布设，也可以是随机布设。
本申请中的FPGA裸片内形成有第一电路结构，第一电路结构可以是模拟电路、数字电路以及模数混合电路等。第一电路结构可以基于FPGA裸片内部的可编程逻辑单元构建形成，构建形成第一电路结构的可编程逻辑单元包括CLB、BRAM和DSP中的至少一种。且进一步的，用于构建形成第一电路结构的可编程逻辑单元可由所在的FPGA裸片的动态可编程端口进行动态配置。
第一电路结构的端口通过互连资源模块也连接到相应的硅堆叠连接点3后通过重布线层内的顶层金属线5连接到相应的连接点引出端4。图1仅示出了裸片1内部的第一电路结构，实际多个FPGA裸片内都可以存在相同或不同的第一电路结构。
硅连接层2内布设有跨裸片连线6，FPGA裸片与可编程逻辑单元相连的连接点引出端4通过硅连接层2内的跨裸片连线6即可连接到其他FPGA裸片中相应的连接点引出端4，实现FPGA裸片之间的互连。且由于跨裸片连线6分层布置互不影响，连线跨度和方向都可灵活布设，因此每个FPGA裸片可通过硅连接层2内的跨裸片连线6与其他任意一个FPGA裸片相连。比如在图2中裸片1可以与相邻的裸片2相连，也可以与间隔的裸片3相连。再比如在图3中，裸片4可以与同行的裸片5相连，也可以与同列的裸片6相连，也可以与不同行且不同列的裸片7相连。连接点引出端4与硅连接层2的连接方式具体可以是：FPGA裸片上生长有微凸球，连接点引出端4通过微凸球与硅连接层2连接并通过硅连接层2内部的跨裸片连线6连接至其他FPGA裸片，图1可以看出FPGA裸片底部的微凸球结构，本申请不再详细标示。FPGA裸片内的输入输出端口通过硅连接层2上的硅通孔7连接至基板1。
本申请中的硅连接层2为有源硅连接层，硅连接层2内除了布设有跨裸片连线6之外，还布设有第二电路结构，第二电路结构为模拟电路、包括若干个模拟电路元件。硅连接层2上的输入输出端口也连接至基板1。第二电路结构具体可以实现为多种电路结构，主要有如下三类：
1、第二电路结构是FPGA裸片内不易实现的电路结构。受限于芯片面积和加工难度，FPGA裸片内的某些模拟电路元件往往只能做到较小的电路参数规格，而本申请可以将这些电路参数规格受限的模拟电路元件布设在硅连接层2上以达到较大的电路参数规格，因此硅连接层2上的第二电路结构的电路参数 规格大于预定参数规格，该预定参数规格为相同电路结构在FPGA裸片内可实现的最大电路参数规格。这一类模拟电路元件主要有电容和电感：
当为电容器件时，可以由NMOS管实现，第二电路结构包括的电容器件的电容量大于电容量预定参数规格，该电容量预定参数规格是FPGA裸片内可实现的最大电容量。常规的FPGA裸片内的电容通常大小只能在pF级，而本申请第二电路结构中的电容器件的电容量可以达到uF以上级别。比如常规的应用如图4所示，在电源接口VCC处连接电容器件并接地GND可以实现供电降噪滤波的作用，无需外部封装电容，减小封装尺寸。
当为电感器件时，通过硅连接层2上的绕线实现，如图5所示。第二电路结构包括的电感器件的电感量大于电感量预定参数规格，电感量预定参数规格是FPGA裸片内可实现的最大电感量。常规的FPGA裸片内的电感通常大小只能在nH级，而本申请第二电路结构中的电感器件的电感量可以达到100nH以上级别。
2、第二电路结构是规模较大、占用面积较大的电路结构，也即第二电路结构的电路尺寸大于预定尺寸，该预定尺寸为预设的参数。这一类第二电路结构包括电阻器件、双极性晶体管、运算放大器、锁相环、延迟锁相环、振荡器和射频采集电路中的至少一种。这一类大尺寸的电路结构布设在硅连接层内，可以有效减少FPGA裸片的面积，并提高数字逻辑规模。
比如第二电路结构可以是LVDS的终端匹配电阻。
比如第二电路结构可以是锁相环，如图3所示，由鉴相鉴频器、低通滤波器、压控振荡器和分频器构成锁相环，参考时钟经过该锁相环输入FPGA裸片。
比如第二电路结构可以是射频采集电路，则此时可以快速实现支持射频直采的FPGA产品，使得FPGA产品具有低功率、高可靠的优势。
3、第二电路结构是对加工工艺要求较低的电路结构，第二电路结构对工艺水平的需求低于预定工艺水平，该预定工艺水平为一个预定的衡量指标。硅连接层和FPGA裸片采用不同的工艺节点，FPGA裸片采用的工艺节点优于硅连接层采用的工艺节点，通常FPGA裸片采用最先进的工艺节点，以提高逻辑资源规模和***工作频率，而硅连接层的工艺节点则较低，因此可以将对加工工艺要求较低的电路结构布设在硅连接层，提高加工效率。不同元件对工艺水平度需求为业内公知，常见的对加工工艺要求较低的第二电路结构具体可以是电阻、电感、电容等，本申请不详细赘述。
FPGA裸片内与第一电路结构的端口相连的连接点引出端4通过硅连接层内的硅连接层连线连接到第二电路结构的端口，第一电路结构和第二电路结构相连形成多裸片FPGA内部的完整的内置模拟电路。需要说明的是，跨裸片连线连接在FPGA裸片之间，硅连接层连线连接在FPGA裸片和第二电路结构之间，本申请为了对两者的连接关系进行区分才使用了两个不同的名称，但硅连接层连线和跨裸片连线一样实际均为金属线，所以附图中未再单独对硅连接层连线进行标注。
根据第一电路结构和第二电路结构的电路不同，多裸片FPGA内部在形成内置模拟电路时，主要可以概括为如下几种情况，多裸片FPGA内部的内置模拟电路主要包括模拟部分和对应所需的数字部分。
(1)内置模拟电路的模拟部分均布设在硅连接层，也即模拟部分仅由第二电路结构实现。
(2)内置模拟电路的模拟部分一部分布设在硅连接层、一部分布设在FPGA裸片内，此时该多裸片FPGA中至少一个FPGA裸片内形成的第一电路结构为模拟电路，硅连接层内的第二电路结构与至少一个FPGA裸片内的第一电路结构共同形成为模拟部分。
(3)内置模拟电路的模拟部分一部分布设在硅连接层、一部分布设在其他裸片内，此时多裸片FPGA还包括层叠设置在硅连接层上的其他裸片，其他裸片内部形成模拟电路结构的第三电路结构，其他裸片的结构与本申请中的FPGA裸片的结构类似，都包含硅堆叠连接模块。第三电路结构的端口连接到相应的硅堆叠连接点后通过重布线层内的顶层金属线连接到相应的连接点引出端、并通过硅连接层内的硅连接层连线连接到第二电路结构的端口，与第一电路结构连接到第二电路结构的方式类似，本申请不再赘述，结构示意图请参考图6，裸片4为FPGA裸片，除此之外，硅连接层2上还布设其他裸片。则此时，第三电路结构与第一电路结构和第二电路结构相连形成多裸片FPGA内部的内置模拟电路。在这种情况中，硅连接层内的第二电路结构与其他裸片内的第三电路结构共同形成为模拟部分。
在这种情况中，多裸片FPGA内部包括一个或多个其他裸片，每个其他裸片内部的第三电路结构通过硅连接层内的硅连接层连线相连形成规模更大的第三电路结构。
(4)内置模拟电路的模拟部分一部分布设在硅连接层、一部分布设在其他 裸片内、另一部分布设在FPGA裸片内，这种情况可以看做是上述情况(2)和(3)的结合，实现方式类似，本申请不再赘述。
在上述4种情况中，内置模拟电路的数字部分均布设在硅连接层，或者，数字部分布设在至少一个FPGA裸片内，或者，数字部分布设硅连接层和至少一个FPGA裸片内。当内置模拟电路的数字部分布设在至少一个FPGA裸片内时，该多裸片FPGA中至少一个FPGA裸片内形成的第一电路结构为数字电路。比较特殊的，在上述情况(2)、(3)、(4)中，由于模拟部分也会布设在FPGA裸片内，而数字部分也会布设在FPGA裸片内，因此该多裸片FPGA中至少一个FPGA裸片内形成的第一电路结构为模数混合电路，FPGA裸片内的模数混合电路一方面与硅连接层内的第二电路结构共同形成为模拟部分、另一方面也共同形成数字部分。
无论第二电路结构具体为何种电路结构，第一电路结构的端口和第二电路结构的端口之间传输的可能是模拟信号、数字信号和差分信号中的任意一种：
当第一电路结构的端口和第二电路结构的端口之间传输的是模拟信号时，第一电路结构的端口直接通过硅连接层连线连接到第二电路结构的端口，也即通过金属线直连。
当第一电路结构的端口和第二电路结构的端口之间传输的是数字信号时，第一电路结构的端口与第二电路结构的端口之间的硅连接层连线上还设置有缓冲器BUF，BUF通常也布设在硅连接层中。
当第一电路结构的端口和第二电路结构的端口之间传输差分信号时，则第一电路结构的端口包括第一差分口和第二差分口，第二电路结构的端口也包括第一差分口和第二差分口，两个第一差分口对应连接、两个第二差分口对应连接，且两个第一差分口之间的信号线与两个第二差分口之间的信号线完全相同。两个差分口之间的信号线包括第一电路结构的差分口-硅堆叠连接点-连接点引出端-第二电路结构的差分口之间的各段线路。完全相同表示必须全程Matched，具有相同布线、形状、距离和接口。
另外，本申请中的第二电路结构的电路参数可由该多裸片FPGA内部的配置电路调节配置，该配置电路为FPGA裸片内部的配置链，或者，为FPGA裸片内部的动态可重配端口。同样的，
以上所述的仅是本申请的优选实施方式，本发明不限于以上实施例。可以理解，本领域技术人员在不脱离本发明的精神和构思的前提下直接导出或联想 到的其他改进和变化，均应认为包含在本发明的保护范围之内。

Claims (17)

  1. 一种利用有源硅连接层实现内置模拟电路的多裸片FPGA，其特征在于，所述多裸片FPGA包括基板、层叠设置在所述基板上的硅连接层以及层叠设置在所述硅连接层上的若干个FPGA裸片，所述硅连接层覆盖所有的FPGA裸片；
    每个FPGA裸片内包括若干个可配置功能模块、环于各个可配置功能模块分布的互连资源模块以及连接点引出端，所述FPGA裸片内的可配置功能模块至少包括可编程逻辑单元、硅堆叠连接模块和输入输出端口，所述硅堆叠连接模块内包括若干个硅堆叠连接点，所述FPGA裸片内的可编程逻辑单元分别与硅堆叠连接点和输入输出端口通过互连资源模块相连，所述硅堆叠连接点通过重布线层内的顶层金属线与相应的连接点引出端相连；每个FPGA裸片中的连接点引出端通过所述硅连接层内的跨裸片连线与其他FPGA裸片中相应的连接点引出端相连，每个FPGA裸片可通过所述硅连接层内的跨裸片连线与其他任意一个FPGA裸片相连；FPGA裸片内的输入输出端口通过所述硅连接层上的硅通孔连接至所述基板；
    所述FPGA裸片内形成有第一电路结构，所述第一电路结构的端口通过所述互连资源模块连接到相应的硅堆叠连接点后通过重布线层内的顶层金属线连接到相应的连接点引出端；
    所述硅连接层内布设有第二电路结构，所述第二电路结构包括若干个模拟电路元件，所述FPGA裸片上与所述第一电路结构的端口相连的连接点引出端通过所述硅连接层内的硅连接层连线连接到所述第二电路结构的端口，所述第一电路结构和所述第二电路结构相连形成所述多裸片FPGA内部的内置模拟电路，所述硅连接层上的输入输出端口也连接至所述基板。
  2. 根据权利要求1所述的多裸片FPGA，其特征在于，
    所述第二电路结构的电路参数规格大于预定参数规格，所述预定参数规格为相同电路结构在FPGA裸片内可实现的最大电路参数规格。
  3. 根据权利要求2所述的多裸片FPGA，其特征在于，
    所述第二电路结构包括电容器件，所述电容器件的电容量大于电容量预定参数规格，所述电容量预定参数规格是FPGA裸片内可实现的最大电容量，所述电容器件的电容量达到uF以上级别。
  4. 根据权利要求2所述的多裸片FPGA，其特征在于，所述第二电路结构包括电感器件，所述电感器件通过所述硅连接层上的绕线实现，所述电感器件的电感量大于电感量预定参数规格，所述电感量预定参数规格是FPGA裸片内可实现的最大电感量，所述电感器件的电感量达到100nH以上级别。
  5. 根据权利要求1所述的多裸片FPGA，其特征在于，所述第二电路结构的电路尺寸大于预定尺寸。
  6. 根据权利要求5所述的多裸片FPGA，其特征在于，所述第二电路结构包括电阻器件、双极性晶体管、运算放大器、锁相环、延迟锁相环、振荡器和射频采集电路中的至少一种。
  7. 根据权利要求1所述的多裸片FPGA，其特征在于，
    所述硅连接层和FPGA裸片采用不同的工艺节点，FPGA裸片采用的工艺节点优于所述硅连接层采用的工艺节点，则所述第二电路结构对工艺水平的需求低于预定工艺水平。
  8. 根据权利要求1-7任一所述的多裸片FPGA，其特征在于，
    所述第一电路结构的端口和所述第二电路结构的端口之间传输模拟信号时，所述第一电路结构的端口直接通过硅连接层连线连接到所述第二电路结构的端口。
  9. 根据权利要求1-7任一所述的多裸片FPGA，其特征在于，
    所述第一电路结构的端口和所述第二电路结构的端口之间传输数字信号时，所述第一电路结构的端口与所述第二电路结构的端口之间的硅连接层连线上还设置有缓冲器。
  10. 根据权利要求1-7任一所述的多裸片FPGA，其特征在于，所述第一电路结构的端口和所述第二电路结构的端口之间传输差分信号时，则所述第一电路结构的端口包括第一差分口和第二差分口，所述第二电路结构的端口也包括第一差分口和第二差分口，两个第一差分口对应连接、两个第二差分口对应连接，且两个第一差分口之间的信号线与两个第二差分口之间的信号线完全相同。
  11. 根据权利要求1-7任一所述的多裸片FPGA，其特征在于，所述多裸片FPGA中至少一个FPGA裸片内形成的第一电路结构为数字电路，和/或，至少一个FPGA裸片内形成的第一电路结构为模拟电路，和/或，至少一个FPGA裸片内形成的第一电路结构为模数混合电路。
  12. 根据权利要求1-7任一所述的多裸片FPGA，其特征在于，所述多裸片FPGA还包括层叠设置在所述硅连接层上的其他裸片，所述其他裸片内部形成模拟电路结构的第三电路结构，所述第三电路结构的端口连接到相应的硅堆叠连接点后通过重布线层内的顶层金属线连接到相应的连接点引出端、并通过所述硅连接层内的硅连接层连线连接到所述第二电路结构的端口；所述第三电路结构与所述第一电路结构和所述第二电路结构相连形成所述多裸片FPGA内部的内置模拟电路。
  13. 根据权利要求1-7任一所述的多裸片FPGA，其特征在于，所述第二电路结构的电路参数由所述多裸片FPGA内部的配置电路调节配置。
  14. 根据权利要求13所述的多裸片FPGA，其特征在于，所述多裸片FPGA内部的配置电路为FPGA裸片内部的配置链。
  15. 根据权利要求13所述的多裸片FPGA，其特征在于，所述多裸片FPGA内部的配置电路为FPGA裸片内部的动态可重配端口。
  16. 根据权利要求1-7任一所述的多裸片FPGA，其特征在于，所述第一电路结构基于所述FPGA裸片内的可编程逻辑单元构建形成，构建形成所述第一电路结构的可编程逻辑单元包括CLB、BRAM和DSP中的至少一种。
  17. 根据权利要求16所述的多裸片FPGA，其特征在于，用于构建形成所述第一电路结构的可编程逻辑单元由所在的FPGA裸片的动态可编程端口进行动态配置。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582412A (zh) * 2008-05-12 2009-11-18 台湾积体电路制造股份有限公司 输入/输出垫结构
US20100148316A1 (en) * 2008-12-11 2010-06-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Topside and Bottom-side Interconnect Structures Around Core Die with TSV
CN102446883A (zh) * 2011-12-12 2012-05-09 清华大学 一种通用封装基板、封装结构和封装方法
CN103681618A (zh) * 2012-09-20 2014-03-26 国际商业机器公司 具有通孔的功能性玻璃处理晶片
US20160358889A1 (en) * 2015-06-03 2016-12-08 Apple Inc. Dual molded stack tsv package
CN108352378A (zh) * 2015-10-16 2018-07-31 赛灵思公司 无中介层的叠式裸片互连
CN111753478A (zh) * 2020-07-01 2020-10-09 无锡中微亿芯有限公司 利用有源硅连接层实现内置模拟电路的多裸片fpga

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6917219B2 (en) * 2003-03-12 2005-07-12 Xilinx, Inc. Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice
US8476735B2 (en) * 2007-05-29 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Programmable semiconductor interposer for electronic package and method of forming
US7973555B1 (en) * 2008-05-28 2011-07-05 Xilinx, Inc. Configuration interface to stacked FPGA
US9064715B2 (en) * 2010-12-09 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Networking packages based on interposers
US8546955B1 (en) * 2012-08-16 2013-10-01 Xilinx, Inc. Multi-die stack package
US9319148B2 (en) * 2012-10-01 2016-04-19 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Optical interconnection to an integrated circuit
US9106229B1 (en) * 2013-03-14 2015-08-11 Altera Corporation Programmable interposer circuitry
US20150109024A1 (en) * 2013-10-22 2015-04-23 Vaughn Timothy Betz Field Programmable Gate-Array with Embedded Network-on-Chip Hardware and Design Flow
KR102381158B1 (ko) * 2016-08-15 2022-03-30 자일링크스 인코포레이티드 적층형 실리콘 상호 연결(ssi) 기술 통합을 위한 독립형 인터페이스
US10431575B2 (en) * 2017-12-19 2019-10-01 Nxp B.V. Multi-die array device
US10812085B2 (en) * 2018-12-27 2020-10-20 Intel Corporation Power management for multi-dimensional programmable logic devices
CN110739135B (zh) * 2019-10-29 2021-02-02 电子科技大学 一种基于电感可调的变压器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582412A (zh) * 2008-05-12 2009-11-18 台湾积体电路制造股份有限公司 输入/输出垫结构
US20100148316A1 (en) * 2008-12-11 2010-06-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Topside and Bottom-side Interconnect Structures Around Core Die with TSV
CN102446883A (zh) * 2011-12-12 2012-05-09 清华大学 一种通用封装基板、封装结构和封装方法
CN103681618A (zh) * 2012-09-20 2014-03-26 国际商业机器公司 具有通孔的功能性玻璃处理晶片
US20160358889A1 (en) * 2015-06-03 2016-12-08 Apple Inc. Dual molded stack tsv package
CN108352378A (zh) * 2015-10-16 2018-07-31 赛灵思公司 无中介层的叠式裸片互连
CN111753478A (zh) * 2020-07-01 2020-10-09 无锡中微亿芯有限公司 利用有源硅连接层实现内置模拟电路的多裸片fpga

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