CN110010510A - 多管芯阵列装置 - Google Patents
多管芯阵列装置 Download PDFInfo
- Publication number
- CN110010510A CN110010510A CN201811560243.5A CN201811560243A CN110010510A CN 110010510 A CN110010510 A CN 110010510A CN 201811560243 A CN201811560243 A CN 201811560243A CN 110010510 A CN110010510 A CN 110010510A
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- Prior art keywords
- tube core
- flip chip
- die panel
- embedded die
- chip tube
- Prior art date
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Abstract
本发明提供各种实施例,包括制造多管芯封装的方法,所述方法包括:将多个倒装芯片管芯和分离器管芯放置在牺牲载体上;执行焊料回焊以将每个倒装芯片管芯和每个分离器管芯的焊料凸块接合到包括测试探针电路的所述牺牲载体;测试所述倒装芯片管芯和所述分离器管芯;替换任何故障管芯;将所述倒装芯片管芯和所述分离器管芯在所述牺牲载体上包覆成型以形成嵌入式管芯面板;将所述嵌入式管芯面板平坦化以暴露所述嵌入式管芯的背表面;跨越所述嵌入式管芯面板的所述背表面形成金属化层;以及移除所述牺牲载体以暴露所述嵌入式管芯面板的前表面,其中每个倒装芯片管芯和分离器管芯的每个焊料凸块的接触表面暴露于所述前表面中。
Description
技术领域
本公开大体上涉及无线通信,且更具体地说,涉及提供封装半导体装置,所述封装半导体装置包括被配置成控制用于无线通信的天线阵列的多管芯阵列。
背景技术
无线通信用于各种数据传送应用中,例如移动电话服务。无线通信已在例如通过转向包括多输入多输出(multi-in,multi-out;MIMO)和毫米波(mmWaves)来增加所传送数据量方面取得进展。
发明内容
根据本发明的第一方面,提供一种用于制造多管芯封装的方法,所述方法包括:
将多个倒装芯片管芯和多个分离器管芯放置在牺牲载体上,每个倒装芯片管芯和每个分离器管芯以有源侧向下朝向定位于所述牺牲载体上;
执行焊料回焊以将每个倒装芯片管芯和每个分离器管芯的焊料凸块接合到所述牺牲载体,其中所述牺牲载体包括测试探针电路;
使用所述测试探针电路在探针测试中测试所述多个倒装芯片管芯和所述多个分离器管芯;
如由所述测试指示替换任何故障倒装芯片管芯和任何故障分离器管芯;
将所述多个倒装芯片管芯和所述多个分离器管芯在所述牺牲载体上包覆成型以形成嵌入式管芯面板;
将所述嵌入式管芯面板平坦化以使每个倒装芯片管芯和每个分离器管芯的背表面暴露于所述嵌入式管芯面板的背表面中;
跨越所述嵌入式管芯面板的背表面形成金属化层,所述金属化层接触每个倒装芯片管芯和每个分离器管芯的所述背表面;以及
移除所述牺牲载体以暴露所述嵌入式管芯面板的前表面,其中每个倒装芯片管芯和每个分离器管芯的每个焊料凸块的接触表面暴露于所述嵌入式管芯面板的所述前表面中。
在一个或多个实施例中,所述移除所述牺牲载体包括:
研磨掉所述牺牲载体。
在一个或多个实施例中,所述牺牲载体包括玻璃载体。
在一个或多个实施例中,所述方法进一步包括:
将胶带附接到所述金属化层;
在移除所述牺牲载体之后,平坦化以暴露所述嵌入式管芯面板的新前表面,其中每个焊料凸块的新接触表面暴露于所述嵌入式管芯面板的所述新前表面中。
在一个或多个实施例中,所述将所述嵌入式管芯面板平坦化包括:
从每个倒装芯片管芯和每个分离器管芯移除背侧部分以暴露每个倒装芯片管芯和每个分离器管芯的所述背表面。
在一个或多个实施例中,所述包覆成型进一步包括:
用底部填充材料对每个倒装芯片管芯与所述牺牲载体之间的空间进行底部填充。
在一个或多个实施例中,所述方法进一步包括:
在移除所述牺牲载体之后,对所述嵌入式管芯面板的所述前表面执行激光移除,以从每个倒装芯片管芯的每个凸起侧面上的射频(RF)敏感区移除所述底部填充材料。
在一个或多个实施例中,每个倒装芯片管芯包括靠近每个倒装芯片管芯的凸起侧面的射频(RF)收发器。
在一个或多个实施例中,每个分离器管芯被配置成在传输模式期间在第一端口处接收射频(RF)信号并在第二端口和第三端口处输出所述RF信号,且被配置成在接收模式期间在所述第一端口处组合所述第二端口和所述第三端口上的RF信号。
在一个或多个实施例中,所述多管芯封装被配置成附接到印刷电路板(PCB),其中所述PCB包括:
多个天线,其中所述多管芯封装的每个倒装芯片管芯被配置成连接到所述多个天线的子组,和
多个射频(RF)信号线,其被配置成在所述多个倒装芯片管芯与所述多个分离器管芯之间提供信号连接。
根据本发明的第二方面,提供一种用于制造多管芯封装的方法,所述方法包括:
通过胶带将多个倒装芯片管芯附接到临时载体,每个所述倒装芯片管芯以有源侧向下朝向定位于所述临时载体上;
将所述多个倒装芯片管芯在所述临时载体上包覆成型以形成嵌入式管芯面板;
移除所述临时载体和胶带以暴露所述嵌入式管芯面板的前表面,其中在移除所述临时载体和胶带之后暴露每个倒装芯片管芯的有源侧;
在所述嵌入式管芯面板的所述前表面上方形成重布层(RDL)结构,其中所述RDL结构包括连接到每个倒装芯片管芯的所述有源侧的迹线;
将所述嵌入式管芯面板平坦化以使每个倒装芯片管芯的背表面暴露于所述嵌入式管芯面板的背表面中;以及
跨越所述嵌入式管芯面板的所述背表面形成金属化层,所述金属化层接触每个倒装芯片管芯的所述背表面。
在一个或多个实施例中,所述方法进一步包括:
将多个焊球放置在所述RDL结构中的接触焊垫上。
在一个或多个实施例中,所述方法进一步包括:
对所述RDL结构执行激光移除,以从每个倒装芯片管芯的每个凸起侧面上的射频(RF)敏感区移除所述RDL结构的一部分。
在一个或多个实施例中,所述将所述嵌入式管芯面板平坦化包括:
从每个倒装芯片管芯移除背侧部分以暴露每个倒装芯片管芯的所述背表面。
在一个或多个实施例中,所述方法进一步包括:
以有源侧向下朝向将所述多个倒装芯片管芯之间的多个分离器管芯放置在所述临时载体上,其中
在所述包覆成型之后,所述多个分离器管芯也包括在所述嵌入式管芯面板中。
在一个或多个实施例中,所述多管芯封装被配置成附接到印刷电路板(PCB),其中所述PCB包括:
多个天线,其中所述多管芯封装的每个倒装芯片管芯被配置成连接到所述多个天线的子组,和
多个射频(RF)信号线,其被配置成在所述多个倒装芯片管芯与所述多个分离器管芯之间提供信号连接。
在一个或多个实施例中,所述RDL结构进一步包括:
多个射频(RF)信号线,其在所述多个倒装芯片管芯与所述多个分离器管芯之间提供信号连接。
在一个或多个实施例中,所述多管芯封装被配置成附接到印刷电路板(PCB),其中所述PCB包括:
多个天线,其中所述嵌入式管芯面板的每个倒装芯片管芯被配置成连接到所述多个天线的子组。
在一个或多个实施例中,所述RDL结构进一步包括:
在所述多个倒装芯片管芯之间的多个分离器电路;和
多个射频(RF)信号线,其在所述多个倒装芯片管芯与所述多个分离器电路之间提供信号连接。
在一个或多个实施例中,所述方法进一步包括:
将热界面材料(TIM)的第一侧附接到所述嵌入式管芯面板的所述金属化层,其中所述TIM的第二侧被配置成附接到包括散热管的冷却***。
本发明的这些和其它方面将根据下文中所描述的实施例显而易见,且参考这些实施例予以阐明。
附图说明
通过参考附图,可以更好地理解本发明,并且使得本领域的技术人员清楚本发明的多个目的、特征和优点。
图1、2、3和4是描绘根据本公开的一些实施例的耦合到多个天线的示例性射频(RF)单元的组件的框图。
图5、6A和6B是描绘根据本公开的一些实施例的RF单元的示例性阵列的框图。
图7和8是描绘根据本公开的一些实施例的RF单元的另一示例性阵列的框图。
图9A到9I是描绘根据本公开的一些实施例的产生包括RF单元阵列的封装半导体装置的示例性工艺流程的框图。
图10是描绘根据本公开的一些实施例的在示例性封装半导体装置与包括天线阵列的印刷电路板(PCB)之间的界面的框图。
图11A到11I是描绘根据本公开的一些实施例的产生包括RF单元阵列的封装半导体装置的另一示例性工艺流程的框图。
图12是描绘根据本公开的一些实施例的在另一示例性封装半导体装置与包括天线阵列的印刷电路板(PCB)之间的界面的框图。
图13、14和15是描绘根据本公开的一些实施例的示例性封装半导体装置的近视图的框图。
图16和17是描绘根据本公开的一些实施例的在封装半导体装置的额外例子与包括天线阵列的印刷电路板(PCB)之间的界面的框图。
图18是描绘根据本公开的一些实施例的附接到PCB的示例性封装半导体装置的框图。
本发明借助于例子来进行说明且不受附图限制,在附图中,除非另外指出,否则相似的附图标记指示类似的元件。图式中的元件为简单和清楚起见而示出并且不必按比例绘制。
具体实施方式
以下内容阐述旨在说明本发明的各种实施例的详细描述,且不应视为限制性的。
概述
MIMO(多输入多输出)技术是用于实施先进无线通信,例如用于实施5G(第5代)网络的重要技术。天线阵列用于实现大量数据传送,其中天线受射频(RF)管芯的数目控制。随着以阵列实施的天线的数目增加,无线通信装置中所需的RF管芯的数目也增加。然而,总的来说,RF管芯产生大量热,且需要热转移解决方案。无线通信装置的热性能是当前在单一无线通信装置中实施的RF管芯的数目的限制因素,这一限制因素又限制了无线通信装置的数据传送能力。
另外,客户照惯例将每个RF管芯单独地附接在印刷电路板(PCB)上以形成无线通信装置。随着在此类装置中实施的RF管芯的数目增加,RF管芯当中产生非平面性的风险也增加。举例来说,每个RF管芯在附接到PCB时可能具有一定倾斜度或焊料凸块高度变化。RF管芯的非平面性可能会限制从每个RF管芯的(非平面)侧面到散热器或散热片的平面表面的热转移。虽然此类倾斜或变化可以用厚的热界面材料补偿,但是较大厚度增大了从RF管芯到散热器的导热路径且降低了热性能。
本公开提供封装半导体装置的实施例和制造包括RF管芯阵列的此类装置的实施例,所述RF管芯阵列可包括数百管芯。本发明所公开的装置具有有源表面,所述有源表面被配置成直接附接到实施天线阵列的印刷电路板(PCB)。有源表面为可以通过焊料凸块、焊球或其它焊接附接机构附接到PCB的平面表面。所述装置还具有平面背表面,所述平面背表面可以接合到冷却***,例如散热管或其它热转移机构,其中每个RF管芯的薄化背侧暴露于平面背表面中。直接导热路径形成于每个管芯与冷却***之间,以耗散本发明所包括的RF管芯中的更多功率从而提高热性能,这也增加了本发明所公开的装置的使用期限(例如,由较低操作温度引起)。提高的热性能也可以使额外RF管芯包括在本发明所公开的装置中,以提供增加的RF功率容量。
在本文中所描述的制造工艺的一些实施例中,具有测试电路的牺牲载体用于在执行包覆成型之前测试管芯,从而允许在包覆成型之前检测并替换任何故障管芯,这提高了所得装置的良率和可靠性。在一些实施例中,可以从每个RF管芯上的RF敏感区移除任意介电材料(例如模塑化合物、底层填充物或介电质RDL层),从而提供提高的RF性能。在一些实施例中,制造工艺也可以在装置中形成导电迹线或信号线,以使PCB与装置之间的转变数降至最低从而提高RF性能。
本公开可尤其有利于实施呈微波频率或毫米波频率(或具有毫米波长的频率)的操作频率的装置。本文中所公开的封装半导体装置可以在无线通信装置(例如路由器、用于蜂窝电话***的基站、实施无线通信(例如,5G)的网络装置及其类似者)中实施。
示例性实施例
图1示出示例性射频(RF)单元100,所述射频(RF)单元100包括被配置成在具有波长或拉姆达(λ)的操作频率下处理RF信号的RF管芯102。操作频率的例子包括但不限于通常落在20kHz到300GHz的范围中的频率,例如以13.56MHz为中心的频带、以3.6GHz为中心的频带、以5GHz为中心的频带或以60GHz为中心的频带。RF管芯102可包括RF前端电路,其实施如下文结合图2进一步论述的传输器、接收器或所述两者的前端组件。
图2示出也被称为装芯片管芯的RF管芯102的背侧202、有源侧204和横向侧210,所述倒装芯片管芯被配置成在面向下的朝向(例如,面向PCB的有源侧)上连接到PCB或其它基板。RF管芯102的有源侧204包括具有路由到在有源侧204上的接合焊垫的信号路径的有源电路,且背侧202(例如,块状硅)与有源侧204相对。在示出的实施例中,多个焊料凸块206附接到在有源侧204上的接合焊垫。虽然示出了焊料凸块206附接到围绕管芯102的外周成行布置的接合焊垫,但是焊料凸块206可以附接到布置成其它形状且布置于管芯102上的其它区域中的接合焊垫。有源电路还包括在图2中以虚线轮廓示出的RF敏感区208。RF敏感区208可包括前端电路(也以虚线轮廓示出),所述前端电路包括传输器电路、接收器电路或所述两者作为收发器电路。前端电路可包括但不限于传输器功率放大器、接收器低噪声放大器、一或多个平衡-不平衡转换器、一或多个滤波器、循环器或其它天线耦合装置、阻抗匹配元件、本机振荡器、锁相环路、谐振频率电路(例如,一或多个电阻器和电容器)、控制逻辑和其它适当的前端元件。
返回到图1,RF单元100的RF管芯102通过接触一个焊料凸块206的相应互连件106耦合到一组天线104,其中RF管芯102可将RF信号提供到每个天线104以供传输(例如,由区域208中的传输器电路输出),可从每个天线104接收RF信号(例如,输入到区域208中的接收器电路),或这两种情况。在本文中所论述的实施例中,该组天线104包括4个天线,但在其它实施例中可以实施其它数目的天线(例如,2个、6个、8个)。RF管芯102可以被配置成实施使用多个传输和接收天线进行多路径传播的MIMO(多输入多输出)技术。在本文中所论述的实施例中,天线104在RF管芯102所附接到的印刷电路板(PCB)或其它载体上实施,如图4中进一步所论述。在图1中示出的实施例中,每个天线104是具有基于操作频率的波长(λ)的侧面尺寸108的正方形贴片天线,且可将RF信号通过其传输或接收的PCB的介电常数纳入考虑。侧面尺寸108的例子包括但不限于一拉姆达(λ)、二分之一拉姆达(λ/2)、四分之一拉姆达(λ/4)、四分之三拉姆达(3λ/4)或四拉姆达(4λ)长度。在下文结合图3进一步论述天线104。
图3示出示例性矩形天线104,所述矩形天线104具有宽度108和长度308。在一些实施例中,宽度108等于长度308以提供正方形贴片天线,但在其它实施例中,宽度108可以不同于长度308。在其它实施例中,天线104可以是圆形的、椭圆形的或具有连续区域的无定形形状。天线104通过具有宽度304的微带传输线302附接到互连件106。微带302可以通过使微带302与周围的天线104分离的间隙的尺寸(例如间隙间距312和间隙的长度310)调谐或匹配到天线104。在一些实施例中,天线104可为四分之一波长的元件,且将PCB中的接地平面用作低架地网(counterpoise)以形成半波偶极子。
图4示出RF管芯102、互连件106和天线104的示例性分解图。如本文中所论述,互连件106和天线104实施于印刷电路板(PCB)402中,所示出的所述PCB 402没有中间介电层。在一些实施例中,每个天线104可以与被配置成将RF信号反射到天线104的反射器404对准,以提高天线104的谐振。反射器404具有比天线104大的厚度。尽管未示出,但接地平面也可以在PCB中的天线104上方或下方实施,或接地元件可以在PCB中的每个天线104之间实施。PCB包括在由介电层或层压板形成的非导电基板上的导电特征(例如着陆焊垫)。PCB可为使用聚酰亚胺的柔性类型PCB或使用FR4或BT树脂的刚性类型PCB,或其组合。
返回到图1,该组天线104以在行方向上(例如,在页面的左右方向上)具有间距110且在列方向上(例如,在页面的上下方向上)具有间距112的行和列(例如,2×2)阵列布置。在一些实施例中,行间距110和列间距112是基于操作频率的波长(λ)和天线104的大小。行间距110和列间距112的例子包括但不限于一拉姆达(λ)、二分之一拉姆达(λ/2)、四分之一拉姆达(λ/4)、四分之三拉姆达(3λ/4)或四拉姆达(4λ)间距。间距110和112的选择取决于各种因素,包括但不限于互耦合(其通常与天线104之间的间隔或间距成反比)和光栅波瓣的出现(其可表现为干扰和功率损耗源)。在一些实施例中,行间距110和列间距112可为相同间距值以提供具有均匀间距的天线阵列。在其它实施例中,行间距110和列间距112可为不同间距值,例如二分之一拉姆达和四分之三拉姆达间距。
如图1中所示,RF单元100具有占据面积或外周边(以虚线示出),具有行长度114和列长度116。RF单元100的占据面积足够大以包括该组天线104的布局和行间距110和列间距112的一部分,以使得RF单元100可用作模板并重复(例如,在行和列两个方向上边对边放置)以形成RF单元100的阵列(也被称为RF单元布局),其中RF管芯102被布置成具有均匀行间距和均匀列间距(其中均匀行间距可以或可以不等于均匀列间距)。RF单元的占据面积内的该组天线104的布局也可以相同方式重复以(在PCB中)形成天线阵列,在所述天线阵列中,天线被布置成具有均匀行间距和均匀列间距(其中均匀行间距可以或可以不等于均匀列间距)。本公开提供一种形成包括根据RF单元布局而布置的RF管芯102阵列的单一封装半导体装置的方式,所述RF管芯102阵列被配置成直接附接到PCB且耦合到对应天线阵列,如下文进一步论述。
应注意,任何数目的RF单元100可以此类阵列实施,例如图5中示出的RF单元100的简单2×2布置。RF单元的布置可为各种形状,例如矩形、圆形布置(例如,其中RF管芯可以或可以不成行和成列)、无定形形状(例如,N×M个数目的RF管芯,但不成行和成列布置)及其类似者。RF单元布局500实施包括总共4个RF管芯102的RF单元阵列,所述RF管芯102被配置成耦合到总共16个天线104。其它例子包括4×8RF单元阵列(例如,32个RF管芯耦合到128个天线)、8×8RF单元阵列(例如,64个RF管芯耦合到256个天线)以及其它。在一些实施例中,RF单元布局的一个个例可用于将RF管芯阵列实施为传输器的部分,其也被称为传输器管芯阵列,而RF单元布局的另一个例性阵列可用于将RF管芯的另一阵列实施为接收器的部分,其也被称为接收器管芯阵列。举例来说,图18示出各自实施为N×M管芯阵列的传输器管芯阵列1802和接收器管芯阵列1804,N为大于一的整数且M为大于一的另一整数,其中N和M不必相等。在一些实施例中,传输器管芯阵列1802可实施于一个封装半导体装置(例如,8×8或64个RF管芯)中且接收器管芯阵列1804可实施于另一封装半导体装置(例如,8×8或64个RF管芯)中。在其它实施例中,单一封装半导体装置可包括传输器管芯阵列1802和接收器管芯阵列1804(例如,2×8×8或128个RF管芯)两者。
可使用一或多个封装半导体装置来形成较大封装装置,例如提供无线通信的路由器或其它网络装置。举例来说,图18示出包括附接到PCB 1810的传输器管芯阵列1802和接收器管芯阵列1804(作为单一封装半导体装置或作为两个封装半导体装置)的装置1800。传输器管芯阵列1802耦合到实施于PCB 1810中的收发器天线阵列,且接收器管芯阵列1804耦合到实施于PCB 1810中的接收器天线阵列(未示出)。中央处理单元(CPU)1806也可以附接到PCB 1810,所述中央处理单元(CPU)1806可被配置成执行信号处理,例如数字信号处理,以从所接收RF信号中提取信息或产生包括信息的RF信号以供传输。电源1808也可以附接到PCB 1810以为CPU、RF管芯和其它各种装置组件供电。
图6A示出根据图5中示出的RF单元布局500以两行两列(2×2)阵列布置的RF管芯102的示例性阵列600。分支RF信号路径使用多个分离器管芯602和信号线604耦合到每个RF管芯102。每个分离器管芯602包括实施专用功率分离器、功率组合器或所述两者的具有低***损耗的有源电路。每个分离器管芯602具有3个端口,一个端口“面向”主端口610且两个端口“面向”RF管芯102。实施专用功率分离器的分离器管芯602被配置成在面向一对RF管芯102的两个端口处将来自主端口610的输入RF信号分离成可比较输出RF信号。实施专用功率组合器的分离器管芯602被配置成将来自面向RF管芯102的端口的两个输入RF信号组合成向主端口610输出的单一RF信号。分离器管芯602可使用WLCSP(晶片级芯片规模封装)技术形成。在RF管芯102之间实施的分离器管芯602的数目取决于RF信号路径中的分支点的数目,所述分支点的数目可与实施于布局中的RF管芯102的数目相当(例如,针对达到4个RF管芯的RF信号路径所实施的3个分离器管芯)。包括分离器管芯602的RF信号路径沿RF单元100的边界布置,以便使每个RF管芯102与分离器管芯602之间的距离减到最小(或使信号线604的长度减到最小)。
举例来说,当传输RF信号(例如在专用传输器中或在设置成传输模式的收发器中)时,RF信号从“主干”路径上的主端口610开始且进入图6A的中部中示出的第一分离器管芯602,所述第一分离器管芯602将RF信号输出到一对分支(由信号线604实施)上,一个分支向左且一个分支向右。左分支由另一分离器管芯602分成另一对分支(在图6A的左侧所示),所述另一对分支分别被提供到在其相应组的天线104上传输RF信号的左上RF管芯和左下RF管芯。右分支也由另一分离器管芯602分成另一对分支(或信号线604)(在图6A的右侧所示),所述另一对分支分别被提供到在其相应组的天线104上传输RF信号的右上RF管芯和右下RF管芯。在接收RF信号(例如在专用接收器中或在设置成接收模式的收发器中)时遵循反向路径。在每组天线104处接收RF信号,并由相应的分离器管芯602组合每对分支(或信号线604),最终组合成朝向主端口610的主干路径。图6A中示出的分支图案是围绕阵列600的竖直和水平中线对称。
穿过线B的截面图示出于图6B中,所述截面图示出附接到PCB 606的顶表面的一对RF管芯102和分离器管芯δ02。RF管芯102各自耦合到形成于PCB 606内的一组天线104。在一些实施例中,每个天线104与PCB 606的底表面上的反射器404对准。在一些实施例中,不实施反射器404且天线104可替代地位于在与反射器404等效的位置中的PCB 606的底表面上。
图6A中示出的示例性分支图案可用于在主端口610与较大阵列中的每个RF管芯102之间形成较大分支信号路径。图7示出RF单元布局700的示例性分支信号路径,所述RF单元布局700实施总共64个RF管芯和63个分离器管芯的8×8RF单元阵列。图6A的分支图案用于实施分支的对称部分,其中整个所得分支信号路径通常是围绕阵列700的竖直和水平中线对称的(例如,共同分支图案可见于阵列700的四个象限中)。右下部分702示出于图8中,所述右下部分702示出耦合到每个分支点的多个管芯。以图8中右下方处的一对管芯开始,第一分支点耦合到2个管芯,朝向主端口610的下一分支点耦合到4个管芯,且朝向主端口610的下一分支点耦合到8个管芯。后续分支点分别耦合到16个、32个和64个管芯。
实施分支信号路径的信号线604可实施于PCB 606中或本文所论述的封装半导体装置的各种实施例中。一些实施例(例如图10和12中示出的实施例)规定,每个分离器管芯602之间的信号线604实施于PCB 606中。其它实施例(例如图16和17中示出的实施例)规定,每个分离器管芯602之间的信号线604实施于封装半导体装置中。本文中所描述的实施例可使用与图9A到9I和图11A到11I中示出的那些工艺相同的工艺制造。
图9A到9I示出用于产生包括RF管芯102和分离器管芯602两者的阵列的封装半导体装置的示例性工艺流程,所述RF管芯102和分离器管芯602根据RF单元100的布局而布置。虽然图9A到9I中仅示出两个RF管芯102和一个分离器管芯602,但是这些管芯代表封装半导体装置中所包括的所有RF管芯102和分离器管芯602。
图9A示出根据RF单元阵列放置在牺牲载体902上的多个RF管芯102和多个分离器管芯602。在一些实施例中,牺牲载体902是玻璃载体。牺牲载体902包括按模拟所得封装半导体装置所附接到的PCB的布局的布局来布置的多个导电迹线和触点906。RF管芯102和分离器管芯602在牺牲载体902上的放置位置对应于在PCB上的位置。导电迹线和触点906还针对每个RF管芯102和分离器管芯602实施测试电路908。包括接合焊垫的RF管芯102和分离器管芯602各自具有有源侧204,所述接合焊垫具有附接的焊料凸块904(例如,管芯可在WLCSP工艺中“凸起”)。RF管芯102和分离器管芯602以有源侧204向下(或面向下)朝向放置在牺牲载体902上,其中焊料凸块904与触点906对准。RF管芯102在有源侧204上各自具有RF敏感区208,所述RF管芯102可包括实施传输器、接收器或收发器的前端电路。RF管芯102和分离器管芯602各自具有背对着牺牲载体902的背侧202。
图9B示出在执行回焊之后附接到牺牲载体902的RF管芯102和分离器管芯602,所述回焊在焊料凸块904与触点906之间形成电接触。回焊减少焊料凸块904的任何高度变化。图9C示出使用测试电路908在牺牲载体902上执行探针测试910。检查每个RF管芯102和分离器管芯602,并移除和替换任何检测到的故障RF管芯或分离器管芯。这一步骤确保所得封装半导体装置的令人满意的良率,是因为一个有故障的RF管芯102意味着一组天线(例如4个或更多个天线)不可用。
图9D示出在RF管芯102和分离器管芯602包封于牺牲载体902上之后所得的嵌入式管芯面板,所述包封在替换在探针测试910期间检测到的任何故障管芯之后发生。用模塑化合物材料包封RF管芯102和分离器管芯602以在每个管芯102和602的背侧202上方形成具有背表面916的模具主体912(其中所包封的管芯102和602在本文中也被称为嵌入式管芯阵列)。在一些实施例中,底部填充材料914也用于填充每个管芯与牺牲载体902之间的空间,从而使得模具主体912完全包封管芯102和602。底部填充材料914是具有低CTE(热膨胀系数)的粘附到管芯102和602的介电或绝缘材料。底部填充材料(如底部填充材料914)可包括但不限于基于环氧树脂的***或可以(例如,通过热量、紫外光及其类似者)固化成固体复合材料的液体聚合物中的低CTE填充材料(例如,二氧化硅、氧化铝、氮化硼及其类似者)。在一些实施例中,底部填充材料可为模塑化合物材料(用于形成模具主体,如模具主体912),所述模塑化合物材料可以基于联苯型或多芳型环氧树脂或粘附到管芯102和602的其它适当材料。可以通过传递模塑技术、底部填充技术、包覆成型技术、圆顶封装(glob top)、压缩成型技术或其它适合的包封技术执行包封。
还应注意,调整RF管芯之间的间距(例如列间距和行间距)以抵消模具主体的任何已知收缩,从而保持RF管芯之间的恰当距离。举例来说,特定大小的面板可经受模具主体的收缩(例如,随着模塑化合物固化,整个模具主体可收缩)。RF管芯的列间距和行间距可通过模具主体的已知收缩来增加,以补偿此类收缩(例如,如果模具主体收缩1到2%,那么RF管芯之间的距离增加1到2%)。
图9E示出在执行平坦化步骤918以减小面板的厚度且形成面板的新背侧之后的嵌入式管芯面板。平坦化步骤918移除模具主体912的一部分920以暴露模具主体912的(新)背表面924,所述(新)背表面924也被称为嵌入式管芯面板的背表面924。平坦化步骤918也移除每个管芯102和602的一部分以将每个管芯的(新)背表面922暴露于面板的背表面924中。平坦化步骤918之后也可能是例如使用干式抛光、超细研磨或其它适合的技术的抛光步骤。可以使用研磨或CMP(化学机械抛光)技术执行平坦化步骤918以获得共面表面924和922。
图9F示出在任选背侧金属化层926形成于共面表面924和922上方之后的嵌入式管芯面板。在没有金属化层926的情况下,平坦化步骤918减小管芯102和602的厚度且提供管芯102和602的共面背侧(例如,消除管芯102和602的背侧的任何倾斜),这两者皆提高嵌入式管芯面板的热性能。在示出的实施例中,金属化层926直接接触每个RF管芯102和分离器管芯602的硅背侧,以提高面板的热导率且进一步提高面板的热性能。金属化层(如金属化层926)通过沉积工艺形成,所述沉积工艺包括但不限于溅射、旋涂、化学气相沉积(CVD)、物理气相沉积(PVD)和共形沉积。金属化层(如金属化层926)可包括具有适合热导特性的一或多种导电材料,例如金、铜、铝、钨及其类似者。
图9G示出在带928附接到背侧金属化层926且移除牺牲载体902之后的嵌入式管芯面板。在一些实施例中,胶带(如胶带928)由聚合物膜形成,所述聚合物膜例如是PVC(聚氯乙烯)、聚烯烃、聚乙烯或类似材料,其中粘合剂放置在聚合物膜表面上。在一些实施例中,胶带可响应于UV(紫外光)暴露或温度漂移而移除(例如,粘合剂响应于UV暴露或温度漂移而减弱)。在一些实施例中,胶带包括将面板从所述胶带剥离的剥离层。在一些实施例中,使用临时载体(例如,玻璃载体)918而非胶带928。在一些实施例中,牺牲载体902通过研磨步骤934来移除,所述研磨步骤934暴露模具主体912的前表面930,所述前表面930也被称为面板的前表面930。每个(回焊)焊料凸块904的前表面932也暴露于面板的前表面930中,其中前表面930和932共面。焊料凸块904的前表面932被配置成附接到PCB。图9G中示出的面板950(在移除胶带928之后)可为封装半导体装置的一个实施例。
图9H示出在执行另一平坦化步骤936以将面板进一步薄化到所需厚度且形成面板的新前侧之后的嵌入式管芯面板。平坦化步骤936移除模具主体912的一部分以暴露模具主体912的(新)前表面940,所述(新)前表面940也被称为面板的前表面940。平坦化步骤918也移除每个焊料凸块904的一部分以暴露面板的前表面940中的每个焊料凸块904的(新)前表面942,所述(新)前表面942被配置成附接到PCB。可以使用研磨或CMP(化学机械抛光)技术执行平坦化步骤936以获得共面表面940和942。平坦化步骤936之后也可能是例如使用干式抛光、超细研磨或其它适合的技术的抛光步骤。图9H中示出的面板952(在移除胶带928之后)可为封装半导体装置的一个实施例。
图9I示出在执行激光步骤938且移除胶带928之后的嵌入式管芯面板。RF敏感区208周围存在介电材料(如模具主体912)带来信号衰减且不利地影响RF性能。激光步骤938使用激光从RF敏感区208周围移除模具主体912的一部分,所述移除暴露RF管芯102的有源侧204而不破坏RF管芯102。在一些实施例中,应选择底部填充材料914作为可易于用激光移除的材料,所述底部填充材料914用于对每个RF管芯102与牺牲载体902之间的RF敏感区208进行底部填充。激光步骤(如激光步骤938)可使用近红外(NIR)激光(例如,Nd:YAG激光)或绿色(例如,二次谐波发生)激光或其它适合的激光实施,所述其它适合的激光器例如是那些用于激光打标或焊球开封以局部移除介电材料(如底部填充材料和模塑化合物材料)而不破坏底层特征的激光。激光步骤(如步骤938)有效地在RF敏感区208周围形成气隙,这对RF性能有益。图9I中示出的面板954(在激光步骤938之后)可为封装半导体装置的一个实施例。
图10示出示例性装置1000的分解图,所述示例性装置1000包括使用如图9A到9I中示出的制造工艺制造的示例性封装半导体装置1050(例如,装置950、952或954)。如所示出,热界面材料(TIM)1006附接到封装半导体装置1050的背侧,所述背侧由金属化层926形成。TIM 1006是导热的。TIM 1006还附接到冷却***1002,所述冷却***1002在示出的实施例中包括一或多个散热管1004。在一些实施例中,冷却***1002还包括在一或多个散热管1004周围的散热器或散热片,所述散热器或散热片可由铝、铝合金、铜、铜合金、氮化硼、氮化铝、金刚石、碳纳米管及其组合形成。因为确认RF管芯102和分离器管芯602的背表面共面(由平坦化步骤918引起),所以经由金属化层926和TIM 1006在冷却***1002(例如,散热器或散热片)的平面表面与管芯102和602的每个背表面之间形成有效导热路径,从而提供提高的热转移。另外,由于RF管芯102和分离器管芯602被薄化,因此导热路径更接近产生热量的有源电路以提高热转移。TIM的例子包括但不限于含有悬浮碳纳米管或氧化铍、氮化铝、氮化硼或金刚石粉末的硅酮或环氧基材料。在一些实施例中,也可以使用金属填料,如银。在一些实施例中,TIM可为相变金属合金、石墨烯基粘合剂及其类似者。
应注意,与包括电动机的加压换气扇或风扇***相比(所述电动机在连续运行以用于长期操作时易发生故障),散热管1004***是被设计成用于长期操作而几乎无需维护的高效热导体。加压换气扇或风扇***也可能需要散热器或散热片,所述加压换气扇或风扇***可能缺乏到每个管芯的有效导热路径,其取决于(可能非平面的管芯)是否与散热器的平面表面进行充分热接触(例如,管芯可能由于一定程度的倾斜而为非平面的)。
封装半导体装置1050与PCB 606之间的界面也示出于图10中。装置1050基于也由PCB 606实施的布局来实施嵌入式管芯阵列(包括RF管芯102和分离器管芯602两者)。装置1050中的嵌入式管芯阵列具有多个暴露焊料凸块904,所述焊料凸块904与PCB 606上的多个着陆焊垫1008对准。在一些实施例中,可结合回焊工艺,使用焊膏、焊球或其它形式的焊接附接件将焊料凸块904附接到着陆焊垫1008。连接到分离器管芯602的着陆焊垫1008提供与PCB 606中的信号线604的连接。连接到RF管芯102的一些着陆焊垫1008提供与PCB 606中的天线的连接。在一些实施例中,天线可实施为PCB 606的背侧上的天线608。在其它实施例中,天线阵列可实施为在PCB 606内部的阵列,其中反射器608实施于PCB 606的背侧上。
由于信号线604实施于PCB 606中,因此在装置1050与PCB 606之间来回路由RF信号。举例来说,RF信号从PCB 606上的信号线604路由,转变到封装半导体装置1050中的分离器管芯602,转变回到PCB 606上的后续信号线604,且(最终)转变到封装半导体装置1050中的RF管芯102,其中在每次转变时发生信号衰减。当使用焊料凸块将装置1050附接到PCB606时,在每次焊料凸块转变时也发生另外的信号衰减。下文结合图16和17进一步论述使此RF信号路由的反复性质降到最低的其它实施例,所述其它实施例可以通过减少PCB 606与装置1050之间的转变数来使信号损耗降到最低。
图11A到11I示出用于产生包括RF管芯102和分离器管芯602两者的阵列的封装半导体装置的另一示例性工艺流程,所述RF管芯102和分离器管芯602根据RF单元100的布局而布置。图11A到11I中示出的管芯102和602代表封装半导体装置中所包括的所有管芯102和602。图11A到11I中示出的工艺使用重布层(RDL)实施扇出晶片级处理(FOWLP)。
图11A示出根据RF单元阵列的放置在临时载体1102上的多个RF管芯102和多个分离器管芯602。在一些实施例中,临时载体1102是牺牲载体,如牺牲载体902(上文所论述)。在一些实施例中,临时载体1102是玻璃载体。管芯102和602各自具有包括接合焊垫的有源侧204,但接合焊垫此时不凸起。管芯102和602以有源侧204向下(或面向下)朝向在临时载体1102上的放置位置对应在PCB上的位置。RF管芯102在有源侧204上各自具有RF敏感区208,所述RF管芯102可包括实施传输器、接收器或收发器的前端电路。RF管芯102和分离器管芯602各自具有背对着临时载体1102的背侧202。
图11B示出在RF管芯102和分离器管芯602包封于临时载体1102上之后所得的嵌入式管芯面板。用模塑化合物材料包封管芯102和602以在每个管芯102和602的背侧202上方形成具有背表面1108的模具主体1106(其中所包封的管芯102和602在本文中也被称为嵌入式管芯阵列)。图11C示出在移除临时载体1102之后所得的嵌入式管芯面板,所述移除暴露模具主体1106的前表面1110,其也被称为面板的前表面1110。有源侧204也暴露于面板的前表面1110中。在一些实施例中,临时载体1102可通过类似于图9G中示出的研磨步骤的研磨步骤来移除。在其它实施例中,临时载体1102包括将面板从所述临时载体1102剥离的剥离层。
图11D示出在RDL(重布层)结构1112形成于面板的前表面1110上之后的嵌入式管芯面板。RDL结构(如结构1112)由多个介电层和金属层形成,所述介电层和金属层又形成延伸穿过RDL结构的多个导电迹线。RDL结构使用应用于标志的一系列众多工艺步骤形成,所述工艺步骤包括但不限于沉积包括介电材料和金属的半导体材料(例如生长、氧化、溅射和共形沉积)、蚀刻半导体材料(例如使用湿性蚀刻剂或干性蚀刻剂)、执行用于图案化的光刻(包括沉积和移除光刻掩模或其它光阻材料)、层压、分配、印刷、喷射、喷涂及其类似者。在示出的实施例中,RDL结构1112实施导电迹线1116和触点1114,所述导电迹线1116和触点1114接触每个管芯102和602上的每个接合焊垫。
图11E示出在胶带1120(如胶带928)附接到RDL结构1112之后的嵌入式管芯面板。图11F示出在执行平坦化步骤1122以减小面板的厚度且形成面板的新背侧之后的嵌入式管芯面板。平坦化步骤1122移除模具主体1106的一部分1124以暴露模具主体1106的(新)背表面1128,所述(新)背表面1128也被称为面板的背表面1128。平坦化步骤1122也移除每个管芯102和602的一部分,以将每个管芯的(新)背表面1126暴露于面板的背表面1128中。可以使用研磨或CMP技术执行平坦化步骤1122以获得共面表面1126和1128。平坦化步骤1122之后也可能是例如干式抛光、超细研磨或其它适合的技术的抛光步骤。
图11G示出在任选背侧金属化层1130(如金属化层926)形成于共面表面1126和1128上方之后的嵌入式管芯面板。金属化层1130直接接触每个RF管芯102和分离器管芯602的背侧以提高热导率。图11G中示出的面板1150(在移除胶带1120之后)可为封装半导体装置的一个实施例。
图11H示出在移除胶带1120且面板凸起之后的嵌入式管芯面板,其中焊料凸块1132形成于RDL结构1112的每个触点1114上。图11H中示出的面板1152可为封装半导体装置的一个实施例。
图11I示出在执行激光步骤1134之后的嵌入式管芯面板。激光步骤1134(如步骤938)使用激光从RF敏感区208周围移除RDL结构1112的一部分,所述移除暴露RF管芯102的有源侧204而不破坏RF管芯102。激光步骤在RF敏感区208周围形成气隙,这对RF性能有益。图11I中示出的面板1154可为封装半导体装置的一个实施例。
图12示出另一示例性装置的分解图,所述示例性装置包括使用如同图11A到11I中示出的制造工艺的制造工艺制造的示例性封装半导体装置1250(例如,装置1150、1152或1154)。TIM 1006附接到封装半导体装置1250的背侧,所述背侧由金属化层1130形成。TIM1006也附接到如上文所描述的冷却***1102。还示出了封装半导体装置1250与PCB 606之间的界面。装置1050上的焊料凸块1132与PCB 606上的多个着陆焊垫1008对准,所述多个着陆焊垫1008包括如上文所描述的与PCB中的天线的连接。焊料凸块1132可通过执行回焊工艺来连接到PCB 606。在示出的实施例中,信号线604也实施于PCB 606中。
图13、14和15示出用于比较由类似于图9A到9I和11A到11I中示出的那些制造工艺的制造工艺实现的厚度或高度的代表性截面图。为进行参考,图13示出实施裸RF管芯的常规封装半导体装置,所述裸RF管芯各自具有厚度1305、TIM厚度1310、金属化厚度1315和焊料凸块高度1320(例如,在回焊之前)。TIM和金属化层用于形成从裸RF管芯到在图13中示出的装置顶部处的热转移机构的热连接路径。照惯例,裸RF管芯单独地放置在PCB上,其中每个裸RF管芯可能具有一定倾斜或旋转,其中裸RF管芯的背侧是非平面的。为了补偿这一程度的非平面性,常规装置中的TIM厚度1310大于将每个非平面RF管芯附接到热转移机构的平面表面所需的厚度(例如,100微米)。然而,较大TIM厚度1310增加导热路径的长度且降低图13中的装置的热性能。另外,裸RF管芯的厚度1305可为从晶片单切时的管芯的原始厚度(例如,200微米)。图13中的装置的所得轮廓高度是厚度1305、1310、1315和1320的总和。
图14示出通过类似于图9A到9I中示出的制造工艺的制造工艺形成的示例性封装半导体装置,且图15示出通过类似于图11A到11I中示出的制造工艺的制造工艺形成的示例性封装半导体装置。图14和15两者皆示出由本发明所公开的制造工艺中的平坦化步骤引起的RF管芯的所减小厚度1405和1505,所述平坦化步骤从RF管芯的背侧移除多余的硅(例如,使RF管芯变薄20到50微米)且降低轮廓高度。由于图14中的模具主体实施足够刚度,因此管芯厚度1405的减小量相比管芯厚度1504可更大(例如,厚度1405可为总共50微米,而厚度1505可为总共150微米)。由于平坦化步骤确保RF管芯的共面背侧,因此需要更薄的TIM厚度1410和1510(例如,25到50微米),这也降低了轮廓高度。另外,即使实施相同金属化厚度(例如,厚度1415和1515是与厚度1315相同的值,例如2到6微米),从RF管芯到热转移机构(例如,散热管)的导热路径同时更短且更接近RF管芯(归因于薄化硅)的有源侧上的有源电路以提供改进的热转移。
图14还示出短于焊料凸块高度1320的焊料凸块高度1420(例如,在回焊之前),其中装置上的每一焊料凸块的焊料凸块高度1420可由平坦化步骤控制。图15示出焊料凸块高度1520(在回焊之前),所述焊料凸块高度1520可等于焊料凸块高度1320(例如,170到200微米)。图15还示出抵消焊料凸块高度1520的RDL结构高度1525(例如,取决于RDL层厚度和所用RDL层的数目,例如总共10到30微米)。然而,图14和15中示出的装置的所得轮廓高度仍然短于图13中示出的常规装置的轮廓高度。
应注意,可修改图11A到11I中示出的工艺以使用重布层(RDL)实施扇出晶片级处理(FOWLP),从而将信号线604移动到封装半导体装置(且移出PCB),所述移动减少所得封装半导体装置与PCB之间的转变的数目。举例来说,可修改图11D中示出的RDL结构的形成以形成包括在分离器管芯602与RF管芯102之间形成的信号线604的RDL结构。
图16示出另一示例性装置的分解图,所述示例性装置包括使用类似于图11A到11I中示出的制造工艺的制造工艺制造的示例性封装半导体装置1650,所述制造工艺包括修改后的图11D RDL步骤。装置1650包括形成分支RF信号路径(例如,如图7中示出的路径)的RDL结构1112,其中RDL结构1112的导电迹线1116也在RF管芯102上的接合焊垫与分离器管芯602上的接合焊垫之间形成信号线604。RDL结构1112也可以形成到分离器管芯602上的接合焊垫的其它线(例如,接地线),其中分离器管芯602完全不再需要凸起。通过信号线104连接到分离器管芯602的RF管芯102上的接合焊垫也不需要凸起。此类实施例也允许信号线604和对应着陆焊垫1008从PCB 606移除(例如,简化PCB制造工艺)。图16中示出的实施例使从PCB 606到装置1650的转变减到最少(例如,将转变减少到一,其中RF信号被提供到装置1650上的主端口610),这降低了信号衰减且提高了RF性能。
图17示出另一示例性装置的分解图,所述示例性装置包括使用类似于图11A到11I中示出的制造工艺的制造工艺制造的示例性封装半导体装置1750,所述制造工艺包括修改后的图11D RDL步骤。装置1750包括进一步实施每个分离器管芯602的功能的RDL结构1112。此类实施例省略了图11A中示出的步骤中的将分离器管芯602作为单独管芯放置于临时载体1102上。替代地,有源电路1702(以虚线轮廓示出)形成于装置1750上的RDL结构1112内(例如在修改后的图11D RDL步骤期间),所述有源电路1702实施功率分离器、功率组合器或所述两者。RDL结构1112也形成分支RF信号路径(例如,如图7中示出的路径),其中RDL结构1112的导电迹线也在RF管芯102上的接合焊垫与有源电路1702的相应端口之间形成信号线604。通过信号线104连接到有源电路1702的RF管芯102上的接合焊垫不需要凸起。此类实施例也允许信号线604和对应着陆焊垫1008从PCB 606移除(例如,简化PCB制造工艺)。图17中示出的实施例使从PCB 606到装置1750的转变减到最少(例如,将转变减少到一,其中RF信号被提供到装置1750上的主端口610),这降低了信号衰减且提高了RF性能。
本文中所描述的RF管芯102可由半导体晶片(也简称为晶片)形成,所述半导体晶片可以是任何半导体材料或材料组合,例如砷化镓、锗化硅、绝缘体上硅(SOI)、硅、单晶硅、类似物和以上各者的组合。RF管芯102可使用倒装芯片工艺形成以使管芯102凸起并从晶片单切管芯102。本文中所描述的分离器管芯602也可以由半导体晶片形成,所述半导体晶片可使用WLCSP(晶片级芯片规模封装)工艺使管芯602凸起并从晶片单切管芯602。用于RF管芯102和分离器管芯602的有源电路使用应用于晶片的一系列众多工艺步骤形成,所述工艺步骤包括但不限于:沉积包括介电材料和金属的半导体材料(例如,生长、氧化、溅镀和共形沉积)、蚀刻半导体材料(例如,使用湿性蚀刻剂或干性蚀刻剂)、平坦化半导体材料(例如,执行化学机械抛光或平坦化)、执行用于图案化的光刻(包括沉积和移除光刻掩模或其它光阻材料)、离子植入、退火及其类似者。在一些实施例中,有源电路可为集成电路组件的组合或可为另一类型的微电子装置。集成电路组件的例子包括但不限于处理器、存储器、逻辑、模拟电路、传感器、MEMS(微机电***)装置、独立分离装置(例如电阻器、电感器、电容器、二极管、功率晶体管),及其类似者。
如本文所用,“节点”意味着任何内部或外部参考点、连接点、接合点、信号线、导电元件等等,在所述“节点”处存在给定信号、逻辑电平、电压、数据模式、电流或量。此外,两个或更多个节点可通过一个物理元件实现(并且尽管在共同节点处接收或输出,但是仍然可对两个或更多个信号进行多路复用、调制或以其它方式区分)。
以下描述是指节点或特征被“连接”或“耦合”在一起。如本文所使用,除非另外明确地陈述,否则“耦合”意指一个节点或特征直接或间接接合到另一节点或特征(或与其直接或间接连通),并且未必是以物理方式接合。如本文所使用,除非另外明确地陈述,否则“连接”意指一个节点或特征直接接合到另一节点或特征(或与其直接连通)。举例来说,开关可“耦合”到多个节点,但所有这些节点不必始终彼此“连接”,开关可能取决于开关状态而将不同节点彼此连接。此外,尽管本文所示的各种示意图描绘元件的某些示例性布置,但在实际实施例中也可存在额外介入元件、装置、特征或组件(假设给定电路的功能性不受不利影响)。
目前应了解,已提供封装半导体装置的实施例和制造此类装置的实施例,所述半导体装置可包括多个RF管芯、多个分离器管芯或两者,其中本发明所公开的装置中所包括的管芯的总数可为数百个管芯。装置提供用于附接到印刷电路板(PCB)或其它载体且附接到用于冷却***以改进热性能的平面表面。装置还可以包括使PCB与装置之间的任何转变减到最少以改进RF性能的导电迹线或信号线。
在本公开的一个实施例中,提供一种制造多管芯封装的方法,所述方法包括:将多个倒装芯片管芯和多个分离器管芯放置在牺牲载体上,每个倒装芯片管芯和每个分离器管芯以有源侧向下朝向定位于牺牲载体上;执行焊料回焊以将每个倒装芯片管芯和每个分离器管芯的焊料凸块接合到牺牲载体,其中牺牲载体包括测试探针电路;在探针测试中使用测试探针电路测试多个倒装芯片管芯和多个分离器管芯;如由测试所指示替换任何故障倒装芯片管芯和任何故障分离器管芯;使多个倒装芯片管芯和多个分离器管芯在牺牲载体上包覆成型以形成嵌入式管芯面板;使嵌入式管芯面板平坦化以将每个倒装芯片管芯和每个分离器管芯的背表面暴露于嵌入式管芯面板的背表面中;跨越嵌入式管芯面板的背表面形成金属化层,所述金属化层接触每个倒装芯片管芯和每个分离器管芯的背表面;以及移除牺牲载体以暴露嵌入式管芯面板的前表面,其中每个倒装芯片管芯和每个分离器管芯的每个焊料凸块的接触表面暴露于嵌入式管芯面板的前表面中。
上述实施例的一个方面规定,移除牺牲载体包括:研磨掉牺牲载体。
上述实施例的另一方面规定,牺牲载体包括玻璃载体。
上述实施例的另一方面规定,所述方法还包括:将胶带附接到金属化层;在移除牺牲载体之后,平坦化以暴露嵌入式管芯面板的新的前表面,其中每个焊料凸块的新接触表面暴露于嵌入式管芯面板的新的前表面中。
上述实施例的另一方面规定,使嵌入式管芯面板平坦化包括:从每个倒装芯片管芯和每个分离器管芯移除背侧部分,以暴露每个倒装芯片管芯和每个分离器管芯的背表面。
上述实施例的另一方面规定,包覆成型还包括:用底部填充材料对每个倒装芯片管芯与牺牲载体之间的空间进行底部填充。
上述实施例的又一方面规定,所述方法还包括:在移除牺牲载体之后,对嵌入式管芯面板的前表面执行激光移除,以从每个倒装芯片管芯的每个凸起侧面上的射频(RF)敏感区移除底部填充材料。
上述实施例的另一方面规定,每个倒装芯片管芯包括靠近每个倒装芯片管芯的凸起侧面的射频(RF)收发器。
上述实施例的另一方面规定,每个分离器管芯被配置成在传输模式期间在第一端口处接收射频(RF)信号且在第二端口和第三端口处输出所述RF信号,且被配置成在接收模式期间在第一端口处组合第二和第三端口上的RF信号。
上述实施例的另一方面规定,多管芯封装被配置成附接到印刷电路板(PCB),其中所述PCB包括:多个天线,其中多管芯封装的每个倒装芯片管芯被配置成连接到多个天线的子组;和多个射频(RF)信号线,所述RF信号线被配置成在多个倒装芯片管芯与多个分离器管芯之间提供信号连接。
在本公开的另一实施例中,提供一种制造多管芯封装的方法,所述方法包括:通过胶带将多个倒装芯片管芯附接到临时载体,每个倒装芯片管芯以有源侧向下朝向定位于临时载体上;使临时载体上的多个倒装芯片管芯包覆成型以形成嵌入式管芯面板;移除临时载体和胶带以暴露嵌入式管芯面板的前表面,其中在移除临时载体和胶带之后暴露每个倒装芯片管芯的有源侧;在嵌入式管芯面板的前表面上方形成重布层(RDL)结构,其中RDL结构包括连接到每个倒装芯片管芯的有源侧的迹线;使嵌入式管芯面板平坦化以将每个倒装芯片管芯的背表面暴露于嵌入式管芯面板的背表面中;以及跨越嵌入式管芯面板的背表面形成金属化层,所述金属化层接触每个倒装芯片管芯的背表面。
上述实施例的一个方面规定,所述方法还包括:将多个焊球放置在RDL结构中的接触焊垫上。
上述实施例的另一方面规定,所述方法还包括:对RDL结构执行激光移除以从每个倒装芯片管芯的每个凸起侧面上的射频(RF)敏感区移除RDL结构的一部分。
上述实施例的另一方面规定,使嵌入式管芯面板平坦化包括:从每个倒装芯片管芯移除背侧部分以暴露每个倒装芯片管芯的背表面。
上述实施例的另一方面规定,所述方法还包括:以有源侧向下朝向将多个倒装芯片管芯之间的多个分离器管芯放置在临时载体上,其中在包覆成型之后,多个分离器管芯也包括在嵌入式管芯面板中。
上述实施例的又一方面规定,多管芯封装被配置成附接到印刷电路板(PCB),其中所述PCB包括:多个天线,其中多管芯封装的每个倒装芯片管芯被配置成连接到多个天线的子组;和多个射频(RF)信号线,所述RF信号线被配置成在多个倒装芯片管芯与多个分离器管芯之间提供信号连接。
上述实施例的再一方面规定,RDL结构还包括:在多个倒装芯片管芯与多个分离器管芯之间提供信号连接的多个射频(RF)信号线。
上述实施例的又另一方面规定,多管芯封装被配置成附接到印刷电路板(PCB),其中所述PCB包括:多个天线,其中嵌入式管芯面板的每个倒装芯片管芯被配置成连接到多个天线的子组。
上述实施例的另一方面规定,RDL结构还包括:在多个倒装芯片管芯之间的多个分离器电路;和在多个倒装芯片管芯与多个分离器电路之间提供信号连接的多个射频(RF)信号线。
上述实施例的另一方面规定,所述方法还包括:将热界面材料(TIM)的第一侧附接到嵌入式管芯面板的金属化层,其中TIM的第二侧被配置成附接到包括散热管的冷却***。
由于实施本发明的设备大部分由本领域的技术人员已知的电子组件和电路组成,因此为了理解和了解本发明的基本概念并且为了不混淆或偏离本发明的教示,将不会以比上文所说明的认为必要的任何更大程度阐述电路细节。
此外,在说明书和权利要求书中的术语“前面”、“背面”、“顶部”、“底部”、“在......上方”、“在......下方”和类似者(如果存在的话)用于描述性目的,且未必用于描述永久性相对位置。应理解,如此使用的术语在适当情况下可互换,使得本文中所描述的本发明实施例(例如)能够相比本文中所说明或以其它方式描述的那些朝向以其它朝向进行操作。
应注意,如本文所用的术语“相邻(neighboring)”意味着“邻接于(adjacent to)”(例如,紧靠着而无中间物体),且如本文所用的“侧向(laterally)”意味着“在侧向方向上”(例如,平行于基板平面的水平方向)。
如本文所使用,术语“实质性”和“大体上”意味着足以用切实可行的方式实现所陈述的目的或值,这考虑由可在晶圆制造期间发生的常见和预期工艺异常引起的任何轻微缺陷或偏差(如果存在的话),这些轻微缺陷或偏差对于所陈述的目的或值并不显著。
虽然本文中参考具体实施例描述了本发明,但是可以在不脱离如以下所附权利要求书中所阐述的本发明的范围的情况下进行各种修改和改变。举例来说,可在图7中实施额外或更少RF管芯。因此,说明书和图式应视为说明性而不是限制性意义,并且预期所有这些修改都包括在本发明的范围内。并不意图将本文中相对于具体实施例描述的任何益处、优点或针对问题的解决方案理解为任何或所有权利要求的关键、必需或必不可少的特征或元件。
此外,如本文中所使用,术语“一(a/an)”被定义为一个或大于一个。另外,权利要求书中对例如“至少一个”和“一或多个”等引导性短语的使用不应被解释为暗示由不定冠词“一(a/an)”引导的另一权利要求要素将含有此类引导的权利要求要素的任何特定权利要求限制于仅含有一个此类要素的发明,即使是当同一权利要求包括引导性短语“一或多个”或“至少一个”和例如“一”等不定冠词时也如此。定冠词的使用也是如此。
除非另有规定,否则例如“第一”和“第二”等术语用于任意地区别此类术语所描述的元件。因此,这些术语未必意图指示此类元件的时间上的优先级或其它优先级。
Claims (10)
1.一种用于制造多管芯封装的方法,其特征在于,所述方法包括:
将多个倒装芯片管芯和多个分离器管芯放置在牺牲载体上,每个倒装芯片管芯和每个分离器管芯以有源侧向下朝向定位于所述牺牲载体上;
执行焊料回焊以将每个倒装芯片管芯和每个分离器管芯的焊料凸块接合到所述牺牲载体,其中所述牺牲载体包括测试探针电路;
使用所述测试探针电路在探针测试中测试所述多个倒装芯片管芯和所述多个分离器管芯;
如由所述测试指示替换任何故障倒装芯片管芯和任何故障分离器管芯;
将所述多个倒装芯片管芯和所述多个分离器管芯在所述牺牲载体上包覆成型以形成嵌入式管芯面板;
将所述嵌入式管芯面板平坦化以使每个倒装芯片管芯和每个分离器管芯的背表面暴露于所述嵌入式管芯面板的背表面中;
跨越所述嵌入式管芯面板的背表面形成金属化层,所述金属化层接触每个倒装芯片管芯和每个分离器管芯的所述背表面;以及
移除所述牺牲载体以暴露所述嵌入式管芯面板的前表面,其中每个倒装芯片管芯和每个分离器管芯的每个焊料凸块的接触表面暴露于所述嵌入式管芯面板的所述前表面中。
2.根据权利要求1所述的方法,其特征在于,进一步包括:
将胶带附接到所述金属化层;
在移除所述牺牲载体之后,平坦化以暴露所述嵌入式管芯面板的新前表面,其中每个焊料凸块的新接触表面暴露于所述嵌入式管芯面板的所述新前表面中。
3.根据权利要求1所述的方法,其特征在于,所述将所述嵌入式管芯面板平坦化包括:
从每个倒装芯片管芯和每个分离器管芯移除背侧部分以暴露每个倒装芯片管芯和每个分离器管芯的所述背表面。
4.根据权利要求1所述的方法,其特征在于,所述包覆成型进一步包括:
用底部填充材料对每个倒装芯片管芯与所述牺牲载体之间的空间进行底部填充。
5.根据权利要求1所述的方法,其特征在于,每个分离器管芯被配置成在传输模式期间在第一端口处接收射频(RF)信号并在第二端口和第三端口处输出所述RF信号,且被配置成在接收模式期间在所述第一端口处组合所述第二端口和所述第三端口上的RF信号。
6.根据权利要求1所述的方法,其特征在于,
所述多管芯封装被配置成附接到印刷电路板(PCB),其中所述PCB包括:
多个天线,其中所述多管芯封装的每个倒装芯片管芯被配置成连接到所述多个天线的子组,和
多个射频(RF)信号线,其被配置成在所述多个倒装芯片管芯与所述多个分离器管芯之间提供信号连接。
7.一种用于制造多管芯封装的方法,其特征在于,所述方法包括:
通过胶带将多个倒装芯片管芯附接到临时载体,每个所述倒装芯片管芯以有源侧向下朝向定位于所述临时载体上;
将所述多个倒装芯片管芯在所述临时载体上包覆成型以形成嵌入式管芯面板;
移除所述临时载体和胶带以暴露所述嵌入式管芯面板的前表面,其中在移除所述临时载体和胶带之后暴露每个倒装芯片管芯的有源侧;
在所述嵌入式管芯面板的所述前表面上方形成重布层(RDL)结构,其中所述RDL结构包括连接到每个倒装芯片管芯的所述有源侧的迹线;
将所述嵌入式管芯面板平坦化以使每个倒装芯片管芯的背表面暴露于所述嵌入式管芯面板的背表面中;以及
跨越所述嵌入式管芯面板的所述背表面形成金属化层,所述金属化层接触每个倒装芯片管芯的所述背表面。
8.根据权利要求7所述的方法,其特征在于,所述将所述嵌入式管芯面板平坦化包括:
从每个倒装芯片管芯移除背侧部分以暴露每个倒装芯片管芯的所述背表面。
9.根据权利要求7所述的方法,其特征在于,所述RDL结构进一步包括:
在所述多个倒装芯片管芯之间的多个分离器电路;和
多个射频(RF)信号线,其在所述多个倒装芯片管芯与所述多个分离器电路之间提供信号连接。
10.根据权利要求7所述的方法,其特征在于,进一步包括:
将热界面材料(TIM)的第一侧附接到所述嵌入式管芯面板的所述金属化层,其中所述TIM的第二侧被配置成附接到包括散热管的冷却***。
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CN111753481B (zh) * | 2020-07-01 | 2022-03-22 | 无锡中微亿芯有限公司 | 利用有源硅连接层平衡延迟的多裸片fpga |
CN111755437B (zh) * | 2020-07-01 | 2022-05-31 | 无锡中微亿芯有限公司 | 利用硅连接层形成片上网络的fpga装置 |
US11776915B2 (en) | 2020-07-01 | 2023-10-03 | Wuxi Esiontech Co., Ltd. | FPGA device forming network-on-chip by using silicon connection layer |
US12009307B2 (en) | 2020-07-01 | 2024-06-11 | Wuxi Esiontech Co., Ltd. | Multi-die FPGA implementing built-in analog circuit using active silicon connection layer |
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US20190189606A1 (en) | 2019-06-20 |
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