CN111696930A - 内埋元件封装结构、内埋式面封装基板及其制造方法 - Google Patents
内埋元件封装结构、内埋式面封装基板及其制造方法 Download PDFInfo
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Abstract
一种内埋元件封装结构,包括一线路基板、一内埋元件以及一应力抵消层。线路基板具有一核心层以及一非对称线路结构,核心层具有一第一厚度。内埋元件设置于核心层中。应力抵消层设置于核心层的一侧,应力抵消层具有一第二厚度,第二厚度介于4~351微米之间。
Description
技术领域
本发明是有关于一种元件封装结构及其制造方法,且特别是有关于一种内埋元件封装结构、内埋式面封装基板及其制造方法。
背景技术
在***级封装结构中,将半导体芯片埋入封装基板中的内埋元件技术(Semiconductor Embedded in SUBstrate,简称SESUB),因为具有降低封装基板产品受到噪声干扰及产品尺寸减小的优点,近年来已成为本领域制造商的研发重点。为了提高生产的良率,内埋元件必须固定在线路基板的核心层内,以利于后续制作的图案化导电层能与内埋元件电性连接。
另外,为了减少线路基板的翘曲量,线路基板于内埋元件的上方及下方设置相同数量的导电层,因而线路基板的用铜量增加而导致生产成本增加。
发明内容
本发明有关于一种内埋元件封装结构、内埋式面封装基板及其制造方法,可减少生产成本并可减少条状基板的翘曲量。
根据本发明的一方面,提出一种内埋元件封装结构,包括一线路基板、一内埋元件以及一应力抵消层。线路基板具有一核心层以及一非对称线路结构,核心层具有一第一厚度。内埋元件设置于核心层中。应力抵消层设置于核心层的一侧,应力抵消层具有一第二厚度,第二厚度介于4~351微米之间。
根据本发明的一方面,提出一种内埋式面封装基板,包括多个线路基板单元、多个内埋元件以及一应力抵消层。各线路基板单元具有一核心层以及一非对称线路结构,核心层具有一第一厚度。此些内埋元件设置于此些线路基板单元的核心层中。应力抵消层设置于此些线路基板单元的一侧,其中应力抵消层具有一第二厚度,内埋式面封装基板的翘曲量小于5mm。
根据本发明的一方面,提出一种内埋元件封装结构的制造方法,包括设置一应力抵消层于一核心层的一侧,核心层具有一第一厚度,应力抵消层具有一第二厚度。将一电子元件设置于核心层中。形成一非对称的线路结构于电子元件的上方及下方。
为了对本发明的上述及其他方面有更佳的了解,下文特举实施例,并配合所附附图详细说明如下:
附图说明
图1绘示原设计与改善后的线路结构的层数与翘曲量的关系比对图。
图2绘示原设计与改善后的线路结构的层数、铜箔基板厚度、核心层厚度、厚度比值、翘曲量以及残铜率的关系的比对表。
图3A绘示依照本发明一实施例的内埋元件封装结构的剖面示意图。
图3B绘示依照本发明另一实施例的内埋元件封装结构的剖面示意图。
图3C绘示依照本发明另一实施例的内埋元件封装结构的剖面示意图。
图3D绘示依照本发明另一实施例的内埋元件封装结构的剖面示意图。
图4绘示依照本发明一实施例的内埋式面封装基板的剖面示意图。
图5A至5E绘示依照本发明一实施例的内埋元件封装结构的制造方法的流程图。
附图标记:
100-103:内埋元件封装结构
110:线路基板
111:核心层
112:上导电层
112a:电性接点
113:介电材料层
115、116:下导电层
120:内埋元件
121:电性接垫
130:应力抵消层
S1:第一表面
S2:第二表面
140:焊球
T1:第二厚度
T2:第一厚度
C、C1、C2:导电柱
200:内埋式面封装基板
201:内埋元件封装结构
210:线路基板单元
211:核心层
211’:绝缘材料
211”:绝缘材料
212:非对称线路结构
220:内埋元件
230:应力抵消层
240:锡球
具体实施方式
以下提出实施例进行详细说明,实施例仅用以作为范例说明,并非用以限缩本发明欲保护的范围。以下是以相同/类似的符号表示相同/类似的元件做说明。以下实施例中所提到的方向用语,例如:上、下、左、右、前或后等,仅是参考所附附图的方向。因此,使用的方向用语是用来说明并非用来限制本发明。
依照本发明的一实施例,提出一种内埋元件封装结构,用以改善非对称线路结构于内埋元件的上方及下方产生一非对称的应力分布,因而可解决面封装基板(panelsubstrate)翘曲的问题。
非对称线路结构为在内埋元件的上方及下方的导电层的数量不同,例如上方导电层为2层或2层以上/下方导电层为1层(以2L+1L表示)、上方导电层为1层/下方导电层为2层或2层以上(以1L+2L表示)、上方导电层为2层或2层以上/没有下方导电层(以2L表示)、上方导电层为1层/没有下方导电层(以1L表示)或是其他种组合。
上述内容只是示意性举例一二,本发明对此不加以限制。请参照图1及图2所列的组合态样,非对称线路结构的上方导电层及下方导电层的数量可为2L+1L、1L+2L、2L、1L等至少四组非对称组合之一,且不同态样的非对称线路结构对于面封装基板造成的翘曲量也不同,因此,本实施例根据不同组合的非对称线路结构来量身订制不同厚度的应力抵消层,以有效抑制面封装基板的翘曲量,使其小于5mm。面封装基板例如是长条状基板或二维阵列基板,其包括多个线路基板单元和多个设置于线路基板单元内的内埋元件。
请参照图1及图2,在原始设计的封装结构(a)中,上方导电层及下方导电层的数量为2L+1L组合时,基板的翘曲量为19-25mm,远大于可容许的翘曲量5-10mm,然而在改善的封装结构(b)中加入应力抵消层之后,可使基板的翘曲量减少至2-4mm,小于可容许的翘曲量5-10mm。
此外,在原始设计的封装结构(a)中,上方导电层及下方导电层的数量为1L+2L组合时,基板的翘曲量为21-26mm,远大于可容许的翘曲量5-10mm,然而在改善的封装结构(b)中加入应力抵消层之后,可使基板的翘曲量减少至3-4mm,小于可容许的翘曲量5-10mm。
另外,在原设计的封装结构(a)中,上方导电层及下方导电层的数量为2L组合时(无下方导电层),基板的翘曲量为15-21mm,远大于可容许的翘曲量5-10mm,然而在改善的封装结构(b)中加入应力抵消层之后,可使基板的翘曲量减少至0-2mm,小于可容许的翘曲量5-10mm。
再者,在原设计的封装结构(a)中,上方导电层及下方导电层的数量为1L组合时(无下方导电层),基板的翘曲量为21-28mm,远大于可容许的翘曲量5-10mm,然而在改善的封装结构(b)中加入应力抵消层之后,可使基板的翘曲量为2-5mm,小于可容许的翘曲量10mm。
由上述的图表可知,本实施例可根据不同的非对称组合来订制不同厚度的应力抵消层,以有效抑制基板的翘曲量小于5mm。请参照图2,在原设计的结构(a)中,由于铜箔基板(Copper clad laminate,简称CCL)的厚度为固定值,介于30+/-5微米或40+/-5微米之间,且未考虑各导电层的残铜率及铜箔厚度对翘曲量的影响,因而翘曲量均远大于可容许的翘曲量5-10mm,无法降低。反观,在改善后的封装结构(b)中,由于铜箔基板(CCL)的厚度为非固定值,可介于4-351微米之间,且本实施例中进一步考虑各导电层的残铜率及铜箔厚度对翘曲量的影响,因此改善后的翘曲量可小于5mm。
如图2所示,当上方导电层及下方导电层的数量为2L+1L、1L+2L、2L、1L等四组组合时,铜箔基板(CCL)的厚度分别介于34-171(+/-12)微米、81-339(+/-12)微米、51-300(+/-12)微米以及16-129(+/-12)微米之间,其中+/-12微米为公差值。此外,当上方导电层及下方导电层的数量为2L+1L、1L+2L、2L、1L等四组组合时,铜箔基板的厚度(T1)与核心层的厚度(T2)的比值分别介于0.18~1.152、0.57~2.90、0.42~2.58以及0.03~1.17之间。核心层的厚度为固定值,例如为121+/-10微米,其厚度可根据实际需求调整。
在本实施例中,铜箔基板(或以下所称呼的应力抵消层)的厚度主要取决于该非对称的线路结构各导电层的残铜率与厚度,因此,当导电层的数量、残铜率以及厚度等多个参数中至少之一改变时,铜箔基板的厚度也会跟着改变,藉以平衡非对称线路结构对线路基板产生的非对称应力分布。
在一实施例中,各导电层的残铜率例如介于10%至95%之间,残铜率指铜层制成线路后的面积和整个未图案化铜层面积之比。没有加工制作线路的原始铜层的残铜率就是100%。此外,各导电层的厚度例如介于10至30微米之间。一般而言,残铜率增加或厚度增加,对线路基板的应力的影响程度也会增加,但仍需进一步比较核心层上方及下方的导电层的数量的差值,请参照如下说明。
请参照图3A,其绘示一种内埋元件封装结构100,包括一线路基板110、一内埋元件120以及一应力抵消层130。线路基板110具有一核心层111以及一上导电层112,且核心层111具有一第一厚度(以T2表示于图2中)。内埋元件120设置于核心层111中。核心层111具有相对的一第一表面S1(或第一侧)以及一第二表面S2(或第二侧),上导电层112设置于第一表面S1,且上导电层112与内埋元件120电性连接。也就是说,上导电层112的电性接点112a与相对应的内埋元件120的电性接垫121相互接触而导通。此外,本实施例更可设置多个焊球140于线路基板110上,并与上导电层112电性连接,以制作球格阵列型态的内埋元件封装结构100。
图3A中的非对称线路结构只有单一上导电层112,位于内埋元件120的上方,因此,本实施例中设置一应力抵消层130于内埋元件120的下方,也就是设置于核心层111的第二表面S2,用以平衡内埋元件120的上方及下方的应力分布。
应力抵消层130例如为包含玻纤的介电材料层,且没有铜层覆盖在此应力抵消层130上。由于应力抵消层130的介电材料固化之后具有较强的刚性,可抑制线路基板110向上弯曲,故可有效减少线路基板110的翘曲。在另一实施例中,应力抵消层130亦可采用具有预定强度的复合材料、纳米材料或金属材料制成,本发明对此不加以限制。
根据图2中的数值可知,图3A中应力抵消层130具有一第二厚度(以T1表示于图2中)例如介于16-129(+/-12)微米之间,且应力抵消层130的厚度与核心层111的厚度的比值(T1/T2)例如介于0.03-1.17之间。
举例而言,应力抵消层130的胶材与玻纤密度分别为1.1g/cm3与2.5g/cm3,胶含量50%,玻纤含量50%,上导电层112的铜密度为8.9g/cm3,残铜率为65%,铜厚度为13.6微米。应力抵消层130的厚度可以算式表示为:(上导电层铜厚度×残铜率×铜密度)/((胶含量×胶密度)+(玻纤含量×玻纤密度)),即(13.6微米×65%×8.9)/(50%×1.1+50%×2.5)=43.7微米。在另一实施例中,当残铜率变为95%时,应力抵消层130的厚度相对增加至63.88微米。在另一实施例中,当残铜率变为95%,且铜厚度变为30微米时,应力抵消层130的厚度相对增加至141微米。反之,当残铜率变为10%,且铜厚度变为10微米时,应力抵消层130的厚度相对减少至4微米。
请参照图3B,其绘示一种内埋元件封装结构101,包括一线路基板110、一内埋元件120以及一应力抵消层130。线路基板110具有一核心层111、二层上导电层112、114以及一介电材料层113。核心层111具有一第一厚度。内埋元件120设置于线路基板110的核心层111中。核心层111具有相对的一第一表面S1以及一第二表面S2,上导电层112设置于核心层111的第一表面S1,且上导电层112与内埋元件120电性连接,另一上导电层114设置于介电材料层113上。此二层上导电层112、114之间以贯穿介电材料层113的导电柱C相互导通。介电材料层113设置于此二上导电层112、114之间。此外,本实施例更可设置多个焊球140于线路基板110上,并与上导电层112、114电性连接,以制作球格阵列型态的内埋元件封装结构101,如上所述。
图3B中的非对称线路结构有两层上导电层112、114,位于内埋元件120的上方,因此,本实施例中设置一应力抵消层130于内埋元件120的下方,也就是设置于核心层111的第二表面S2,用以平衡内埋元件120的上方及下方的应力分布。上导电层112、114的数量不限定只有两层,亦可两层以上。
根据图2中的数值可知,图3B中应力抵消层130的厚度(以T1表示于图2中)例如介于51-300(+/-12)微米之间,且应力抵消层130的厚度与核心层111的厚度的比值(T1/T2)例如介于0.42-2.58之间。图3B中应力抵消层130的厚度主要取决于(上导电层铜厚度×残铜率×铜密度)/((胶含量×胶密度)+(玻纤含量×玻纤密度))以及介电材料层113的厚度,其算式如上所述,在此不再赘述。上述介电材料层113的材料可与应力抵消层130的介电材料相同,例如为玻纤含量相同的介电材料,因此,当介电材料层113的厚度增加(例如2层或3层)时,应力抵消层130的厚度也需相对增加,才能达到应力平衡。
请参照图3C,其绘示一种内埋元件封装结构102,包括一线路基板110、一内埋元件120以及一应力抵消层130。线路基板110具有一核心层111、二层上导电层112、114、一介电材料层113以及一下导电层115。介电材料层113设置于此二上导电层112、114之间。本实施例与上述实施例的差异在于更包括一下导电层115,设置于核心层111的第二表面S2,其余元件以相同的标号表示,在此不再赘述。
图3C中的非对称线路结构有两层上导电层112、114以及一下导电层115,分别位于内埋元件120的上方及下方,因此,本实施例中设置一应力抵消层130于内埋元件120的下方,也就是设置于核心层111的第二表面S2,与下导电层115位于核心层111的同一侧,用以平衡内埋元件120的上方及下方的应力分布。
根据图2中的数值可知,图3C中应力抵消层130的厚度(以T1表示于图2中)例如介于34-171(+/-12)微米之间,且应力抵消层130的厚度与核心层111的厚度的比值(T1/T2)例如介于0.18-1.152之间。图3C中应力抵消层130的厚度主要取决于((上导电层铜厚度×残铜率×铜密度)-(下导电层铜厚度×残铜率×铜密度))/((胶含量×胶密度)+(玻纤含量×玻纤密度))以及介电材料层113的厚度,其算式如上所述。在本实施例中,由于二个上导电层112、114中位于下方的第一上导电层112与下导电层115的应力相互抵消,因此只要考虑第二上导电层114及介电材料层113产生的非对称应力。此外,当介电材料层113的厚度增加(例如2层或3层)时,应力抵消层130的厚度也需相对增加,才能达到应力平衡,如上所述。
请参照图3D,其绘示一种内埋元件封装结构103,包括一线路基板110、一内埋元件120以及一应力抵消层130。线路基板110具有一核心层111、一上导电层112以及二层下导电层115、116。上导电层112设置于核心层111的上方,此二层下导电层115、116位于核心层111的下方。上导电层112与此二层下导电层115、116之间例如以贯穿核心层111的导电柱C1以及贯穿应力抵消层130的导电柱C2相互导通。应力抵消层130设置于此二层下导电层115、116之间,且应力抵消层130与此二层下导电层115、116均位于核心层111的相同侧。
图3D中的非对称线路结构有一上导电层112以及两层下导电层115、116,分别位于内埋元件120的上方及下方。第一下导电层115虽然位于内埋元件120的下方,但其对线路基板110产生向下弯的张应力,而第二下导电层116对线路基板110产生向上弯的张应力,两者的应力可抵消。因此,本实施例中,应力抵消层130的厚度主要取决于上导电层112的残铜率与厚度以及核心层111的厚度。此外,下导电层115的数量不限定只有两层,亦可两层以上。
根据图2中的数值可知,图3D中应力抵消层130的厚度(以T1表示于图2中)例如介于81-339(+/-12)微米之间,且应力抵消层130的厚度与核心层111的厚度的比值(T1/T2)例如介于0.59-2.90之间。图3D中应力抵消层130的厚度主要取决于((上导电层铜厚度×残铜率×铜密度)+(第一下导电层铜厚度×残铜率×铜密度)-(第二下导电层铜厚度×残铜率×铜密度)+(核心层的厚度))/((胶含量×胶密度)+(玻纤含量×玻纤密度))以及介电材料层113的厚度,其算式如上所述。在本实施例中,由于第一下导电层115与第二下导电层116的应力相互抵消,因此只要考虑上导电层112及核心层111产生的非对称应力。
请参照图4,根据上述内容,本发明提出一种内埋式面封装基板200,其包括多个线路基板单元210、多个内埋元件220以及一应力抵消层230。多个线路基板单元210可经由切割而分为多个线路基板110,如图3A至图3D所示。内埋式面封装基板200可视为上述内埋元件封装结构100-103的半成品。
各个线路基板单元210具有一核心层211以及一非对称线路结构212(仅绘示一层)。核心层211具有一第一厚度,非对称线路结构212如同图3A至图3D所示,在此不再一一绘示,其中非对称线路结构212于内埋元件220的上方及下方产生一非对称应力分布,导致内埋式面封装基板200翘曲。
此外,内埋元件220设置于各个线路基板单元210的核心层211中。应力抵消层130设置于核心层211的一侧,用以平衡非对称线路结构212的应力分布,其中应力抵消层230具有抑制基板翘曲的一第二厚度,使内埋式面封装基板200的翘曲量小于5mm以下。
在一实施例中,内埋式面封装基板200的长度尺寸及宽度尺寸为240.5mmх95mm或更大。当内埋式面封装基板200的翘曲量大于5mm时,内埋式面封装基板200的平整度不够,无法进行锡膏印刷制程或回焊制程,故无法制作锡球240(参见图5D)或无法回焊焊球240使其固定在线路基板单元210上。此外,当内埋式面封装基板200的翘曲量大于5mm时,也不利于将内埋式面封装基板200切割为多个线路基板,因而影响封装成品的质量。另外,本实施例采用非对称线路结构212,相对于传统的对称线路结构(例如2L+2L或1L+1L组合),还可减少至少一层导电层的数量以及减少图案化一层导电层的步骤,因此本实施例的封装结构的生产成本相对减少。
请参照图5A至图5E,根据上述内容,本发明提出一种内埋元件封装结构的制造方法如下。在图5A中,先以计算机仿真结果确认内埋元件封装结构的整体结构及其应力分布之后,决定一应力抵消层230的所需厚度。在图5B中,将一绝缘材料211’设置于应力抵消层230上。在图5C中,设置一电子元件于绝缘材料211’上并以另一绝缘材料211”覆盖,以形成一内埋元件120于核心层211中,其中核心层211具有一第一厚度,应力抵消层230具有一第二厚度。在图5D中,形成一非对称线路结构212于核心层211上,并与内埋元件220电性连接。非对称线路结构212不限定只有一层,亦可具有多层上导电层及/或多层下导电层。当非对称线路结构212具有下导电层时,可先形成下导电层于应力抵消层230上,再形成核心层211于下导电层上。在图5E中,当形成焊球240于内埋式面封装基板200之后,再将各个线路基板单元210切开,以形成多个内埋元件封装结构201。
在一实施例中,电子元件例如为半导体芯片、驱动芯片、控制芯片等主动元件或电阻、电感、电容之类的被动元件。
在上述的制造方法的一实施例中,可先形成一非对称线路结构于电子元件的上方及下方之后,再将一应力抵消层230设置于核心层211的一侧;或者,可将一应力抵消层230设置于核心层211的一侧之后,再形成一非对称线路结构于电子元件的上方及下方,本发明对此不加以限制。
综上所述,虽然本发明已以实施例公开如上,然其并非用以限定本发明。本发明所属技术领域的普通技术人员在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当视权利要求书所界定者为准。
Claims (25)
1.一种内埋元件封装结构,其特征在于,包括:
一线路基板,具有一核心层以及一非对称线路结构,该核心层具有一第一厚度;
一内埋元件,设置于该核心层中;以及
一应力抵消层,设置于该核心层的一侧,该应力抵消层具有一第二厚度,该第二厚度介于4~351微米之间。
2.如权利要求1所述的结构,其特征在于,该应力抵消层为包含玻纤的介电材料层。
3.如权利要求1所述的结构,其特征在于,该核心层具有相对的一第一表面以及一第二表面,该非对称线路结构包含一上导电层,该上导电层设置于该第一表面,且与该内埋元件电性连接。
4.如权利要求1所述的结构,其特征在于,该核心层具有相对的一第一表面以及一第二表面,该非对称线路结构包含至少二层的上导电层以及至少一介电材料层,该至少二层的上导电层设置于该第一表面,且与该内埋元件电性连接,该至少一介电材料层设置于该至少二层的上导电层之间。
5.如权利要求4所述的结构,其特征在于,该非对称线路结构更包含一下导电层,设置于该第二表面。
6.如权利要求1所述的结构,其特征在于,该核心层具有相对的一第一表面以及一第二表面,该非对称线路结构包含一上导电层、至少二层的下导电层以及至少一介电材料层,该上导电层设置于该第一表面,且与该内埋元件电性连接,该至少二层的下导电层设置于该第二表面,且该至少一介电材料层设置于该至少二层的下导电层之间。
7.如权利要求6所述的结构,其特征在于,以该应力抵消层为该至少一介电材料层。
8.如权利要求1所述的结构,其特征在于,该第二厚度与该第一厚度的比值介于0.03~2.9之间。
9.如权利要求3所述的结构,其特征在于,该第二厚度与该第一厚度的比值介于0.03~1.17之间。
10.如权利要求4所述的结构,其特征在于,该第二厚度与该第一厚度的比值介于0.42~2.58之间。
11.如权利要求5所述的结构,其特征在于,该第二厚度与该第一厚度的比值介于0.18~1.152之间。
12.如权利要求6所述的结构,其特征在于,该第二厚度与该第一厚度的比值介于0.57~2.9之间。
13.一种内埋式面封装基板,其特征在于,包括:
多个线路基板单元,各该线路基板单元具有一核心层以及一非对称线路结构,该核心层具有一第一厚度;
多个内埋元件,设置于该些线路基板单元的该核心层中;以及
一应力抵消层,设置于该些线路基板单元的一侧,其中该应力抵消层具有一第二厚度,该内埋式面封装基板的翘曲量小于5mm。
14.如权利要求13所述的基板,其特征在于,该非对称线路结构包含一上导电层,设置于该核心层的一侧并与该内埋元件电性连接,其中该应力抵消层的该第二厚度取决于该上导电层的残铜率及厚度。
15.如权利要求13所述的基板,其特征在于,该非对称线路结构包含至少二层上导电层以及至少一介电材料层,该至少二层上导电层设置于该核心层的另一侧并与该内埋元件电性连接,该至少一介电材料层设置于该至少二层上导电层之间,其中该应力抵消层的该第二厚度取决于该至少二层上导电层的残铜率及厚度与该至少一介电材料层的厚度。
16.如权利要求15所述的基板,其特征在于,该非对称线路结构更包含一下导电层,与该应力抵消层同侧设置于该核心层上,该应力抵消层的该第二厚度更进一步取决于该下导电层的残铜率及厚度。
17.如权利要求13所述的基板,其特征在于,该非对称线路结构包含一上导电层以及至少二层下导电层,该应力抵消层设置于该至少二层的下导电层之间,其中该应力抵消层的该第二厚度取决于该上导电层及该至少二层下导电层的残铜率及厚度与该核心层的该第一厚度。
18.如权利要求13所述的基板,其特征在于,该第二厚度与该第一厚度的比值介于0.03~2.9之间。
19.如权利要求14所述的基板,其特征在于,该第二厚度与该第一厚度的比值介于0.03~1.17之间。
20.如权利要求15所述的基板,其特征在于,该第二厚度与该第一厚度的比值介于0.42~2.58之间。
21.如权利要求16所述的基板,其特征在于,该第一厚度与该第二厚度的比值介于0.18~1.152之间。
22.如权利要求17所述的基板,其特征在于,该第一厚度与该第二厚度的比值介于0.57~2.9之间。
23.一种内埋元件封装结构的制造方法,其特征在于,包括:
设置一应力抵消层于一核心层的一侧,该核心层具有一第一厚度,该应力抵消层具有一第二厚度;
将一电子元件设置于该核心层中;以及
形成一非对称的线路结构于该电子元件的上方及下方。
24.如权利要求23所述的方法,其特征在于,该第一厚度与该第二厚度的比值介于0.03~2.9之间。
25.如权利要求23所述的方法,其特征在于,该第二厚度取决于该非对称的线路结构各导电层的残铜率与厚度。
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