TWI645519B - 元件內埋式封裝載板及其製作方法 - Google Patents

元件內埋式封裝載板及其製作方法 Download PDF

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Publication number
TWI645519B
TWI645519B TW106118292A TW106118292A TWI645519B TW I645519 B TWI645519 B TW I645519B TW 106118292 A TW106118292 A TW 106118292A TW 106118292 A TW106118292 A TW 106118292A TW I645519 B TWI645519 B TW I645519B
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Taiwan
Prior art keywords
layer
patterned conductive
conductive layer
insulating layer
component
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TW106118292A
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English (en)
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TW201903981A (zh
Inventor
楊景筌
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旭德科技股份有限公司
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Priority to TW106118292A priority Critical patent/TWI645519B/zh
Priority to CN201710616762.8A priority patent/CN108987371A/zh
Priority to US15/890,373 priority patent/US10798822B2/en
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Publication of TWI645519B publication Critical patent/TWI645519B/zh
Publication of TW201903981A publication Critical patent/TW201903981A/zh

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    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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Abstract

一種元件內埋式封裝載板，包括一核心層、至少一電子元件、一第一絕緣層、一第二絕緣層、一第三圖案化導電層、一第四圖案化導電層、多個導電盲孔結構、一第一保護層以及一第二保護層。電子元件配置於核心層的一開口內。第一絕緣層與第二絕緣層完全填滿開口且完全包覆電子元件。導電盲孔結構連接第三、第四圖案化導電層與核心層的多個導電通孔結構，以及第三、第四圖案化導電層與電子元件。第一保護層覆蓋第三圖案化導電層且具有一第一粗糙表面。第二保護層覆蓋第四圖案化導電層且具有一第二粗糙表面。

Description

元件內埋式封裝載板及其製作方法
本發明是有關於一種封裝載板及其製作方法，且特別是有關於一種元件內埋式封裝載板及其製作方法。
近年來，隨著電子技術的日新月異，高科技電子產業的相繼問世，使得高速處理化、多功能化、高密度化、小型輕量化及低價化之電子產品不斷地推陳出新。在這些電子產品內通常會配置一封裝載板，此封裝載板除了具有導電線路以外，亦可承載例如是電容器、電感器、電阻器或是IC晶片之電子元件，以作為電子產品的資料處理單元。然而，電子元件若全部配置於封裝載板上，則易產生承載面積增加與佈線空間降低的問題，且無法滿足市面上對電子產品之小型輕量化的需求。因此，如何將電子元件內埋於封裝載板中以降低封裝載板的厚度與增加佈線空間，儼然成為設計者在研發上關注的議題之一。
本發明提供一種元件內埋式封裝載板，具有較薄的封裝厚度。
本發明還提供一種元件內埋式封裝載板的製作方法，用以製作出上述的元件內埋式封裝載板。
本發明的元件內埋式封裝載板，其包括一核心層、至少一電子元件、一第一絕緣層、一第二絕緣層、一第三圖案化導電層、一第四圖案化導電層、多個導電盲孔結構、一第一保護層以及一第二保護層。核心層包括一介電層、一開口、一第一圖案化導電層、一第二圖案化導電層以及多個導電通孔結構。介電層具有彼此相對的一上表面與一下表面。開口貫穿介電層。第一圖案化導電層位於上表面上，而第二圖案化導電層位於下表面上。導電通孔結構貫穿介電層且連接第一圖案化導電層與第二圖案化導電層。電子元件配置於核心層的開口內。第一絕緣層覆蓋第一圖案化導電層與介電層的上表面且填充於開口內。第二絕緣層覆蓋第二圖案化導電層與介電層的下表面且填充於開口內。第一絕緣層與第二絕緣層完全填滿開口且完全包覆電子元件。第三圖案化導電層配置於第一絕緣層上。第四圖案化導電層配置於第二絕緣層上。導電盲孔結構連接第三圖案化導電層與導電通孔結構，第四圖案化導電層與導電通孔結構，第三圖案化導電層與電子元件以及第四圖案化導電層與電子元件。第一保護層覆蓋第三圖案化 導電層與部分第一絕緣層且具有一第一粗糙表面。第二保護層覆蓋第四圖案化導電層與部分第二絕緣層且具有一第二粗糙表面。
在本發明的一實施例中，上述的第一粗糙表面的粗糙度介於1微米至5微米之間。
在本發明的一實施例中，上述的第二粗糙表面的粗糙度介於1微米至5微米之間。
在本發明的一實施例中，上述的電子元件包括一主動元件或一被動元件。
本發明的元件內埋式封裝載板的製作方法，其包括以下步驟。形成一核心層，核心層包括一介電層、一開口、一第一圖案化導電層、一第二圖案化導電層以及多個導電通孔結構。介電層具有彼此相對的一上表面與一下表面。開口貫穿介電層。第一圖案化導電層位於上表面上，而第二圖案化導電層位於下表面上。導電通孔結構貫穿介電層且連接第一圖案化導電層與第二圖案化導電層。配置至少一電子元件於核心層的開口內。壓合一第一絕緣層以及位於第一絕緣層上的第一線路層於第一圖案化導電層上，其中第一絕緣層覆蓋第一圖案化導電層與介電層的上表面且填充於開口內。壓合一第二絕緣層以及位於第二絕緣層上的第二線路層於第二圖案化導電層上，其中第二絕緣層覆蓋第二圖案化導電層與介電層的下表面且填充於開口內。第一絕緣層與第二絕緣層完全填滿開口且完全包覆電子元件。形成多個導電盲孔結構、一第三圖案化導電層以及一第四圖案化導電層。第三圖案化 導電層位於第一絕緣層上且包括第一線路層，而第四圖案化導電層位於第二絕緣層上且包括第二線路層。導電盲孔結構連接第三圖案化導電層與導電通孔結構，第四圖案化導電層與導電通孔結構，第三圖案化導電層與電子元件以及第四圖案化導電層與電子元件。形成一第一保護層與一第二保護層。第一保護層具有一第一粗糙表面且覆蓋第三圖案化導電層與部分第一絕緣層。第二保護層具有一第二粗糙表面且覆蓋第四圖案化導電層與部分第二絕緣層。
在本發明的一實施例中，上述的形成核心層的步驟，包括：提供介電層、一第一銅箔層以及一第二銅箔層。第一銅箔層配置於介電層的上表面上，而第二銅箔層配置於介電層的下表面上。形成多個貫孔，貫孔貫穿介電層、第一銅箔層與第二銅箔層。形成一導電材料層於第一銅箔層與第二銅箔層上，其中導電材料層填滿貫孔且覆蓋第一銅箔層與第二銅箔層。圖案化導電材料層、第一銅箔層與第二銅箔層，而定義出導電通孔結構、第一圖案化導電層與第二圖案化導電層。圖案化導電材料層、第一銅箔層與第二銅箔層之後，形成開口。
在本發明的一實施例中，上述的元件內埋式封裝載板的製作方法，更包括：於形成核心層之後且於配置電子元件之前，提供一支撐件以接觸第二圖案化導電層。於壓合第一絕緣層以及位於第一絕緣層上的第一線路層於第一圖案化導電層上之後，且於壓合第二絕緣層以及位於第二絕緣層上的第二線路層於第二圖 案化導電層上之前，移除支撐件以暴露出第二圖案化導電層。
在本發明的一實施例中，上述的形成導電盲孔結構、第三圖案化導電層以及第四圖案化導電層的步驟，包括：形成多個盲孔，盲孔由第一線路層延伸至第一圖案化導電層與電子元件，以及由第二線路層延伸至第二圖案化導電層與電子元件。形成一導電材料層於第一線路層與第二線路層上，其中導電材料層填滿盲孔且覆蓋第一線路層與第二線路層。圖案化導電材料層、第一線路層與第二線路層，而定義出導電盲孔結構、第三圖案化導電層以及第四圖案化導電層。
在本發明的一實施例中，上述的第一粗糙表面的粗糙度介於1微米至5微米之間。
在本發明的一實施例中，上述的第二粗糙表面的粗糙度介於1微米至5微米之間。
在本發明的一實施例中，上述的電子元件包括一主動元件或一被動元件。
本發明的元件內埋式封裝載板，其包括一元件內埋式封裝載板單元、一承載件、一第三絕緣層、一第四絕緣層、一第五圖案化導電層、一第六圖案化導電層以及多個導電連接結構。元件內埋式封裝單元具有一元件內埋層、一第一保護層以及一第二保護層。承載件具有一容納開口，而元件內埋式封裝載板單元配置於容納開口內。第三絕緣層覆蓋第一保護層與承載件且填充於容納開口內。第四絕緣層覆蓋第二保護層與承載件且填充於容納 開口內，其中第三絕緣層與第四絕緣層完全填滿容納開口且完全包覆元件內埋式封裝載板單元。第五圖案化導電層配置於第三絕緣層上。第六圖案化導電層配置於第四絕緣層上。導電連接結構連接第五圖案化導電層與導電盲孔結構，第六圖案化導電層與導電盲孔結構，第五圖案化導電層與承載件以及連接第六圖案化導電層與承載件。
在本發明的一實施例中，上述的元件內埋層包括一核心層、至少一電子元件、一第一絕緣層、一第二絕緣層、一第三圖案化導電層、一第四圖案化導電層以及多個導電盲孔結構。核心層包括一介電層、一開口、一第一圖案化導電層、一第二圖案化導電層以及多個導電通孔結構。介電層具有彼此相對的一上表面與一下表面。開口貫穿介電層。第一圖案化導電層位於上表面上，而第二圖案化導電層位於下表面上。導電通孔結構貫穿介電層且連接第一圖案化導電層與第二圖案化導電層。電子元件配置於核心層的開口內。第一絕緣層覆蓋第一圖案化導電層與介電層的上表面且填充於開口內。第二絕緣層覆蓋第二圖案化導電層與介電層的下表面且填充於開口內。第一絕緣層與第二絕緣層完全填滿開口且完全包覆電子元件。第三圖案化導電層配置於第一絕緣層上。第四圖案化導電層配置於第二絕緣層上。導電盲孔結構連接第三圖案化導電層與導電通孔結構，第四圖案化導電層與導電通孔結構，第三圖案化導電層與電子元件以及第四圖案化導電層與電子元件。第一保護層覆蓋第三圖案化導電層與部分第一絕緣層 且具有一第一粗糙表面。第二保護層覆蓋第四圖案化導電層與部分第二絕緣層且具有一第二粗糙表面。
在本發明的一實施例中，上述的第一粗糙表面的粗糙度介於1微米至5微米之間。
在本發明的一實施例中，上述的第二粗糙表面的粗糙度介於1微米至5微米之間。
在本發明的一實施例中，上述的電子元件包括一主動元件或一被動元件。
本發明的元件內埋式封裝載板的製作方法，其包括以下步驟。提供一承載件，承載件具有一容納開口。將一元件內埋式封裝載板單元配置於承載件的容納開口內，其中元件內埋式封裝載板單元具有一元件內埋層、一第一保護層以及一第二保護層。壓合一第三絕緣層及其上的一第三線路層於第一保護層上，其中第三絕緣層覆蓋第一保護層與承載件且填充於容納開口內。壓合一第四絕緣層及其上的一第四線路層於第二保護層上，其中第四絕緣層覆蓋第二保護層與承載件且填充於容納開口內。第三絕緣層與第四絕緣層完全填滿容納開口且完全包覆元件內埋式封裝載板單元。形成多個導電連接結構、一第五圖案化導電層以及一第六圖案化導電層。第五圖案化導電層位於第三絕緣層上。第六圖案化導電層位於第四絕緣層上。導電連接結構連接第五圖案化導電層與導電盲孔結構，第六圖案化導電層與導電盲孔結構，第五圖案化導電層與承載件以及第六圖案化導電層與承載件。
在本發明的一實施例中，上述的形成該元件內埋層的方法包括：形成一核心層，核心層包括一介電層、一開口、一第一圖案化導電層、一第二圖案化導電層以及多個導電通孔結構。介電層具有彼此相對的一上表面與一下表面。開口貫穿介電層。第一圖案化導電層位於上表面上，而第二圖案化導電層位於下表面上。導電通孔結構貫穿介電層且連接第一圖案化導電層與第二圖案化導電層。配置至少一電子元件於核心層的開口內。壓合一第一絕緣層以及位於第一絕緣層上的第一線路層於第一圖案化導電層上，其中第一絕緣層覆蓋第一圖案化導電層與介電層的上表面且填充於開口內。壓合一第二絕緣層以及位於第二絕緣層上的第二線路層於第二圖案化導電層上，其中第二絕緣層覆蓋第二圖案化導電層與介電層的下表面且填充於開口內。第一絕緣層與第二絕緣層完全填滿開口且完全包覆電子元件。形成多個導電盲孔結構、一第三圖案化導電層以及一第四圖案化導電層。第三圖案化導電層位於第一絕緣層上且包括第一線路層，而第四圖案化導電層位於第二絕緣層上且包括第二線路層。導電盲孔結構連接第三圖案化導電層與導電通孔結構，第四圖案化導電層與導電通孔結構，第三圖案化導電層與電子元件以及第四圖案化導電層與電子元件。形成一第一保護層與一第二保護層。第一保護層具有一第一粗糙表面且覆蓋第三圖案化導電層與部分第一絕緣層。第二保護層具有一第二粗糙表面且覆蓋第四圖案化導電層與部分第二絕緣層。核心層、電子元件、第一絕緣層、第二絕緣層、導電盲孔 結構、第三圖案化導電層、第四圖案化導電層、第一保護層以及第二保護層定義出一元件內埋式封裝載板單元。
在本發明的一實施例中，上述的第一粗糙表面的粗糙度介於1微米至5微米之間。
在本發明的一實施例中，上述的第二粗糙表面的粗糙度介於1微米至5微米之間。
在本發明的一實施例中，上述的電子元件包括一主動元件或一被動元件。
基於上述，由於本發明的元件內埋式封裝載板是將電子元件或元件內埋式封裝載板單元內埋於其內，因此除了可具有較薄的封裝厚度之外，亦可透過電子元件或元件內埋式封裝載板單元來提升元件內埋式封裝載板的效能。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
100、200‧‧‧元件內埋式封裝載板
100’‧‧‧元件內埋式封裝載板單元
102‧‧‧元件內埋層
110‧‧‧核心層
112‧‧‧介電層
112a‧‧‧上表面
112b‧‧‧下表面
113‧‧‧第一銅箔層
114‧‧‧開口
115‧‧‧第二銅箔層
116‧‧‧第一圖案化導電層
118‧‧‧第二圖案化導電層
120‧‧‧電子元件
120a‧‧‧頂表面
120b‧‧‧底表面
122‧‧‧第一電極墊
124‧‧‧第二電極墊
130‧‧‧第一絕緣層
135‧‧‧第一線路層
140‧‧‧第二絕緣層
145‧‧‧第二線路層
150‧‧‧第三圖案化導電層
160‧‧‧第四圖案化導電層
170‧‧‧導電盲孔結構
180‧‧‧第一保護層
182‧‧‧第一粗糙表面
190‧‧‧第二保護層
192‧‧‧第二粗糙表面
210‧‧‧承載件
212‧‧‧容納開口
220‧‧‧第三絕緣層
225‧‧‧第三線路層
230‧‧‧第四絕緣層
235‧‧‧第四線路層
240‧‧‧第五圖案化導電層
250‧‧‧第六圖案化導電層
260‧‧‧導電連接結構
B‧‧‧盲孔
C1、C2‧‧‧導電材料層
S、S’‧‧‧支撐件
T‧‧‧導電通孔結構
圖1繪示為本發明的一實施例一種元件內埋式封裝載板的剖面示意圖。
圖2A至圖2M繪示為本發明的一實施例的一種元件內埋式封裝載板的製作方法的剖面示意圖。
圖3繪示為本發明的另一實施例一種元件內埋式封裝載板的 剖面示意圖。
圖4A至圖4E繪示為本發明的另一實施例的一種元件內埋式封裝載板的製作方法的局部步驟的剖面示意圖。
圖1繪示為本發明的一實施例一種元件內埋式封裝載板的剖面示意圖。請參考圖1，在本實施例中，元件內埋式封裝載板100包括一元件內埋層102、一第一保護層180以及一第二保護層190，其中該元件內埋層102包括一核心層110、至少一電子元件120(圖1中僅示意地繪示一個)、一第一絕緣層130、一第二絕緣層140、一第三圖案化導電層150、一第四圖案化導電層160以及多個導電盲孔結構170。
詳細來說，本實施例的核心層110包括一介電層112、一開口114、一第一圖案化導電層116、一第二圖案化導電層118以及多個導電通孔結構T。介電層112具有彼此相對的一上表面112a與一下表面112b。開口114為一貫穿開口，貫穿介電層112。第一圖案化導電層116位於介電層112的上表面112a上，而第二圖案化導電層118位於介電層112的下表面112b上。導電通孔結構T貫穿介電層112且連接第一圖案化導電層116與第二圖案化導電層11g。
電子元件120配置於核心層110的開口114內，其中電子元件120例如是一主動元件，如電晶體；或者是，一被動元件， 如電阻、電容或電感。如圖1所示，電子元件120具有彼此相對的一頂表面120a與一底表面120b、一第一電極墊122與多個第二電極墊124，其中第一電極墊122配置於頂表面120a上，而第二電極墊124配置於底表面120b上。當然，於其他未繪示的實施例中，電子元件120的個數亦可為多個，且其可為主動元件、被動元件或主動元件與被動元件的組合。再者，於其他未繪示的實施例中，電子元件120亦可僅在一表面(頂表面120a或底表面120b)上設置電極墊，且不限定電極墊的數量為一個或多個。
請再參考圖1，本實施例的第一絕緣層130覆蓋第一圖案化導電層116與介電層112的上表面112a且填充於開口114內。第二絕緣層140覆蓋第二圖案化導電層118與介電層112的下表面112b且填充於開口114內。第一絕緣層130與第二絕緣層140完全填滿開口114且完全包覆電子元件120。第三圖案化導電層150配置於第一絕緣層130上，而第四圖案化導電層160配置於第二絕緣層140上。導電盲孔結構170連接第三圖案化導電層150與導電通孔結構T，第四圖案化導電層160與導電通孔結構T，第三圖案化導電層150與電子元件120的第一電極墊122以及第四圖案化導電層160與電子元件120的第二電極墊124。意即，本實施例透過導電盲孔結構170來結構性與電性連接第三圖案化導電層150與導電通孔結構T，結構性與電性連接第四圖案化導電層160與導電通孔結構T，結構性與電性連接第三圖案化導電層150與電子元件120的第一電極墊122以及結構性與電性連接第四圖 案化導電層160與電子元件120的第二電極墊124。
特別是，本實施例的第一保護層180覆蓋第三圖案化導電層150與部分第一絕緣層130，且第一保護層180具有一第一粗糙表面182，其中第一粗糙表面182的粗糙度例如是介於1微米至5微米之間，例如十點平均粗糙度(Rz)是介於1微米至5微米之間。第二保護層190覆蓋第四圖案化導電層160與部分第二絕緣層140，且第二保護層190具有一第二粗糙表面192，其中第二粗糙表面192的粗糙度例如是介於1微米至5微米之間例如十點平均粗糙度(Rz)是介於1微米至5微米之間。此處，第一保護層180與第二保護層190具有耐酸鹼與耐水洗的特性，可有效保護第三圖案化導電層150、第四圖案化導電層160、第一絕緣層130以及第二絕緣層140。
由於本實施例的元件內埋式封裝載板100是將電子元件120內埋於其內，因此相較於習知將電子元件設置在封裝載板上而言，本實施例的元件內埋式封裝載板100除了可具有較薄的封裝厚度之外，亦可透過內埋的電子元件120來提升元件內埋式封裝載板100的效能。
以上僅介紹本發明的元件內埋式封裝載板100的結構，並未介紹本發明的元件內埋式封裝載板100的製作方法。對此，以下將以圖1中的元件內埋式封裝載板100的結構作為舉例說明，並配合圖2A至圖2M對本發明的元件內埋式封裝載板100的製程進行詳細的說明。
圖2A至圖2M繪示為本發明的一實施例的一種元件內埋式封裝載板的製作方法的剖面示意圖。請先參考圖2A，依照本實施例的元件內埋式封裝載板100的製程，首先，提供介電層112、一第一銅箔層113以及一第二銅箔層115。第一銅箔層113配置於介電層112的上表面112a上且完全覆蓋上表面112a，而第二銅箔層115配置於介電層112的下表面112b上且完全覆蓋下表面112b。
接著，請參考圖2B，形成多個貫孔H，其中貫孔H貫穿介電層112、第一銅箔層113與第二銅箔層115。此處，形成貫孔H的方法例如機械鑽孔或雷射鑽孔，於此並不加以限制。
接著，請參考圖2C，形成一導電材料層C1於第一銅箔層113與第二銅箔層115上，其中導電材料層C1填滿貫孔H且覆蓋第一銅箔層113與第二銅箔層115。此處，導電材料層C1是完全覆蓋於第一銅箔層113與第二銅箔層115上，且導電材料層C1例如是透過電鍍的方式而形成於第一銅箔層113與第二銅箔層115上。
接著，請同時參考圖2C與圖2D，圖案化導電材料層C1、第一銅箔層113與第二銅箔層115，而定義出導電通孔結構T、第一圖案化導電層116與第二圖案化導電層118。由此可知，本實施例的第一圖案化導電層116具體化是由第一銅箔層113與導電材料層C1所組成，而第二圖案化導電層118具體化是由第二銅箔層115與導電材料層C1所組成。
接著，請參考圖2E，形成貫穿介電層112的開口114， 而完成一核心層110的製作。簡言之，本實施例所形成的核心層110包括介電層112、開口114、第一圖案化導電層116、第二圖案化導電層118以及導電通孔結構T。介電層112具有彼此相對的上表面112a與下表面112b，而開口114貫穿介電層110。第一圖案化導電層116位於上表面112a上，而第二圖案化導電層118位於下表面112b上。導電通孔結構T貫穿介電層112且連接第一圖案化導電層116與第二圖案化導電層118。
接著，請參考圖2F，提供一支撐件S以接觸第二圖案化導電層118。此處，支撐件S例如是一膠層，用以支撐核心層110的結構。舉例來說，所述膠層例如是具黏性的膠帶(tape)，其例如是由厚度為25um的聚醯亞胺(Polyimide)層與厚度為5um黏著層所組成。然本發明不以此為限，在其他實施例中，支撐件S可為其他適當種類的膠層。
接著，請參考圖2G，配置電子元件120於核心層110的開口114內。此處，電子元件120配置於核心層110的開口114內，且電子元件120的第二電極墊124位於支撐件S上，意即電子元件120被支撐件S所支撐。如圖2G所示，電子元件120的個數具體化為一個，其例如是一主動元件，如電晶體；或者是，一被動元件，如電阻、電容或電感。當然，於其他未繪示的實施例中，電子元件120的個數亦可為多個，且其可為主動元件、被動元件或主動元件與被動元件的組合。再者，於其他未繪示的實施例中，電子元件120亦可僅在一表面(頂表面120a或底表面120b) 上設置電極墊，且不限定電極墊的數量為一個或多個。
接著，請參考圖2H，壓合第一絕緣層130以及位於第一絕緣層130上的一第一線路層135於第一圖案化導電層116上，其中第一絕緣層130覆蓋第一圖案化導電層116與介電層112的上表面112a且填充於開口114內。此處，壓合第一絕緣層130以及位於第一絕緣層130上的第一線路層135於第一圖案化導電層116上的方法例如是熱壓合法，因此第一絕緣層130會因為熱壓的關係而填入開口114內。須說明的是，圖2H中所繪示的第一絕緣層130填入開口114內的位置深度僅為示意，並不限於此。
接著，請同時參考圖2H與圖2I，移除支撐件S以暴露出第二圖案化導電層118與電子元件120的第二電極墊124。此處，移除支撐件S的方法例如是使用自動化設備夾住支撐件S的一端，並以機械力將支撐件S撕除，比如是剝離法或掀離法。然本發明不以此為限，在其他實施例中，支撐件S可藉由其他適當方式被移除。
接著，請參考圖2J，壓合第二絕緣層140以及位於第二絕緣層140上的第二線路層145於第二圖案化導電層118上，其中第二絕緣層140覆蓋第二圖案化導電層118與介電層112的下表面112b且填充於開口114內。此處，壓合第二絕緣層140以及位於第二絕緣層140上的第二線路層145於第二圖案化導電層118上的方法例如是熱壓合法，因此第二絕緣層140會因為熱壓的關係而填入開口114內。特別是，第一絕緣層130與第二絕緣層140 完全填滿開口114且完全包覆電子元件120。
接著，請參考圖2K，形成多個盲孔B，其中盲孔B由第一線路層135延伸至第一圖案化導電層116與電子元件120的第一電極墊122，以及由第二線路層145延伸至第二圖案化導電層118與電子元件120的第二電極墊124。緊接著，形成一導電材料層C2於第一線路層135與第二線路層145上，其中導電材料層C2填滿盲孔B且覆蓋第一線路層135與第二線路層145。
之後，請同時參考圖2K與圖2L，圖案化導電材料層C2、第一線路層135與第二線路層145，而形成導電盲孔結構170、第三圖案化導電層150以及第四圖案化導電層160。此處，第三圖案化導電層150位於第一絕緣層130上，且第三圖案化導電層150具體化是由第一線路層135與導電材料層C2所組成。第四圖案化導電層160位於第二絕緣層140上，且第四圖案化導電層160具體化是由第二線路層145與導電材料層C2所組成。導電盲孔結構170連接第三圖案化導電層150與導電通孔結構T，第四圖案化導電層160與導電通孔結構T，第三圖案化導電層150與電子元件120的第一電極墊122以及第四圖案化導電層160與電子元件120的第二電極墊124。意即，本實施例透過導電盲孔結構170來結構性與電性連接第三圖案化導電層150與導電通孔結構T，結構性與電性連接第四圖案化導電層160與導電通孔結構T，結構性與電性連接第三圖案化導電層150與電子元件120的第一電極墊122以及結構性與電性連接第四圖案化導電層160與電子元件120的 第二電極墊124。以上述製程舉例說明，經過上述製程形成元件內埋層102。
最後，請參考圖2M，形成第一保護層180與第二保護層190，而元件內埋層102位於第一保護層180與第二保護層190之間，其中第一保護層180與第二保護層190較佳是具有耐酸鹼與耐水洗的特性，其材質例如是聚乙醯胺(Polyimide)、銲罩(solder mask)、覆樹脂銅箔(resin coated copper，RCC)、玻纖半固化樹脂(prepreg)、ABF膜(Ajinomoto Build-up Film)材料或其他適當材料等，但是不限於此材質，且形成第一保護層180與第二保護層190的方法包括塗佈法或壓合法，其中塗佈法使用之材質例如為聚乙醯胺、銲罩材料或其他適當材料，而壓合法使用之材質例如為銲罩、覆樹脂銅箔、玻纖半固化樹脂、ABF膜材料或其他適當材料。第一保護層180具有第一粗糙表面182且覆蓋第三圖案化導電層150與部分第一絕緣層130，其中第一粗糙表面182的粗糙度例如是介於1微米至5微米之間，例如十點平均粗糙度(Rz)是介於1微米至5微米之間。第二保護層190具有第二粗糙表面192且覆蓋第四圖案化導電層160與部分第二絕緣層140，其中第二粗糙表面192的粗糙度例如是介於1微米至5微米之間，例如十點平均粗糙度(Rz)是介於1微米至5微米之間。至此，已完成元件內埋式封裝載板100的製作。
由於本實施例第一保護層180是覆蓋第三圖案化導電層150與部分第一絕緣層130，而第二保護層190是覆蓋第四圖案化 導電層160與部分第二絕緣層140。因此，第一保護層180與第二保護層190可有效地保護第三圖案化導電層150與第四圖案化導電層160。此外，第一保護層180具有第一粗糙表面182，而第二保護層190具有第二粗糙表面192，因此後續將此內埋式封裝載板100置入另一承載板(未繪示)內時，可有效提高內埋式封裝載板100與承載板之間的接合力。
由於本實施例是透過二次壓合絕緣層的方式，即壓合第一絕緣層130與壓合第二絕緣層140的步驟，將電子元件120完全包覆，而形成元件內埋式封裝載板100。因此，相較於習知將電子元件設置在封裝載板上而言，本實施例的元件內埋式封裝載板100除了可具有較薄的封裝厚度之外，亦可透過內埋的電子元件120來提升元件內埋式封裝載板100的效能。
圖3繪示為本發明的另一實施例一種元件內埋式封裝載板的剖面示意圖。請參考圖3，本實施例的元件內埋式封裝載板200與圖1中的元件內埋式封裝載板100相似，差異之處在於：圖1中元件內埋式封裝載板100中內埋的是電子元件120，而元件內埋式封裝載板200中內埋的是一元件內埋式封裝載板單元100’。詳細來說，本實施例的元件內埋式封裝載板200包括元件內埋式封裝載板單元100’、一承載件210、一第三絕緣層220、一第四絕緣層230、一第五圖案化導電層240、一第六圖案化導電層250以及多個導電連接結構260。
具體來說，本實施例的元件內埋式封裝載板單元100’的 結構可與上述圖1的元件內埋式封裝載板100的結構相同，例如元件內埋式封裝載板單元100’具有一元件內埋層102、一第一保護層180以及一第二保護層190。承載件210具有一容納開口212，而元件內埋式封裝載板單元100’配置於容納開口212內。第三絕緣層220覆蓋元件內埋式封裝載板單元100’的第一保護層180與承載件210且填充於容納開口212內。第四絕緣層230覆蓋元件內埋式封裝載板單元100’的第二保護層190與承載件210且填充於容納開口212內，其中第三絕緣層220與第四絕緣層230完全填滿容納開口212且完全包覆元件內埋式封裝載板單元100’。第五圖案化導電層240配置於第三絕緣層220上，而第六圖案化導電層250配置於第四絕緣層230上。導電連接結構260連接第五圖案化導電層240與導電盲孔結構170，第六圖案化導電層250與導電盲孔結構170，第五圖案化導電層240與承載件210以及連接第六圖案化導電層250與承載件210。也就是說，本實施例透過導電連接結構260來結構性與電性連接第五圖案化導電層240與元件內埋式封裝載板單元100’的導電盲孔結構170，結構性與電性連接第六圖案化導電層250與元件內埋式封裝載板單元100’的導電盲孔結構170，結構性與電性連接第五圖案化導電層240與承載件210以及結構性與電性連接連接第六圖案化導電層250與承載件210。
圖4A至圖4E繪示為本發明的另一實施例的一種元件內埋式封裝載板的製作方法的局部步驟的剖面示意圖。在製程上， 於圖2M的步驟之後，即形成第一保護層180與第二保護層190之後，即可定義出元件內埋式封裝載板單元100’。接著，請參考圖4A，提供承載件210，其中承載件210具有容納開口212。提供一支撐件S’以接觸承載件210。此處，支撐件S’例如是一膠層，用以支撐承載件210的結構。舉例來說，所述膠層例如是具黏性的膠帶(tape)，其例如是由厚度為25um的聚醯亞胺(Polyimide)層與厚度為5um黏著層所組成。然本發明不以此為限，在其他實施例中，支撐件S’可為其他適當種類的膠層。
接著，請參考圖4B，將元件內埋式封裝載板單元100’配置於承載件210的容納開口212內，意即元件內埋式封裝載板單元100’被支撐件S’所支撐。接著，請參考圖4C，透過熱壓合的方式，壓合第三絕緣層220及其上的第三線路層225於元件內埋式封裝載板單元100’的第一保護層180上，其中第三絕緣層220覆蓋第一保護層180與承載件210且填充於容納開口212內。之後，移除支撐件S’以暴露出元件內埋式封裝載板單元100’。此處，移除支撐件S’的方法例如是使用自動化設備夾住支撐件S’的一端，並以機械力將支撐件S’撕除，比如是剝離法或掀離法。然本發明不以此為限，在其他實施例中，支撐件S’可藉由其他適當方式被移除。
請參考圖4D，壓合第四絕緣層230及其上的第四線路層235於第二保護層190上，其中第四絕緣層230覆蓋第二保護層190與承載件210且填充於容納開口212內。此處，第三絕緣層 220與第四絕緣層230完全包覆元件內埋式封裝載板單元100’且填滿容納開口212。之後，請參考圖4E，形成導電連接結構260、第五圖案化導電層240以及第六圖案化導電層250，其中形成導電連接結構260、第五圖案化導電層240以及第六圖案化導電層250可參考上述圖2K與圖2L的步驟，於此不再贅述。第五圖案化導電層240位於第三絕緣層220上，而第六圖案化導電層250位於第四絕緣層230上。導電連接結構260連接第五圖案化導電層240與導電盲孔結構170，第六圖案化導電層250與導電盲孔結構170，第五圖案化導電層240與承載件210以及第六圖案化導電層250與承載件210。至此，已完成元件內埋式封裝載板200的製作。簡言之，本實施例的元件內埋式封裝載板200是將以內埋有電子元件120的元件內埋式封裝載板單元100’內埋於其內，因此除了可有效降低整體元件內埋式封裝載板200的厚度之外，亦可有效提升元件內埋式封裝載板200的效能。此外，由於元件內埋式封裝載板單元100’的第一保護層180與第二保護層190分別具有第一粗糙表面182與第二粗糙表面192，因此可與第三絕緣層220與第四絕緣層230之間具有較佳的接合能力。
綜上所述，由於本發明的元件內埋式封裝載板是將電子元件或元件內埋式封裝在板單元內埋於其內，因此除了可具有較薄的封裝厚度之外，亦可透過電子元件或元件內埋式封裝載板單元來提升元件內埋式封裝載板的效能。
雖然本發明已以實施例揭露如上，然其並非用以限定本 發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。

Claims (21)

  1. 一種元件內埋式封裝載板，包括：一核心層，包括一介電層、一開口、一第一圖案化導電層、一第二圖案化導電層以及多個導電通孔結構，該介電層具有彼此相對的一上表面與一下表面，該開口貫穿該介電層，該第一圖案化導電層位於該上表面上，而該第二圖案化導電層位於該下表面上，該些導電通孔結構貫穿該介電層且連接該第一圖案化導電層與該第二圖案化導電層；至少一電子元件，配置於該核心層的該開口內；一第一絕緣層，覆蓋該第一圖案化導電層與該介電層的該上表面，且填充於該開口內；一第二絕緣層，覆蓋該第二圖案化導電層與該介電層的該下表面，且填充於該開口內，其中該第一絕緣層與該第二絕緣層完全填滿該開口且完全包覆該電子元件；一第三圖案化導電層，配置於該第一絕緣層上；一第四圖案化導電層，配置於該第二絕緣層上；多個導電盲孔結構，連接該第三圖案化導電層與該些導電通孔結構，該第四圖案化導電層與該些導電通孔結構，該第三圖案化導電層與該電子元件以及該第四圖案化導電層與該電子元件；一第一保護層，覆蓋該第三圖案化導電層與部分該第一絕緣層，且具有一第一粗糙表面；以及一第二保護層，覆蓋該第四圖案化導電層與部分該第二絕緣層，且具有一第二粗糙表面。
  2. 如申請專利範圍第1項所述的元件內埋式封裝載板，其中該第一粗糙表面的粗糙度介於1微米至5微米之間。
  3. 如申請專利範圍第1項所述的元件內埋式封裝載板，其中該第二粗糙表面的粗糙度介於1微米至5微米之間。
  4. 如申請專利範圍第1項所述的元件內埋式封裝載板，其中該電子元件包括一主動元件或一被動元件。
  5. 一種元件內埋式封裝載板的製作方法，包括：形成一核心層，該核心層包括一介電層、一開口、一第一圖案化導電層、一第二圖案化導電層以及多個導電通孔結構，該介電層具有彼此相對的一上表面與一下表面，該開口貫穿該介電層，該第一圖案化導電層位於該上表面上，而該第二圖案化導電層位於該下表面上，該些導電通孔結構貫穿該介電層且連接該第一圖案化導電層與該第二圖案化導電層；配置至少一電子元件於該核心層的該開口內；壓合一第一絕緣層以及位於該第一絕緣層上的第一線路層於該第一圖案化導電層上，其中該第一絕緣層覆蓋該第一圖案化導電層與該介電層的該上表面且填充於該開口內；壓合一第二絕緣層以及位於該第二絕緣層上的第二線路層於該第二圖案化導電層上，其中該第二絕緣層覆蓋該第二圖案化導電層與該介電層的該下表面且填充於該開口內，該第一絕緣層與該第二絕緣層完全填滿該開口且完全包覆該電子元件；形成多個導電盲孔結構、一第三圖案化導電層以及一第四圖案化導電層，該第三圖案化導電層位於該第一絕緣層上且包括該第一線路層，而該第四圖案化導電層位於該第二絕緣層上且包括該第二線路層，該些導電盲孔結構連接該第三圖案化導電層與該些導電通孔結構，該第四圖案化導電層與該些導電通孔結構，該第三圖案化導電層與該電子元件以及該第四圖案化導電層與該電子元件；以及形成一第一保護層與一第二保護層，該第一保護層具有一第一粗糙表面且覆蓋該第三圖案化導電層與部分該第一絕緣層，而該第二保護層具有一第二粗糙表面且覆蓋該第四圖案化導電層與部分該第二絕緣層。
  6. 如申請專利範圍第5項所述的元件內埋式封裝載板的製作方法，其中形成該核心層的步驟，包括：提供該介電層、一第一銅箔層以及一第二銅箔層，該第一銅箔層配置於該介電層的該上表面上，而該第二銅箔層配置於該介電層的該下表面上；形成多個貫孔，該些貫孔貫穿該介電層、該第一銅箔層與該第二銅箔層；形成一導電材料層於該第一銅箔層與該第二銅箔層上，其中該導電材料層填滿該些貫孔且覆蓋該第一銅箔層與該第二銅箔層；圖案化該導電材料層、該第一銅箔層與該第二銅箔層，而定義出該些導電通孔結構、該第一圖案化導電層與該第二圖案化導電層；以及圖案化該導電材料層、該第一銅箔層與該第二銅箔層之後，形成該開口。
  7. 如申請專利範圍第5項所述的元件內埋式封裝載板的製作方法，更包括：於形成該核心層之後且於配置該電子元件之前，提供一支撐件以接觸該第二圖案化導電層；以及於壓合該第一絕緣層以及位於該第一絕緣層上的該第一線路層於該第一圖案化導電層上之後，且於壓合該第二絕緣層以及位於該第二絕緣層上的該第二線路層於該第二圖案化導電層上之前，移除該支撐件以暴露出該第二圖案化導電層。
  8. 如申請專利範圍第5項所述的元件內埋式封裝載板的製作方法，其中形成該些導電盲孔結構、該第三圖案化導電層以及該第四圖案化導電層的步驟，包括：形成多個盲孔，該些盲孔由該第一線路層延伸至該第一圖案化導電層與該電子元件，以及由該第二線路層延伸至該第二圖案化導電層與該電子元件；形成一導電材料層於該第一線路層與該第二線路層上，其中該導電材料層填滿該盲孔且覆蓋該第一線路層與該第二線路層；以及圖案化該導電材料層、該第一線路層與該第二線路層，而定義出該些導電盲孔結構、該第三圖案化導電層以及該第四圖案化導電層。
  9. 如申請專利範圍第5項所述的元件內埋式封裝載板的製作方法，其中該第一粗糙表面的粗糙度介於1微米至5微米之間。
  10. 如申請專利範圍第5項所述的元件內埋式封裝載板的製作方法，其中該第二粗糙表面的粗糙度介於1微米至5微米之間。
  11. 如申請專利範圍第5項所述的元件內埋式封裝載板的製作方法，其中該電子元件包括一主動元件或一被動元件。
  12. 一種元件內埋式封裝載板，包括：一元件內埋式封裝載板單元，具有一元件內埋層、一第一保護層與一第二保護層，其中該元件內埋層位於該第一保護層與該第二保護層之間，且該第一保護層具有一第一粗糙表面、該第二保護層具有一第二粗糙表面；一承載件，具有一容納開口，而該元件內埋式封裝載板單元配置於該容納開口內；一第三絕緣層，覆蓋該第一保護層與該承載件且填充於該容納開口內；一第四絕緣層，覆蓋該第二保護層與該承載件且填充於該容納開口內，其中該第三絕緣層與該第四絕緣層完全填滿該容納開口且完全包覆該元件內埋式封裝載板單元；一第五圖案化導電層，配置於該第三絕緣層上；一第六圖案化導電層，配置於該第四絕緣層上；以及多個導電連接結構，連接該第五圖案化導電層與該些導電盲孔結構，該第六圖案化導電層與該些導電盲孔結構，該第五圖案化導電層與該承載件以及該第六圖案化導電層與該承載件。
  13. 如申請專利範圍第12項所述的元件內埋式封裝載板，其中該元件內埋層包括：一核心層，包括一介電層、一開口、一第一圖案化導電層、一第二圖案化導電層以及多個導電通孔結構，該介電層具有彼此相對的一上表面與一下表面，該開口貫穿該介電層，該第一圖案化導電層位於該上表面上，而該第二圖案化導電層位於該下表面上，該些導電通孔結構貫穿該介電層且連接該第一圖案化導電層與第二圖案化導電層；至少一電子元件，配置於該核心層的該開口內；一第一絕緣層，覆蓋該第一圖案化導電層與該介電層的該上表面，且填充於該開口內；一第二絕緣層，覆蓋該第二圖案化導電層與該介電層的該下表面，且填充於該開口內，其中該第一絕緣層與該第二絕緣層完全填滿該開口且完全包覆該電子元件；一第三圖案化導電層，配置於該第一絕緣層上；一第四圖案化導電層，配置於該第二絕緣層上；以及多個導電盲孔結構，連接該第三圖案化導電層與該些導電通孔結構，該第四圖案化導電層與該些導電通孔結構，該第三圖案化導電層與該電子元件以及該第四圖案化導電層與該電子元件，其中，該第一保護層覆蓋該第三圖案化導電層與部分該第一絕緣層，以及該第二保護層覆蓋該第四圖案化導電層與部分該第二絕緣層。
  14. 如申請專利範圍第12項所述的元件內埋式封裝載板，其中該第一粗糙表面的粗糙度介於1微米至5微米之間。
  15. 如申請專利範圍第12項所述的元件內埋式封裝載板，其中該第二粗糙表面的粗糙度介於1微米至5微米之間。
  16. 如申請專利範圍第12項所述的元件內埋式封裝載板，其中該電子元件包括一主動元件或一被動元件。
  17. 一種元件內埋式封裝載板的製作方法，包括：提供一承載件，該承載件具有一容納開口；將一元件內埋式封裝載板單元配置於該承載件的該容納開口內，該元件內埋式封裝載板單元具有一元件內埋層、一第一保護層與一第二保護層；壓合一第三絕緣層及其上的一第三線路層於該第一保護層上，其中該第三絕緣層覆蓋該第一保護層與該承載件且填充於該容納開口內；壓合一第四絕緣層及其上的一第四線路層於該第二保護層上，其中該第四絕緣層覆蓋該第二保護層與該承載件且填充於該容納開口內，該第三絕緣層與該第四絕緣層完全填滿該容納開口且完全包覆該元件內埋式封裝載板單元；以及形成多個導電連接結構、一第五圖案化導電層以及一第六圖案化導電層，該第五圖案化導電層位於該第三絕緣層上，而該第六圖案化導電層位於該第四絕緣層上，該些導電連接結構連接該第五圖案化導電層與該些導電盲孔結構，該第六圖案化導電層與該些導電盲孔結構，該第五圖案化導電層與該承載件以及該第六圖案化導電層與該承載件。
  18. 如申請專利範圍第17項所述的元件內埋式封裝載板的製作方法，其中形成該元件內埋層的方法包括：形成一核心層，該核心層包括一介電層、一開口、一第一圖案化導電層、一第二圖案化導電層以及多個導電通孔結構，該介電層具有彼此相對的一上表面與一下表面，該開口貫穿該介電層，該第一圖案化導電層位於該上表面上，而該第二圖案化導電層位於該下表面上，該些導電通孔結構貫穿該介電層且連接該第一圖案化導電層與該第二圖案化導電層；配置至少一電子元件於該核心層的該開口內；壓合一第一絕緣層以及位於該第一絕緣層上的第一線路層於該第一圖案化導電層上，其中該第一絕緣層覆蓋該第一圖案化導電層與該介電層的該上表面且填充於該開口內；壓合一第二絕緣層以及位於該第二絕緣層上的第二線路層於該第二圖案化導電層上，其中該第二絕緣層覆蓋該第二圖案化導電層與該介電層的該下表面且填充於該開口內，該第一絕緣層與該第二絕緣層完全填滿該開口且完全包覆該電子元件；以及形成多個導電盲孔結構、一第三圖案化導電層以及一第四圖案化導電層，該第三圖案化導電層位於該第一絕緣層上且包括該第一線路層，而該第四圖案化導電層位於該第二絕緣層上且包括該第二線路層，該些導電盲孔結構連接該第三圖案化導電層與該些導電通孔結構，該第四圖案化導電層與該些導電通孔結構，該第三圖案化導電層與該電子元件以及該第四圖案化導電層與該電子元件，其中，該第一保護層與該第二保護層，該第一保護層具有一第一粗糙表面且覆蓋該第三圖案化導電層與部分該第一絕緣層，而該第二保護層具有一第二粗糙表面且覆蓋該第四圖案化導電層與部分該第二絕緣層，且該核心層、該電子元件、該第一絕緣層、該第二絕緣層、該些導電盲孔結構、該第三圖案化導電層、該第四圖案化導電層、該第一保護層以及該第二保護層定義出該元件內埋式封裝載板單元。
  19. 如申請專利範圍第17項所述的元件內埋式封裝載板的製作方法，其中該第一粗糙表面的粗糙度介於1微米至5微米之間。
  20. 如申請專利範圍第17項所述的元件內埋式封裝載板的製作方法，其中該第二粗糙表面的粗糙度介於1微米至5微米之間。
  21. 如申請專利範圍第17項所述的元件內埋式封裝載板的製作方法，其中該電子元件包括一主動元件或一被動元件。
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