JP6478309B2 - 多層基板及び多層基板の製造方法 - Google Patents
多層基板及び多層基板の製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 82
- 238000000034 method Methods 0.000 title claims description 68
- 238000004519 manufacturing process Methods 0.000 title claims description 40
- 230000003014 reinforcing effect Effects 0.000 claims description 79
- 239000000463 material Substances 0.000 claims description 20
- 238000000926 separation method Methods 0.000 claims description 19
- 239000011162 core material Substances 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 9
- 239000012530 fluid Substances 0.000 claims description 7
- 229920003002 synthetic resin Polymers 0.000 claims description 7
- 239000000057 synthetic resin Substances 0.000 claims description 7
- 230000002787 reinforcement Effects 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 description 23
- 239000002184 metal Substances 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 230000010354 integration Effects 0.000 description 6
- 239000003365 glass fiber Substances 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
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- 239000010432 diamond Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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Description
11 外部電極
12 接着剤
100、200、300 多層基板
110 補強層
111 第1補強層
115 第2補強層
120 第1絶縁層
121 キャビティ
130 第2絶縁層
140 第3絶縁層
141 第3上部絶縁層
142 第3下部絶縁層
P1 第1回路パターン層
P2 第2回路パターン層
P3 第3回路パターン層
P4 第4回路パターン層
P5 第5回路パターン層
P1´ 第1金属層
P2´ 第2金属層
P3´ 第3金属層
V1 第1ビア
V2 第2ビア
V3 第3ビア
V4 第4ビア
V5 第5ビア
V6 第6ビア
SR ソルダーレジスト
SB ソルダーボール
312 放熱接着剤
412 非伝導性接着剤
DC 分離層
Claims (7)
- 一面に第3回路パターン層が備えられた第1補強層に、外部電極が備えられた電子部品を実装する段階と、
前記第3回路パターン層及び前記第1補強層を覆うとともに、前記電子部品の側面に接触される第2絶縁層を、前記第1補強層上に形成する段階と、
前記電子部品の少なくとも一部が挿入されるキャビティが備えられた第1絶縁層を前記第2絶縁層上に積層する段階と、
前記電子部品及び前記第1絶縁層を覆うとともに、前記キャビティと前記電子部品との間に充填される第3上部絶縁層を、前記第1絶縁層上に形成する段階と、
少なくとも一つの回路パターンが第3ビアにより前記外部電極と直接連結される第5回路パターン層を前記第3上部絶縁層上に形成する段階と、
前記第5回路パターン層及び前記第3上部絶縁層を覆う第3下部絶縁層を前記第3上部絶縁層上に形成する段階と、
少なくとも一つの回路パターンが第4ビアにより前記第5回路パターン層の少なくとも一つの回路パターンと直接連結される第4回路パターン層を前記第3下部絶縁層上に形成する段階と、
前記第4回路パターン層及び前記第3下部絶縁層を覆う第2補強層を前記第3下部絶縁層上に形成する段階と、を含み、
前記第1補強層及び前記第2補強層は、多層基板の反りを減少させるためのものである、多層基板の製造方法。 - 前記第1補強層及び前記第2補強層は、熱膨張係数が11ppm/℃以下である条件及び弾性係数が25GPa以上である条件のうち少なくとも一つの条件を満たす材料からなる、請求項1に記載の多層基板の製造方法。
- 前記第1補強層及び前記第2補強層はガラス材料からなる、請求項2に記載の多層基板の製造方法。
- 前記第1補強層は分離層の上面及び下面にそれぞれ形成され、前記分離層を中心として上面方向及び下面方向に前記多層基板の製造方法が夫々行われた後に、前記分離層から分離される、請求項2に記載の多層基板の製造方法。
- 前記第3上部絶縁層及び前記第3下部絶縁層は、芯材を含まない流動性合成樹脂を硬化させることで形成される、請求項2に記載の多層基板の製造方法。
- 前記第2絶縁層は、芯材を含む流動性合成樹脂を硬化させることで形成される、請求項2に記載の多層基板の製造方法。
- 前記第5回路パターン層を前記第3上部絶縁層上に形成する段階は、
前記第5回路パターン層の少なくとも一つの回路パターンを前記第3回路パターン層の少なくとも一つの回路パターンと直接連結させる第5ビアを形成する段階を含む、請求項2に記載の多層基板の製造方法。
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KR20120157886 | 2012-12-31 | ||
KR10-2012-0157886 | 2012-12-31 | ||
KR10-2013-0137665 | 2013-11-13 | ||
KR1020130137665A KR101522786B1 (ko) | 2012-12-31 | 2013-11-13 | 다층기판 및 다층기판 제조방법 |
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JP6478309B2 true JP6478309B2 (ja) | 2019-03-06 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US9070653B2 (en) * | 2013-01-15 | 2015-06-30 | Freescale Semiconductor, Inc. | Microelectronic assembly having a heat spreader for a plurality of die |
US9691726B2 (en) * | 2014-07-08 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming fan-out package structure |
JP6742682B2 (ja) * | 2014-09-03 | 2020-08-19 | 太陽誘電株式会社 | 多層配線基板 |
DE102014118462A1 (de) * | 2014-12-11 | 2016-06-16 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Semiflexible Leiterplatte mit eingebetteter Komponente |
US10356916B2 (en) * | 2015-06-29 | 2019-07-16 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board with inner layer and outer layers and method of manufacturing the same |
US10276467B2 (en) * | 2016-03-25 | 2019-04-30 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
KR101999625B1 (ko) * | 2016-03-25 | 2019-07-17 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
US10600748B2 (en) | 2016-06-20 | 2020-03-24 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
US9935068B2 (en) | 2016-06-21 | 2018-04-03 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
KR101982049B1 (ko) | 2016-11-23 | 2019-05-24 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
KR101983188B1 (ko) | 2016-12-22 | 2019-05-28 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
KR101901712B1 (ko) | 2017-10-27 | 2018-09-27 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
KR102061851B1 (ko) * | 2017-11-29 | 2020-01-02 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
KR101912290B1 (ko) | 2017-12-06 | 2018-10-29 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
KR102163059B1 (ko) | 2018-09-07 | 2020-10-08 | 삼성전기주식회사 | 연결구조체 내장기판 |
US11277917B2 (en) | 2019-03-12 | 2022-03-15 | Advanced Semiconductor Engineering, Inc. | Embedded component package structure, embedded type panel substrate and manufacturing method thereof |
KR20210073802A (ko) * | 2019-12-11 | 2021-06-21 | 삼성전기주식회사 | 전자부품 내장기판 |
KR20210078951A (ko) * | 2019-12-19 | 2021-06-29 | 삼성전기주식회사 | 전자부품 내장기판 |
KR20220001634A (ko) * | 2020-06-30 | 2022-01-06 | 삼성전기주식회사 | 인쇄회로기판 |
KR20220093507A (ko) * | 2020-12-28 | 2022-07-05 | 삼성전기주식회사 | 패키지 내장기판 |
CN113068326B (zh) * | 2021-03-29 | 2022-09-30 | 北京小米移动软件有限公司 | 一种焊接质量处理方法及装置、电路板 |
DE102021115848A1 (de) | 2021-06-18 | 2022-12-22 | Rolls-Royce Deutschland Ltd & Co Kg | Leiterplatte |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5950756A (ja) * | 1982-09-16 | 1984-03-23 | Mitsubishi Electric Corp | 電機巻線の製造方法 |
JP3094481B2 (ja) | 1991-03-13 | 2000-10-03 | 松下電器産業株式会社 | 電子回路装置とその製造方法 |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US6733907B2 (en) * | 1998-03-27 | 2004-05-11 | Siemens Westinghouse Power Corporation | Hybrid ceramic material composed of insulating and structural ceramic layers |
JP3672169B2 (ja) | 1999-03-05 | 2005-07-13 | 日本特殊陶業株式会社 | コンデンサ、コア基板本体の製造方法、及び、コンデンサ内蔵コア基板の製造方法 |
US6372999B1 (en) * | 1999-04-20 | 2002-04-16 | Trw Inc. | Multilayer wiring board and multilayer wiring package |
US6724638B1 (en) * | 1999-09-02 | 2004-04-20 | Ibiden Co., Ltd. | Printed wiring board and method of producing the same |
JP2001126767A (ja) * | 1999-10-28 | 2001-05-11 | Nec Mobile Energy Kk | 非水電解液二次電池 |
JP2001274556A (ja) * | 2000-03-23 | 2001-10-05 | Nec Corp | プリント配線板 |
JP3838250B2 (ja) * | 2004-09-02 | 2006-10-25 | 株式会社日立製作所 | 積層板及び多層プリント回路板 |
JP2007059821A (ja) * | 2005-08-26 | 2007-03-08 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
CN103298243B (zh) | 2006-07-14 | 2016-05-11 | 斯塔布科尔技术公司 | 具有构成电路一部分的核心层的增层印刷线路板衬底 |
JP5164403B2 (ja) * | 2006-09-13 | 2013-03-21 | 富士通株式会社 | コアレス多層配線基板および半導体装置、その製造方法 |
JP2009218545A (ja) | 2008-03-12 | 2009-09-24 | Ibiden Co Ltd | 多層プリント配線板及びその製造方法 |
CN102106198B (zh) | 2008-07-23 | 2013-05-01 | 日本电气株式会社 | 半导体装置及其制造方法 |
WO2010010910A1 (ja) * | 2008-07-23 | 2010-01-28 | 日本電気株式会社 | コアレス配線基板、半導体装置及びそれらの製造方法 |
JP2010251688A (ja) * | 2009-03-25 | 2010-11-04 | Nec Toppan Circuit Solutions Inc | 部品内蔵印刷配線板及びその製造方法 |
TWI390692B (zh) | 2009-06-23 | 2013-03-21 | Unimicron Technology Corp | 封裝基板與其製法暨基材 |
WO2011016555A1 (ja) * | 2009-08-07 | 2011-02-10 | 日本電気株式会社 | 半導体装置とその製造方法 |
KR101043328B1 (ko) * | 2010-03-05 | 2011-06-22 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판 및 그 제조방법 |
KR101104210B1 (ko) | 2010-03-05 | 2012-01-10 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판 및 그 제조방법 |
JP2011225777A (ja) * | 2010-04-22 | 2011-11-10 | Sumitomo Bakelite Co Ltd | プリプレグ、その製造方法及び積層板 |
KR101067109B1 (ko) | 2010-04-26 | 2011-09-26 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
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