CN110034184B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110034184B
CN110034184B CN201811474807.3A CN201811474807A CN110034184B CN 110034184 B CN110034184 B CN 110034184B CN 201811474807 A CN201811474807 A CN 201811474807A CN 110034184 B CN110034184 B CN 110034184B
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丹羽史和
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Denso Corp
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Abstract

本发明提供一种半导体装置，其降低在二极管区域与IGBT区域之间的边界附近处对半导体基板施加的负载。该半导体装置具有半导体基板。半导体基板具有与集电极区重叠的IGBT区域以及与阴极区重叠的二极管区域。半导体基板具有：横跨从IGBT区域至二极管区域而分布的漂移区；配置在IGBT区域内的体区、体接触区以及发射极区；和配置在二极管区域内的阳极区以及阳极接触区。体区具有第一体区和第二体区，该第二体区的p型杂质浓度与第一体区以及阳极区相比较低。第二体区与阳极区相邻。第一体区在第二体区的阳极区侧的相反侧与第二体区相邻。

Description

半导体装置
技术领域
本发明公开的技术涉及半导体装置。
背景技术
专利文献1公开了具备IGBT(insulated gate bipolar transistor)区域和二极管区域的半导体装置。该半导体装置具有半导体基板、上部电极以及下部电极。上部电极设置在半导体基板的上表面，下部电极设置在半导体基板的下表面。在二极管区域内，以使上部电极为阳极而下部电极为阴极的方式设置有二极管。在IGBT区域内，以使上部电极为发射极而下部电极为集电极的方式设置有IGBT。设置在IGBT区域内的IGBT是沟槽栅极型的IGBT。
专利文献1：日本特开2013-197306号公报
发明内容
在专利文献1的半导体装置中，如果上部电极的电位与下部电极的电位相比较高，则二极管导通，空穴从阳极区流向阴极区。另外，在专利文献1的半导体装置中，IGBT区域内的体区隔着沟槽与阳极区相邻。因此，体区配置为非常靠近阳极区。所以，如果二极管导通，则在从IGBT区域内的体区朝向二极管区域内的阴极区的路径上也会流过空穴。因此，在二极管导通的状态下，在二极管区域与IGBT区域之间的边界附近，漂移区内的空穴的浓度变高。然后，如果上部电极的电位与下部电极的电位相比较低，则二极管进行恢复动作，漂移区内的空穴流向上部电极。通过空穴如上流动，从而恢复电流流动。由于在二极管导通的状态下，在二极管区域与IGBT区域之间的边界附近，空穴的浓度较高，所以在恢复动作中，恢复电流以高密度流过二极管区域与IGBT区域之间的边界附近。因此，存在在二极管区域和IGBT区域之间的边界附近对半导体基板施加高负载的问题。所以，本发明提出一种降低在二极管区域与IGBT区域之间的边界附近处对半导体基板施加的负载的技术。
本发明公开的半导体装置具有：半导体基板、沟槽、栅极绝缘膜、栅极、上部电极以及下部电极。所述沟槽设置在所述半导体基板的上表面。所述栅极绝缘膜配置在所述沟槽内。所述栅极配置在所述沟槽内，并通过所述栅极绝缘膜相对于所述半导体基板绝缘。所述上部电极与所述上表面相接。所述下部电极与所述半导体基板的下表面相接。所述半导体基板在与所述下部电极相接的范围内，具备p型集电极区和n型阴极区。在沿着所述半导体基板的厚度方向俯视观察所述半导体基板时，与所述集电极区重叠的半导体区域是IGBT区域，与所述阴极区重叠的半导体区域是二极管区域。所述沟槽设置在所述IGBT内。所述半导体基板具有：漂移区、体区、体接触区、发射极区、阳极区以及阳极接触区。所述漂移区是n型区域，其横跨从所述IGBT区域至所述二极管区域而分布，配置在所述集电极区的上方以及所述阴极区的上方，并与所述栅极绝缘膜相接。所述体区是p型区域，其配置在所述IGBT区域内的所述漂移区的上方，并与所述栅极绝缘膜相接。所述体接触区是p型区域，其配置在所述体区的上方，与所述上部电极相接，其p型杂质浓度所述体区相比更高。所述发射极区是n型区域，其配置在所述体区的上方，与所述上部电极相接且与所述栅极绝缘膜相接，与所述漂移区之间隔着所述体区。所述阳极区是p型区域，其配置在所述二极管区域内的所述漂移区的上方。所述阳极接触区是p型区域，其配置在所述阳极区的上方，与所述上部电极相接，其p型杂质浓度与所述阳极区相比更高。所述体区具有第一体区和第二体区，该第二体区与所述第一体区以及所述阳极区相比，其p型杂质浓度较低。所述第二体区与所述阳极区相邻。所述第一体区在第二体区的所述阳极区侧的相反侧与所述第二体区相邻。
另外，第二体区可以直接与阳极区相邻，也可以隔着沟槽与阳极区相邻。另外，第一体区可以直接与第二体区相邻，也可以隔着沟槽与第二体区相邻。可以是漂移区与集电极区以及阴极区相接,也可以在漂移区与集电极区之间、漂移区与阴极区之间的至少一个区域中配置有其他半导体区域。可以是体区与漂移区相接，也可以在体区与漂移区之间配置有其他半导体区域。可以是阳极区与漂移区相接，也可以在阳极区与漂移区之间配置有其他半导体区域。
在该结构中，第二体区和阳极区相邻。所以，当二极管区域内的二极管导通时，空穴从IGBT区域内的第二体区流向阴极区。由于第二体区的p型杂质浓度较低，所以从第二体区流向阴极区的空穴较少。所以，在二极管区域与IGBT区域之间的边界附近的漂移区中，空穴的浓度不会变得那么高。因此，恢复动作时，抑制较高的恢复电流流过二极管区域与IGBT区域之间的边界附近。由此，能够降低在二极管区域与IGBT区域之间的边界附近处对半导体基板施加的负载。另外，配置在院里阳极区的位置处的第一体区具有与第二体区相比较高的p型杂质浓度。由于第一体区远离阳极区，所以即使第一体区的p型杂质浓度较高，也基本对恢复电流没有影响。另外，通过使第一体区的p型杂质浓度变高，能够改善IGBT的特性。
附图说明
图1是半导体装置10的俯视图。
图2是图1的II-II线处的剖视图。
图3是示出图2的III-III线处的p型杂质浓度的曲线图。
图4是图1的II-II线处的剖视图。
图5是示出变形例的半导体装置中与图3对应的p型杂质浓度的曲线图。
图6是示出变形例的半导体装置中与图3对应的p型杂质浓度的曲线图。
图7是变形例的半导体装置中与图2对应的剖视图。
图8是变形例的半导体装置中与图2对应的剖视图。
图9是变形例的半导体装置中与图2对应的剖视图。
具体实施方式
如图1所示，实施方式的半导体装置10具有半导体基板12。半导体基板12是硅制基板。另外，以下，将半导体基板12的厚度方向称为z方向，将与半导体基板12的上表面12a平行的一个方向称为x方向，将与半导体基板12的上表面12a平行且与x方向正交的方向称为y方向。如图1所示，半导体基板12具有两个元件区域18以及配置在元件区域18周围的耐压区域19。各元件区域18具有IGBT区域20和二极管区域40。在各元件区域18内，IGBT区域20和二极管区域40在y方向上交替设置。IGBT区域20内设置有IGBT，二极管区域40内设置有二极管。
如图2所示，半导体装置10具有上部电极14和下部电极16。上部电极14配置在半导体基板12的上表面12a(表面)。下部电极16配置在半导体基板12的下表面12b(背面)。上部电极兼作为IGBT的发射极和二极管的阳极电极。下部电极兼作为IGBT的集电极和二极管的阴极电极。
半导体基板12内设置有集电极区30和阴极区48。在包括半导体基板12的下表面12b的范围内，设置有集电极区30和阴极区48。集电极区30是p型杂质浓度较高的p型区域，并与下部电极16欧姆接触。阴极区48是n型杂质浓度较高的n型区域，并与下部电极16欧姆接触。在包括半导体基板12的下表面12b的范围内，在整个IGBT区域20设置有集电极区30，在整个二极管区域40设置有阴极区48。换言之，当如图1所示沿着z方向(半导体基板12的厚度方向)观察半导体基板12时，与集电极区30重叠的半导体区域是IGBT区域20，与阴极区48重叠的半导体区域是二极管区域40。
半导体基板12还具有：缓冲区28、漂移区26、体区24、体接触区23、发射极区22、阳极区42以及阳极接触区41。
缓冲区28是n型杂质浓度低于阴极区48的n型区域。缓冲区28横跨IGBT区域20和二极管区域40而分布。在IGBT区域20内，缓冲区28配置在集电极区30的上方，并与集电极区30相接。在二极管区域40内，缓冲区28配置在阴极区48的上方，并与阴极区48相接。
漂移区26是n型杂质浓度低于缓冲区28的n型区域。漂移区26横跨IGBT区域20和二极管区域40而分布。在IGBT区域20以及二极管区域40内，漂移区26配置在缓冲区28的上方，并与缓冲区28相接。
体区24是p型杂质浓度较低的p型区域。体区24配置在IGBT区域20内。体区24配置在漂移区26的上方，并与漂移区26相接。
体接触区23是p型杂质浓度高于体区24的p型区域。体接触区23配置在IGBT区域20内。体接触区23部分配置在体区24的上部，并与体区24相接。体接触区23被体区24与漂移区26分隔。体接触区23配置在包括半导体基板12的上表面12a在内的范围内，并与上部电极14欧姆接触。
发射极区22是n型杂质浓度高于漂移区域26的n型区域。发射极区22配置在IGBT区域20内。发射极区22部分配置在体区24的上方，并与体区24相接。发射极区22被体区24与漂移区26分隔。发射极区22配置在包括半导体基板12的上表面12a在内的、不存在体接触区23的范围内。发射极区22与上部电极14欧姆接触。
阳极区42是p型杂质浓度较低的p型区域。阳极区42配置在二极管区域40内。阳极区42配置在漂移区26的上方，并与漂移区26相接。
阳极接触区41是p型杂质浓度高于阳极区42的p型区域。阳极接触区41配置在二极管区域40内。阳极接触区41部分配置在阳极区42的上部，并与阳极区42相接。阳极接触区41被阳极区42与漂移区26分隔。阳极接触区41配置在包括半导体基板12的上表面12a在内的范围内，并与上部电极14欧姆接触。
半导体基板12的上表面12a设置有多个沟槽50。各沟槽50沿x方向伸长。多个沟槽50在y方向上隔着间隔排列。IGBT区域20和二极管区域40中各自设置有多个沟槽50。各沟槽50从上表面12a开始延伸直至深度到达漂移区26为止。
IGBT区域20内的各沟槽50的内表面被栅极绝缘膜32覆盖。IGBT区域20内的各沟槽50内配置有栅极34。各栅极34通过栅极绝缘膜32相对于半导体基板12绝缘。各栅极34的上方配置有层间绝缘膜36。各栅极34通过层间绝缘膜36相对于上部电极14绝缘。
漂移区26在沟槽50的下端部与栅极绝缘膜32相接。体区24在漂移区26的上方与栅极绝缘膜32相接。发射极区22在体区24的上方与栅极绝缘膜32相接。所以，各栅极34隔着栅极绝缘膜32与发射极区22、体区24以及漂移区26相对。
二极管区域40内的各沟槽50的内表面被绝缘膜52覆盖。二极管区域40内的各沟槽50内配置有控制电极54。各控制电极54通过绝缘膜52相对于半导体基板12绝缘。各控制电极54的上方配置有层间绝缘膜56。各控制电极54通过层间绝缘膜56相对于上部电极14绝缘。控制电极54的电位独立于栅极34的电位。例如，可以将控制电极54的电位固定为与上部电极14相同的电位。
漂移区26在沟槽50的下端部与绝缘膜52相接。阳极区42在漂移区26的上方与绝缘膜52相接。所以，各控制电极54隔着绝缘膜52与阳极区42、以及漂移区26相对。
图3示出了图2的III-III线处的p型杂质浓度的分布。另外，由于III-III线横穿沟槽50，所以图3中，曲线图在沟槽50的范围处中断。如图3所示，体区24具有第一体区24a、以及p型杂质浓度与第一体区24a相比较低的第二体区24b。图2所示的截面中，体区24被沟槽50划分为多个部分(夹在一对沟槽50间的部分)。第二体区24b设置在被沟槽50划分的部分中最靠近二极管区域40的部分处。第二体区24b在y方向上隔着沟槽50与阳极区42相邻。第一体区24a配置在被沟槽50划分的部分中除了设置第二体区24b的部分(即，最靠近二极管区域40的部分)以外的其它全部部分处。第一体区24a在y方向上隔着沟槽50与第二体区24b相邻。第一体区24a在第二体区24b的阳极区42侧的相反侧与第二体区24b相邻。即，在y方向上，第一体区24a与阳极区42之间配置有第二体区24b。如此，在体区24内，横向(y方向)上的p型杂质浓度产生变化。
如图3所示，第一体区24a内的p型杂质浓度大致等于阳极区42内的p型杂质浓度。另外，第二体区24b内的p型杂质浓度与第一体区24a内的p型杂质浓度以及阳极区42内的p型杂质浓度相比较低。第二体区24b内的p型杂质浓度以随着从第一体区24a一侧朝向阳极区42一侧而降低的方式分布。
接下来，对半导体装置10的动作进行说明。在上部电极14与下部电极16之间，通过阳极接触区41、阳极区42、漂移区26、缓冲区28以及阴极区48形成二极管(以下，称为主二极管)。如果对上部电极14施加高于下部电极16的电位，则主二极管导通。即，电子从下部电极16经由阴极区48、缓冲区28、漂移区26、阳极区42以及阳极接触区41流向上部电极14。同时，如图2的箭头100所示，空穴从上部电极14经由阳极接触区41以及阳极区42流入漂移区26。其结果，在漂移区26内引起电导调制现象，漂移区26的电阻降低。所以，电子能够以低损耗在漂移区26内流动。由此，抑制在主二极管中产生的损耗。流入漂移区26的空穴经由缓冲区28和阴极区48流向下部电极16。
另外，在二极管区域40与IGBT区域20之间的边界38处，通过体接触区23、第二体区24b、漂移区26、缓冲区28以及阴极区48形成寄生二极管。因此，当主二极管导通时，寄生二极管也导通，如图2的箭头102所示，空穴从第二体区24b流入漂移区26。漂移区26内，空穴朝向阴极区48向斜下方流动。因此，从阳极区42流入漂移区26的空穴和从第二体区24b流入漂移区26的空穴在边界38附近的漂移区26汇合。因此，边界38附近的漂移区26处，与位于二极管区域40的中央部的漂移区26相比，空穴的浓度变高。但由于在本实施方式中，第二体区24b的p型杂质浓度较低，所以抑制了箭头102所示的空穴的流入。因此，如箭头102所示从第二体区24b流入漂移区26的空穴较少。因此，抑制空穴的浓度在边界38附近的漂移区26处变得极高。
主二极管导通后，如果使上部电极14的电位降低到与下部电极16的电位相比较低的电位，则主二极管进行恢复动作。即，存在于漂移区26内的空穴被释放到上部电极14。因此，恢复电流(反向电流)瞬间性流过主二极管。如图4所示，存在于漂移区26的中央部附近的范围110内的空穴如箭头112所示，经由阳极区42和阳极接触区41流向上侧，并被释放到上部电极14。另外，存在于边界38附近的范围120内的空穴，如箭头122所示经由阳极区42和阳极接触区41被释放到上部电极14，或如箭头124所示经由第二体区24b和体接触区23被释放到上部电极14。如上所述，在主二极管导通的状态中，在边界38附近的范围120内存在与中央部附近的范围110相比浓度较高的空穴。因此，如箭头122、124所示流动的恢复电流与如箭头112所示流动的恢复电流相比密度较高。即，恢复电流集中在边界38附近的阳极区42和第二体区24b。然而，如上所述，在主二极管的导通状态中，通过第二体区24b，抑制了边界38附近的范围120内的空穴的浓度变得极高。因此，恢复动作时，如箭头122、124所示流动的恢复电流不会变得过高。如此，通过第二体区24b抑制了较高的恢复电流流过边界38附近。由此，防止对半导体基板12施加过大的负载。
另外，如上所述，在第二体区24b内，p型杂质浓度随着从第一体区24a侧越朝向阳极区42侧就越低。所以，第二体区24b的电阻在第一体区24a侧较低，在阳极区42侧较高。因此，箭头124所示路径(从范围120穿过第二体区24b到达上部电极14的最短路径)中，第二体区24b的电阻较高，如箭头126所示绕开最短路径而穿过第二体区24b的路径中，第二体区24b的电阻较低。因此，在箭头124所示的路径与箭头126所示的路径中，电阻大致相等。所以，从边界38附近的范围120流向上部电极14的恢复电流分散地流过箭头124所示的路径和箭头126所示的路径。即，恢复电流分散地流过第二体区24b。由此，进一步抑制恢复电流的集中，进一步降低对半导体基板12施加的负载。
另外，当使半导体装置10作为IGBT进行动作时，在下部电极16上施加高于上部电极14的电位。如果使栅极34的电位上升至与栅极阈值相比更高的电位，则在与栅极绝缘膜32相接的范围内的体区24中形成沟道。于是，电子从上部电极14经由发射极区22、沟道、漂移区26、缓冲区28以及集电极区30流向下部电极16。同时，空穴从下部电极16经由集电极区30、缓冲区28、漂移区26、体区24以及体接触区23流向上部电极。即，IGBT导通，电流从下部电极16流向上部电极14。如果使栅极34的电位降低至与栅极阈值相比更低的电位，则沟道消失，电流停止。即，IGBT断开。如上所述，体区24具备第一体区24a和第二体区24b。由于第一体区24a占体区24的大部分，所以IGBT的特性主要由第一体区24a内的p型杂质浓度决定。由于第一体区24a内的p型杂质浓度与第二体区24b内的p型杂质浓度相比较高，所以能够将IGBT的特性(栅极阈值、耐压等)设为适当的值。即，通过设置第一体区24a，与体区24整体的p型杂质浓度较低的情况相比，能够使栅极阈值变大，并提高耐压。另外，当IGBT导通时，由于电流也流过第二体区24b，所以，能够确保作为IGBT起作用的IGBT区域20的面积较大。由此，能够在不使半导体装置10大型化的情况下确保IGBT的电流容量。
如以上说明，通过在与阳极区42相邻的位置上设置p型杂质浓度较低的第二体区24b，能够降低恢复动作时对半导体基板12施加的负载。另外，通过第二体区24b的阳极区42侧的相反侧的与第二体区24b相邻的位置处设置p型杂质浓度较高的第一体区24a，能够改善IGBT的特性。
另外，在上述实施方式中，如图3所示，第二体区24b内的p型杂质浓度随着从第一体区24a侧朝向阳极区42侧而连续降低。然而，也可以是如图5所示，第二体区24b内的p型杂质浓度随着从第一体区24a侧朝向阳极区42侧而呈阶梯状降低。另外，也可以是如图6所示，第二体区24b内的p型杂质浓度大致恒定。另外，在上述实施方式中，阳极区42的p型杂质浓度和第一体区24a的p型杂质浓度大致相等，但也可以是这些p型杂质浓度彼此不同。
另外，在上述实施方式中，沟槽50位于边界38(即，阴极区48与集电极区30之间的边界)处。然而，也可以是如图7所示，边界38和沟槽50的位置彼此偏离。该情况下，阳极区42和第二体区24b直接相邻而不隔着沟槽50。
另外，在上述实施方式中，在被沟槽50划分的部分中最靠近二极管区域40的部分处设置有第二体区24b。然而，也可以是如图8所示，在被沟槽50划分的部分中最靠近二极管区域40的两个以上的部分处设置有第二体区24b。
另外，上述实施方式中，第一体区24a和第二体区24b隔着沟槽50相邻。然而，也可以是如图9所示，第一体区24a和第二体区24b直接相邻而不隔着沟槽50。
另外，在上述实施方式中，体区24以及阳极区42与漂移区26相接。然而，也可以是在体区24与漂移区26之间、阳极区42与漂移区26之间配置有其他区域(例如n型区域、p型区域、或将n型区域和p型区域组合而成的构造(层叠构造等))。另外，在上述实施方式中，漂移区26与阴极区48之间、以及漂移区26与集电极区30之间配置有缓冲区28。然而，也可以并不在该位置处配置缓冲区28。
以下列出本发明公开的技术要素。另外，以下各技术要素能够各自独立地应用。
本发明公开的一个例子的半导体装置中，也可以是第二体区内的p型杂质浓度分布为随着越靠近阳极区就越低。另外，第二体区的p型杂质浓度也可以分布为随着越靠近阳极区就连续地逐渐变低，还可以分布为随着越靠近阳极区就以阶梯状变低。
根据这样的结构，恢复电流更均匀地流过二极管区域与IGBT区域之间的边界附近。由此，能够进一步降低对半导体基板施加的负载。
以上对实施方式进行了详细说明，但其仅为例示，并不限定权利要求保护的范围。权利要求书所记载的技术包括将以上所例示的具体例子进行各种变形、变更后的内容。本说明书或说明书附图中所说明的技术要素可以单独、或通过各种组合而产生技术效果，并不限定于本发明的权利要求书所记载的组合。另外，本说明书或说明书附图所例示的技术同时实现了多个目的，但对于仅实现其中一个目的这一点而言也具有技术效果。
标号的说明
10…半导体装置
12…半导体基板
14…上部电极
16…下部电极
20…IGBT区域
22…发射极区
23…体接触区
24…体区
24a…第一体区
24b…第二体区
26…漂移区
28…缓冲区
30…集电极区
32…栅极绝缘膜
34…栅极
36…层间绝缘膜
38…边界
40…二极管区域
41…阳极接触区
42…阳极区
48…阴极区
50…沟槽
52…绝缘膜
54…控制电极
56…层间绝缘膜

Claims (4)

1.一种半导体装置，
其具有：半导体基板；
多个沟槽，其设置在所述半导体基板的上表面；
栅极绝缘膜，其配置在所述多个沟槽内；
栅极，其配置在所述多个沟槽内，并通过所述栅极绝缘膜相对于所述半导体基板绝缘；
上部电极，其与所述上表面相接；以及
下部电极，其与所述半导体基板的下表面相接，
所述半导体基板在与所述下部电极相接的范围内具备p型集电极区和n型阴极区，
在沿着所述半导体基板的厚度方向俯视观察所述半导体基板时，与所述集电极区重叠的半导体区域是IGBT区域，与所述阴极区重叠的半导体区域是二极管区域，
所述多个沟槽具有设置在所述IGBT区域内的多个第一沟槽、和设置于所述IGBT区域与所述二极管区域的边界的第二沟槽，
所述半导体基板具有：
漂移区，其横跨从所述IGBT区域至所述二极管区域而分布，配置在所述集电极区的上方以及所述阴极区的上方，并与所述多个沟槽内的所述栅极绝缘膜相接；
p型体区，其配置在所述IGBT区域内的所述漂移区的上方，并与所述栅极绝缘膜相接；
p型体接触区，其配置在所述体区的上方，与所述上部电极相接，其p型杂质浓度与所述体区相比更高；
n型发射极区，其配置在所述体区的上方，与所述上部电极相接，也与所述栅极绝缘膜相接，与所述漂移区之间隔着所述体区；
p型阳极区，其配置在所述二极管区域内的所述漂移区的上方；以及
p型阳极接触区，其配置在所述阳极区的上方，与所述上部电极相接，p型杂质浓度与所述阳极区相比更高，
所述体区由所述多个沟槽划分出第一体区及第二体区，
所述第一体区夹在2个所述第一沟槽之间，
所述第二体区夹在所述第一沟槽与所述第二沟槽之间，
该第二体区与所述第一体区以及所述阳极区相比，其p型杂质浓度较低，
所述第二体区隔着所述第二沟槽与所述阳极区相邻，
所述第一体区在所述第二体区的所述阳极区侧的相反侧隔着所述第一沟槽与所述第二体区相邻。
2.根据权利要求1所述的半导体装置，其中，
所述第二体区的p型杂质浓度分布为随着越靠近所述阳极区就越低。
3.根据权利要求2所述的半导体装置，其中，
所述第二体区的p型杂质浓度分布为随着越靠近所述阳极区就连续地逐渐变低。
4.根据权利要求2所述的半导体装置，其中，
所述第二体区的p型杂质浓度分布为随着越靠近所述阳极区就以阶梯状变低。
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JP7279356B2 (ja) * 2018-12-19 2023-05-23 富士電機株式会社 半導体装置
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009141202A (ja) * 2007-12-07 2009-06-25 Toyota Motor Corp 半導体装置とその半導体装置を備えている給電装置の駆動方法
CN102376709A (zh) * 2010-08-17 2012-03-14 株式会社电装 半导体器件
CN102832216A (zh) * 2011-06-15 2012-12-19 株式会社电装 包括绝缘栅双极晶体管和二极管的半导体设备
WO2013030943A1 (ja) * 2011-08-30 2013-03-07 トヨタ自動車株式会社 半導体装置
CN104576720A (zh) * 2011-01-17 2015-04-29 英飞凌科技奥地利有限公司 半导体器件和逆导igbt
CN106463504A (zh) * 2014-11-17 2017-02-22 富士电机株式会社 半导体装置以及半导体装置的制造方法
CN106796938A (zh) * 2014-08-26 2017-05-31 三菱电机株式会社 半导体元件

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5070941B2 (ja) 2007-05-30 2012-11-14 株式会社デンソー 半導体装置
JP6078961B2 (ja) 2012-03-19 2017-02-15 富士電機株式会社 半導体装置の製造方法
JP2014038937A (ja) * 2012-08-16 2014-02-27 Mitsubishi Electric Corp 半導体装置
JP2014075582A (ja) * 2012-09-12 2014-04-24 Fuji Electric Co Ltd 半導体装置および半導体装置の製造方法
JP6056984B2 (ja) * 2013-11-05 2017-01-11 トヨタ自動車株式会社 半導体装置
DE102014110681B4 (de) * 2014-07-29 2019-06-06 Infineon Technologies Ag Rückwärts leitender igbt und herstellungsverfahren dafür
JP6222702B2 (ja) * 2014-09-11 2017-11-01 株式会社東芝 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009141202A (ja) * 2007-12-07 2009-06-25 Toyota Motor Corp 半導体装置とその半導体装置を備えている給電装置の駆動方法
CN102376709A (zh) * 2010-08-17 2012-03-14 株式会社电装 半导体器件
CN104576720A (zh) * 2011-01-17 2015-04-29 英飞凌科技奥地利有限公司 半导体器件和逆导igbt
CN102832216A (zh) * 2011-06-15 2012-12-19 株式会社电装 包括绝缘栅双极晶体管和二极管的半导体设备
WO2013030943A1 (ja) * 2011-08-30 2013-03-07 トヨタ自動車株式会社 半導体装置
CN106796938A (zh) * 2014-08-26 2017-05-31 三菱电机株式会社 半导体元件
CN106463504A (zh) * 2014-11-17 2017-02-22 富士电机株式会社 半导体装置以及半导体装置的制造方法

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