WO2010143288A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2010143288A1 WO2010143288A1 PCT/JP2009/060685 JP2009060685W WO2010143288A1 WO 2010143288 A1 WO2010143288 A1 WO 2010143288A1 JP 2009060685 W JP2009060685 W JP 2009060685W WO 2010143288 A1 WO2010143288 A1 WO 2010143288A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000009792 diffusion process Methods 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 210000000746 body region Anatomy 0.000 claims abstract description 31
- 238000009825 accumulation Methods 0.000 claims abstract description 16
- 238000011084 recovery Methods 0.000 abstract description 19
- 239000000969 carrier Substances 0.000 abstract description 12
- 239000010410 layer Substances 0.000 description 185
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0664—Vertical bipolar transistor in combination with diodes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
Definitions
- the present invention relates to a semiconductor device in which an insulated gate bipolar transistor (IGBT) element region and a diode element region are formed on the same semiconductor substrate.
- IGBT insulated gate bipolar transistor
- Patent Document 1 discloses a semiconductor device in which an IGBT element region and a reflux diode element region are formed on the same semiconductor substrate.
- a back surface layer, an N ⁇ layer, an N layer, and a P layer are sequentially stacked, and an N + layer is provided on a part of the surface of the P layer.
- a trench gate that penetrates the P layer and the N layer and reaches the N ⁇ layer is provided from the surface side of the semiconductor substrate. The trench gate is in contact with the N + layer.
- As the back layer a P + layer or an N + layer is formed.
- a region where the back layer is a P + layer is an IGBT element region, and a region where the back layer is an N + layer is a diode element region.
- carriers may move between the IGBT element region and the diode element region.
- carriers attracted to the drift region near the interface with the body region move to the anode region side of the diode element region.
- the carrier density in the drift region of the IGBT element region decreases, the resistance of the drift region increases, and the on-voltage during the IGBT operation increases.
- a reverse recovery current flows in the diode element region.
- carriers accumulated outside the diode element region move to the diode element region.
- the reverse recovery current of the diode is increased, and element breakdown is likely to occur.
- the IGBT element region, the diode element region, and the boundary region provided between the IGBT element region and the diode element region are formed in the same semiconductor substrate.
- the IGBT element region includes a first conductivity type collector region, a second conductivity type first drift region provided on the surface side of the semiconductor substrate with respect to the collector region, and a surface of the semiconductor substrate with respect to the first drift region.
- the diode element region includes a second conductivity type cathode region, a second conductivity type second drift region provided on the surface side of the semiconductor substrate with respect to the cathode region, and a surface of the semiconductor substrate with respect to the second drift region. And a second body region of the first conductivity type provided on the side.
- the boundary region is provided in the second diffusion region, the first conductivity type first diffusion region, the first conductivity type second diffusion region provided on the surface side of the semiconductor substrate with respect to the first diffusion region, and the second diffusion region.
- the first drift region in the IGBT element region is in contact with the first diffusion region in the boundary region, and the second drift region in the diode element region is in contact with the first diffusion region in the boundary region.
- the first body region of the IGBT element region is in contact with the second diffusion region of the boundary region, and the second body region of the diode element region is in contact with the second diffusion region of the boundary region.
- the second conductivity type third diffusion region is provided in the first conductivity type second diffusion region.
- the third diffusion region in the boundary region extends until it contacts the carrier accumulation region in the IGBT element region.
- the effect of suppressing carrier movement during the IGBT operation can be further improved.
- the third diffusion region in the boundary region and the carrier accumulation region in the IGBT element region may be formed of the same semiconductor layer.
- the carrier accumulation region and the third diffusion region can be formed at the same time, the labor and cost of the semiconductor device manufacturing process are not increased.
- FIG. 1 is a cross-sectional view of a semiconductor device of Example 1.
- FIG. FIG. 2 is a diagram schematically illustrating a state of the semiconductor device of FIG. 1 during an IGBT operation. It is a figure which shows typically the state at the time of diode operation
- FIG. 1 is a cross-sectional view of a semiconductor device 100 according to the present embodiment.
- FIG. 2 is a diagram schematically showing the state of the semiconductor device 100 shown in FIG. 1 during IGBT operation
- FIG. 3 is a diagram schematically showing the state of the semiconductor device 100 shown in FIG. 1 during diode operation. is there. 2 and 3, the reference numerals of the components of the semiconductor device 100 shown in FIG. 1 are omitted.
- a plus sign surrounded by a circle indicates a hole.
- the semiconductor device 100 includes a semiconductor substrate 10, a back surface electrode 40, a diode surface electrode 41, and an IGBT surface electrode 42.
- the semiconductor device 100 includes a diode element region 1, an IGBT element region 2, a boundary region 3, and a peripheral withstand voltage portion 4 formed on the semiconductor substrate 10.
- the semiconductor substrate 10 includes a first 1N + layer 11, the first 1P + layer 12 adjacent to the 1N + layer 11, a 1N layer 13 and N laminated on the surface of the 1N + layer 11 and the 1P + layer 12 A layer 14;
- the diode element region 1 is a region on the upper surface side of the first N + layer 11 of the semiconductor substrate 10, and a back surface electrode 40 is provided on the back surface side, and a diode is formed on the front surface side.
- a surface electrode 41 is provided.
- the first P layer 151 as the second body region is stacked on the surface of the N ⁇ layer 14 as the second drift region.
- a second P + layer 171 as an anode region is provided on the surface of the first P layer 151.
- the first N + layer 11 is used as a cathode region
- the first N layer 13, the N ⁇ layer 14, the first P layer 151 is used as a conductive region
- the second P + layer 171 is used as an anode region.
- the IGBT element region 2 is a region on the upper surface side of the first P + layer 12 of the semiconductor substrate 10, and a rear surface electrode 40 is provided on the rear surface side, and an IGBT is disposed on the front surface side.
- a surface electrode 42 is provided.
- the second P layer 152, the second N layer 161, and the third P layer 153 are stacked on the surface of the N ⁇ layer 14.
- a third P + layer 172 and a second N + layer 181 are provided on the surface of the third P layer 153.
- the second N layer 161 is isolated from the N ⁇ layer 14 by the second P layer 152, and is isolated from the third P + layer 172 and the second N + layer 181 by the third P layer 153.
- a fourth P layer 301 extending from the surface side of the semiconductor substrate 10 to the N ⁇ layer 14 is provided at the boundary between the IGBT element region 2 and the peripheral breakdown voltage portion 4. The lower end of the fourth P layer 301 extends deeper than the lower end of the second P layer 152.
- a plurality of trench gates 19 are provided from the upper surface of semiconductor substrate 10 toward N ⁇ layer 14.
- the depth of the lower end portion of the trench gate 19 is deeper than the lower end portion of the second P layer 152 and shallower than the lower end portion of the fourth P layer 301.
- the trench gate 19 includes a gate insulating film 192 formed in the trench 191 and a gate electrode 193 filled therein.
- An interlayer insulating film 32 is provided between the gate electrode 193 and the IGBT surface electrode 42.
- the second N + layer 181 is in contact with the trench gate 19.
- the first P + layer 12 is the collector region
- the first N layer 13 is the buffer region
- the N ⁇ layer 14 is the first drift region
- the second P layer 152 and the third P layer 153 are the first body region
- the second N The + layer 181 is used as an emitter region
- the third P + layer 172 is used as a body contact region.
- the second N layer 161 is used as a carrier accumulation region.
- the boundary region 3 is an inactive region provided between the diode element region 1 and the IGBT element region 2. In the boundary region 3, no contact with the surface electrode is formed on the surface side of the semiconductor substrate 10. In the present embodiment, there is a boundary between the first N + layer 11 and the first P + layer 12 in the boundary region 3, and the first N layer 13 and the N ⁇ layer 14 are laminated on the upper layer side of the boundary. ing. In the present embodiment, the boundary region 3 is provided with a fifth P layer 302 extending from the surface side of the semiconductor substrate 10 to the N ⁇ layer 14.
- the fifth P layer 302 extends from the front surface side to the back surface side of the semiconductor substrate 10 along the boundary between the boundary region 3 and the IGBT element region 2 and the boundary between the boundary region 3 and the diode element region 1.
- a third N layer 162 that penetrates the fifth P layer 302 in the planar direction of the semiconductor substrate 10 (lateral direction shown in FIG. 1) is provided, and the end of the third N layer 162 on the IGBT element region 2 side is the IGBT element region. 2 extends to be in contact with the second N layer 161 provided in 2. The end of the third N layer 162 on the diode element region 1 side penetrates into part of the diode element region 1.
- the boundary region 3 includes the N ⁇ layer 14 as the N-type first diffusion region and the P-type second diffusion region provided on the surface side of the semiconductor substrate 10 with respect to the N ⁇ layer 14.
- a fifth P layer 302 and a third N layer 162 as an N-type third diffusion region are provided.
- the third N layer 162 is provided in the fifth P layer 302, and the N ⁇ layer 14 and the third N layer 162 are isolated by the fifth P layer 302. Further, the third N layer 162 extends until it comes into contact with the second N layer 161 serving as an N-type carrier storage region provided in the IGBT element region 2.
- the second N layer 161 and the third N layer 162 are formed on the semiconductor substrate 10 as the same layer.
- the third N layer 162 can be formed simultaneously with the process of forming the second N layer 161, labor and cost in the manufacturing process are not significantly increased.
- the semiconductor device includes 100, the IGBT element region 2, the diode element region 1, and the boundary region 3 provided between the IGBT element region 2 and the diode element region 1 on the same semiconductor substrate 10.
- This is a reverse conducting semiconductor device.
- the first drift region of the IGBT element region 2, the second drift region of the diode element region 1, and the first diffusion region of the boundary region 3 are formed on the semiconductor substrate 10 as the N ⁇ layer 14 which is the same layer.
- the first drift region in the IGBT element region is in contact with the first diffusion region in the boundary region
- the second drift region in the diode element region is in contact with the first diffusion region in the boundary region.
- the second P layer 152 and the third P layer 153 that are the first body regions of the IGBT element region 2 are in contact with the fifth P layer 302 that is the second diffusion region of the boundary region 3, and the second body region of the diode element region 1
- the first P layer 151 is in contact with the fifth P layer 302 which is the second diffusion region of the boundary region 3.
- the third N layer 162 as the N-type third diffusion region provided in the boundary region 3 extends until it contacts the second N layer 161 as the N-type carrier accumulation region provided in the IGBT element region 2. .
- holes are injected from the first P + layer 12 which is the collector region into the first N layer 13 and the N ⁇ layer 14.
- a drift region N - - holes which are minority carriers N occur conductivity modulation in the layer 14, N - resistance of the layer 14 is low.
- an IGBT current flows from the back surface side (collector region side) to the front surface side (emitter region side) of the semiconductor device.
- no current flows in the diode element region 1.
- a region having a high electron density is formed in the vicinity of the trench gate 19. Holes are further attracted to this high electron density region, and as shown in FIG. 2, in the IGBT element region 2, a region having a high hole density is formed in the N ⁇ layer 14 in the vicinity of the boundary with the second P layer 152.
- a second N layer 161 as a carrier accumulation layer is provided between the second P layer 152 and the third P layer 153 which are body regions. Therefore, compared to the case where the second N layer 161 is not provided, the hole density in the N ⁇ layer 14 in the vicinity of the boundary with the second P layer 152 can be increased.
- the third N layer 162 is further provided in the boundary region 3, and the third N layer 162 and the second N layer 161 provided in the IGBT element region 2 are in contact with each other. For this reason, the movement of holes indicated by broken lines in FIG. 2 can be suppressed. That is, by providing the third N layer 162 in the boundary region 3, it is possible to suppress the movement of holes through the fifth P layer 302 and the like to the second P + layer 171 in the diode element region 1. it can. Compared to the case where the third N layer 162 is not provided in the boundary region 3, the hole density in the N ⁇ layer 14 in the vicinity of the boundary with the second P layer 152 can be increased.
- the IGBT element region 2 is switched from the on state to the off state, and the diode element region 1 is operated so that a reflux current flows.
- the potential Va of the back surface electrode 40 is made lower than the potential Vb of the diode surface electrode 41 and the potential Vc of the IGBT surface electrode 42 (Va ⁇ Vb, Vc), as shown in FIG. Holes are injected from a certain second P + layer 171 into the N ⁇ layer 14 as the second drift region via the first P layer 151 as the second body region.
- a diode current flows from the second P + layer 171 (anode region) to the first N + layer 11 (cathode region) via the first P layer 151, the N ⁇ layer 14, and the first N layer 13. No current flows in the IGBT element region 2.
- the third N layer 162 is further provided in the boundary region 3, and the third N layer 162 and the second N layer 161 provided in the IGBT element region 2 are in contact with each other. For this reason, the movement of holes indicated by broken lines in FIG. 3 can be suppressed. That is, by providing the third N layer 162 in the boundary region 3, it is possible to prevent holes from moving from the diode element region 1 to the N ⁇ layer 14 in the boundary region 3 through the fifth P layer 302 and the like. can do. Compared with the case where the second N layer 161 is provided in the IGBT element region 2 and the third N layer 162 is not provided in the boundary region 3, holes may accumulate in the N ⁇ layer 14 in the boundary region 3. It is suppressed.
- the IGBT element region is switched to the on state in a state where the return current flows in the diode element region. That is, the potential Va of the back electrode 40 is set higher than the potential Vb of the diode surface electrode 41 and the potential Vc of the IGBT surface electrode 42 (Va> Vb, Vc), and a positive voltage (positive bias) is applied to the gate electrode 193. . In this case, a reverse recovery current flows in the diode element region 1. During reverse recovery of the diode, carriers accumulated outside the diode element region 1 move to the diode element region 1.
- the reverse recovery current can be reduced during the diode reverse recovery. Therefore, it is possible to suppress element destruction during reverse recovery of the diode.
- the configuration of the boundary region 3 is not limited to the above embodiment.
- the configuration of the boundary region 3 may be a configuration as shown in FIG.
- a semiconductor device 400 shown in FIG. 4 is different from the semiconductor device 100 shown in FIG.
- the sixth P layer 312 is formed at the same depth as the first P layer 151 in the diode element region 1 and the second P layer 152 in the IGBT element region 2.
- a third N layer 162 is formed in the sixth P layer 312, and the third N layer 162 and the N ⁇ layer 14 are isolated by the sixth P layer 312.
- the sixth P layer 312 is provided with a trench 39 that penetrates the sixth P layer 312 and the third N layer 162 from the surface side of the semiconductor substrate 10 and reaches the N ⁇ layer 14. Since the other configuration of the semiconductor device 400 is the same as that of the semiconductor device 100, a duplicate description is omitted.
- the boundary region is an inactive region where a contact between the semiconductor substrate and the surface electrode is not formed, and is provided between the diode element region and the IGBT element region.
- the semiconductor substrate is provided in the second diffusion region, the first diffusion region of the second conductivity type, the second diffusion region of the first conductivity type, and the first diffusion region by the second diffusion region. What is necessary is just to provide the 3rd diffusion area
- the area of the “region where the contact between the semiconductor substrate and the surface electrode is not formed” provided in the boundary region is the “contact between the semiconductor substrate and the surface electrode” provided in the active region such as the diode element region or the IGBT element region. It is larger than the area of the “region where no is formed”.
- the semiconductor substrate has a first conductivity type second diffusion region laminated on the surface side of the second conductivity type first diffusion region, and the second diffusion region has a second diffusion region.
- a third diffusion region of the second conductivity type that is isolated from the first diffusion region by the two diffusion regions, for example, at least one of the following (a) to (c): What is necessary is just to have the structure which satisfy
- the second diffusion region includes a lower end of the first body region of the IGBT element region (the lower end of the second P layer 152 in FIG. 1) and a lower end of the second body region of the diode element region (the first P layer in FIG. 1). This is a diffusion region (the fifth P layer 302 in FIG.
- the second diffusion region has the same depth as the first body region (second P layer 152 in FIG. 4) of the IGBT element region and the second body region (first P layer 151 in FIG. 4) of the diode element region. This is a diffusion region formed in (6th P layer 312 in FIG. 4).
- a trench (a trench 39 in FIG. 4) is formed which penetrates the second diffusion region (sixth P layer 312 in FIG. 4) from the surface side of the semiconductor substrate and reaches the first diffusion region (N ⁇ layer 14 in FIG. 4). Has been.
- (C) a second conductivity type diffusion region (the first N + layer 11 in the first embodiment) which becomes the cathode region of the diode element region on the back surface side (the side not in contact with the second diffusion region) of the first diffusion region; There is a boundary with a first conductivity type diffusion region (in the first embodiment, the first P + layer 12) that becomes the collector region of the IGBT element region.
- the third diffusion region in the boundary region and the carrier accumulation region in the IGBT element region are not in contact with each other, the path through which the carrier moves can be obtained by providing the third diffusion region in the boundary region. Can be narrowed. For this reason, it is possible to obtain the effect of reducing the on-voltage during the IGBT operation and the effect of reducing the reverse recovery current of the diode.
- the third diffusion region does not have to be formed from the boundary between the IGBT element region and the boundary region until reaching the boundary between the diode element region and the boundary region, and is formed in a part thereof. Also good. In this case, it is preferable that the third diffusion region is formed closer to the IGBT element region.
- the third diffusion region is formed of the same semiconductor layer as the carrier storage region of the IGBT element region. However, the third diffusion region and the carrier storage region are formed of different semiconductor layers. It may be.
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Abstract
Description
<IGBT動作時>
裏面電極40の電位Vaをダイオード表面電極41の電位Vb、IGBT表面電極42の電位Vcよりも高電位とし(Va>Vb,Vc)、ゲート電極193に正電圧(正バイアス)を印加すると、IGBT素子領域2では、第1ボディ領域である第2P層152および第3P層153において、トレンチゲート19の近傍にチャネルが形成される。このチャネルを通って、多数キャリアである電子がエミッタ領域である第2N+層181から第1ドリフト領域であるN-層14に注入される。また、コレクタ領域である第1P+層12から第1N層13及びN-層14へ正孔が注入される。少数キャリアである正孔がN-層14に注入されると、ドリフト領域であるN-層14において伝導率変調が起こり、N-層14の抵抗が低くなる。このように電子と正孔が移動することによって、半導体装置の裏面側(コレクタ領域側)から表面側(エミッタ領域側)に向かうIGBT電流が流れる。一方、ダイオード素子領域1では電流は流れない。
次に、IGBT素子領域2をオン状態からオフ状態に切り換え、ダイオード素子領域1を動作させて、還流電流が流れるようにする。裏面電極40の電位Vaをダイオード表面電極41の電位Vb、IGBT表面電極42の電位Vcよりも低くすると(Va<Vb,Vc)、図3に示すように、ダイオード素子領域1では、アノード領域である第2P+層171から、第2ボディ領域である第1P層151を介して、第2ドリフト領域であるN-層14に正孔が注入される。これによって、第2P+層171(アノード領域)から第1P層151、N-層14、第1N層13を介して第1N+層11(カソード領域)へダイオード電流(還流電流)が流れる。IGBT素子領域2では電流は流れない。
次に、ダイオード素子領域に還流電流が流れている状態でIGBT素子領域をオン状態に切換える。すなわち、裏面電極40の電位Vaをダイオード表面電極41の電位Vb、IGBT表面電極42の電位Vcよりも高電位とし(Va>Vb,Vc)、ゲート電極193に正電圧(正バイアス)を印加する。この場合、ダイオード素子領域1に逆回復電流が流れる。ダイオードの逆回復時には、ダイオード素子領域1の外部に蓄積されたキャリアがダイオード素子領域1へと移動する。ダイオードの逆回復時には、N-層14に蓄積した正孔は、第1P層151および第2P+層171の側に排出され、N-層14に蓄積した電子は、第1N層13、第1N+層11側に排出される。この逆回復時のキャリアの移動によって発生する電流を、逆回復電流という。逆回復電流は、N-層14に蓄積したキャリア量が多いほど大きくなる。逆回復電流が大きくなり過ぎると、素子破壊が起こり易くなる。
(a)第2拡散領域は、IGBT素子領域の第1ボディ領域の下端(図1では、第2P層152の下端)およびダイオード素子領域の第2ボディ領域の下端(図1では、第1P層151の下端)よりも深い位置まで形成された拡散領域(図1では、第5P層302)である。
(b)第2拡散領域は、IGBT素子領域の第1ボディ領域(図4では、第2P層152)、ダイオード素子領域の第2ボディ領域(図4では、第1P層151)と同じ深さに形成された拡散領域(図4では、第6P層312)である。かつ、半導体基板の表面側から第2拡散領域(図4では第6P層312)を貫通し、第1拡散領域(図4ではN-層14)に達するトレンチ(図4ではトレンチ39)が形成されている。
(c)第1拡散領域の裏面側(第2拡散領域と接しない側)に、ダイオード素子領域のカソード領域となる第2導電型の拡散領域(実施例1では、第1N+層11)と、IGBT素子領域のコレクタ領域となる第1導電型の拡散領域(実施例1では、第1P+層12)との境界がある。
Claims (3)
- IGBT素子領域と、
ダイオード素子領域と、
IGBT素子領域とダイオード素子領域との間に設けられた境界領域とが同一半導体基板内に形成されている半導体装置であって、
IGBT素子領域は、
第1導電型のコレクタ領域と、
コレクタ領域に対して半導体基板の表面側に設けられた第2導電型の第1ドリフト領域と、
第1ドリフト領域に対して半導体基板の表面側に設けられた第1導電型の第1ボディ領域と、
第1ボディ領域の表面に設けられた第2導電型のエミッタ領域と、
第1ボディ領域内に設けられ、第1ボディ領域によって第1ドリフト領域およびエミッタ領域と隔離されている第2導電型のキャリア蓄積領域と、
半導体基板の表面側から第1ボディ領域を貫通して第1ドリフト領域に達するトレンチゲートとを備えており、
ダイオード素子領域は、
第2導電型のカソード領域と、
カソード領域に対して半導体基板の表面側に設けられた第2導電型の第2ドリフト領域と、
第2ドリフト領域に対して半導体基板の表面側に設けられた第1導電型の第2ボディ領域とを備えており、
境界領域は、
第2導電型の第1拡散領域と、
第1拡散領域に対して半導体基板の表面側に設けられた第1導電型の第2拡散領域と、
第2拡散領域内に設けられ、第2拡散領域によって第1拡散領域と隔離されている第2導電型の第3拡散領域とを備えており、
IGBT素子領域の第1ドリフト領域が境界領域の第1拡散領域に接しており、ダイオード素子領域の第2ドリフト領域が境界領域の第1拡散領域に接しており、
IGBT素子領域の第1ボディ領域が境界領域の第2拡散領域に接しており、ダイオード素子領域の第2ボディ領域が境界領域の第2拡散領域に接している半導体装置。 - 境界領域の第3拡散領域は、IGBT素子領域のキャリア蓄積領域に接するまで伸びている請求項1に記載の半導体装置。
- 境界領域の第3拡散領域と、IGBT素子領域のキャリア蓄積領域とは、同一の半導体層によって形成されている請求項2に記載の半導体装置。
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PCT/JP2009/060685 WO2010143288A1 (ja) | 2009-06-11 | 2009-06-11 | 半導体装置 |
CN200980159805.8A CN102804359B (zh) | 2009-06-11 | 2009-06-11 | 半导体装置 |
EP09845813.6A EP2442355B1 (en) | 2009-06-11 | 2009-06-11 | Semiconductor device |
JP2010547887A JP4915481B2 (ja) | 2009-06-11 | 2009-06-11 | 半導体装置 |
KR1020117026022A KR101221206B1 (ko) | 2009-06-11 | 2009-06-11 | 반도체 장치 |
US13/315,841 US8362519B2 (en) | 2009-06-11 | 2011-12-09 | Semiconductor device |
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JPWO2010143288A1 (ja) | 2012-11-22 |
EP2442355A4 (en) | 2012-10-17 |
CN102804359B (zh) | 2014-06-04 |
US8362519B2 (en) | 2013-01-29 |
CN102804359A (zh) | 2012-11-28 |
JP4915481B2 (ja) | 2012-04-11 |
KR101221206B1 (ko) | 2013-01-21 |
EP2442355A1 (en) | 2012-04-18 |
US20120080718A1 (en) | 2012-04-05 |
EP2442355B1 (en) | 2014-04-23 |
KR20120024576A (ko) | 2012-03-14 |
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