CN1088261C - 具有浮动集电区的绝缘体上的硅器件 - Google Patents

具有浮动集电区的绝缘体上的硅器件 Download PDF

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CN1088261C
CN1088261C CN95195973A CN95195973A CN1088261C CN 1088261 C CN1088261 C CN 1088261C CN 95195973 A CN95195973 A CN 95195973A CN 95195973 A CN95195973 A CN 95195973A CN 1088261 C CN1088261 C CN 1088261C
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T·B·阿恩博格
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7317—Bipolar thin film transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

一种半导体器件包括：硅衬底(1)，在所述硅衬底(1)上的绝缘层(2)，在所述绝缘层(2)上的硅层(3)，所述硅层(3)由第一导电类型(N)的杂质掺杂，从所述硅层(3)的自由表面延伸到所述硅层(3)内的基区(4)，所述基区(4)由第二导电类型(P)的杂质掺杂，从所述基区(4)的自由表面延伸到所述基区(4)内的发射区(5)，所述发射区(5)由所述第一导电类型(N)的杂质重掺杂，及至少一个从所述硅层(3)的自由表面延伸到所述硅层(3)中的集电区(6)，该区距基区(4)一定横向距离，所述集电区(6)由所述第一导电类型(N)的杂质掺杂，设置于所述绝缘层(2)和所述基区(4)之间的所述硅层(3)中的浮动集电区(7)，该区距所述基区(4)一定距离，所述浮动集电区(7)的横向伸展部分大于发射区(5)的横向伸展部分，而小于基区(4)的横向伸展部分，所述浮动集电区(7)以重于所述硅层(3)的掺杂量掺杂所述第一导电类型(N)的杂质。

Description

具有浮动集电区的绝缘体上的硅器件
技术领域：
本发明涉及一种半导体器件，该器件包括：硅衬底；所述硅衬底上的绝缘层；所述绝缘层上的硅层，所述硅层由第一导电类型的杂质轻掺杂；从所述硅层的自由表面延伸到该硅层内的基区，所述基区由第二导电类型的杂质掺杂；从所述基区的自由表面延伸到该区内的发射区，所述发射区由所述第一导电类型的杂质重掺杂；并且至少一个从所述硅层的自由表面延伸到所述硅层中的集电区，该区与基区间有一横向距离，所述集电区由所述第一导电类型的杂质掺杂。
发明背景：
Andrej Litwin和Torkel Arnborg在1993年9月发表于ESSDERC’93的迟交论文快报(Late News Paper at ESSDERC’93)中的用于混合的高压和高密度集成电路应用的极紧凑的CMOS兼容的双极型绝缘体上的硅晶体管(“Extremely compact CMOS compatiblebipolar silicon-on-insulator transistor for mixed high voltage and highdensity integrated circuit applications”)及Andrej Litwin和TorkelArnborg在1994年6月发表于ISPSD’93，Davos中的“紧凑的甚高压兼容双极型绝缘体上的硅晶体管”(“Compact Very High VoltageCompatible Bipolar Silicon-On-Insulator Transistor”)皆公开了一种有上述结构的双极绝缘体上的硅晶体管。
这种晶体管的发射极-基极结构是垂直的，但由横向完全耗尽的集电区来承受高集电极电压。这种晶体管可以设计成几乎能承受高达几百伏的任何所需电压。
高速晶体管的一个重要特点是单位增益频率。该频率是晶体管中相应的渡越时间总和的倒数。在已知的绝缘体上的硅晶体管中，最重要的渡越时间是垂直穿过基区和沿硅-氧化物界面横向输运所需时间。实际输运机制在多数情况下是扩散而不是漂移，这意味着渡越时间正比于输运距离平方的倒数。由于界面处的横向距离大于基区里的垂直距离，所以有关的渡越时间很长。这样晶体管的速度主要受界面处的渡越时间限制。
发明的公开：
本发明的目的是消除由于沿硅-氧化物界面的横向扩散而造成的对速度的限制，在不影响其高电压能力的情况下，提高晶体管的速度。
在上述类型的半导体器件的所述绝缘层和所述基区之间的所述硅层中，距所述基区一定距离设置浮动集电区(floating collector)，所述浮动集电区的横向伸展部分大于发射区的横向伸展部分，而小于基区的横向伸展部分，所述浮动集电区用重于所述硅层的掺杂量掺杂所述第一导电类型的杂质，由这种结构的半导体器件可实现上述目的。
附图简述：
下面将结合一幅根据本发明的双极型绝缘体上的硅晶体管的实施例的附图更具体地说明本发明。
优选实施例描述：
附图中的这一示图展示了根据本发明的双极型绝缘体上的硅(SOI)晶体管的实施例。该晶体管包括硅衬底1，其上设有绝缘氧化层2。
在绝缘氧化层2上设置由N型导电杂质轻掺杂的硅层3。
由P型导电杂质掺杂的基区4从硅层3的自由表面延伸到硅层3内。
由N型导电杂质重掺杂的发射区5从基区4的自由表面延伸到基区4内。
按图示实施例，晶体管包括一个由N型导电杂质掺杂的集电区6。集电区从硅层3的自由表面延伸到硅层3内，距基区4一定横向距离。
按另一实施例(未示出)，晶体管可以包括两个置于基区两侧的集电区。
如上所述，沿基区4和发射区5之下的硅层3和氧化层2间界面的载流子的传输主要是扩散，且相关的渡越时间实际上限制晶体管的速度。
然而，根据本发明，在基区4和发射区5之下选择地***浮动集电区7，可以获得受基区-发射区结构限制的高速度，并且不影响高电压能力。
根据本发明，浮动集电区7设置于绝缘氧化层2和基区4之间的硅层3中，距基区4一定距离。浮动集电区7的横向伸展部分大于发射区5的横向伸展部分，而小于基区4的横向伸展部分。另外，根据本发明，浮动集电区7以重于硅层3的掺杂量由N型导电杂质掺杂。
在基区4和发射区5下加入重掺杂的N型浮动集电区7，可以将有限的渡越时间减少到几乎为零，而且不会影响高电压能力。这样，只改变布局便可以用简单工艺实现极高速度和极高压器件的有机结合。

Claims (1)

1.一种半导体器件，包括：
硅衬底(1)，
在所述硅衬底(1)上的绝缘层(2)，
在所述绝缘层(2)上的硅层(3)，所述硅层(3)由第一导电类型的杂质轻掺杂，
从所述硅层(3)的自由表面延伸到所述硅层(3)内的基区(4)，所述基区(4)由第二导电类型的杂质掺杂，
从所述基区(4)的自由表面延伸到所述基区(4)内的发射区(5)，所述发射区(5)由所述第一导电类型的杂质重掺杂，及
至少一个从所述硅层(3)的自由表面延伸到所述硅层(3)中的集电区(6)，该区与基区(4)间有一横向距离，所述集电区(6)由所述第一导电类型的杂质掺杂，其特征在于：
所述绝缘层(2)和所述基区(4)之间的所述硅层(3)中设置浮动集电区(7)，该区和所述基区(4)分开，所述浮动集电区(7)的横向伸展部分大于发射区(5)的横向伸展部分，而小于基区(4)的横向伸展部分，所述浮动集电区(7)以重于所述硅层(3)的掺杂量掺杂所述第一导电类型的杂质。
CN95195973A 1994-10-31 1995-10-31 具有浮动集电区的绝缘体上的硅器件 Expired - Lifetime CN1088261C (zh)

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SE9403722-3 1994-10-31
SE9403722A SE513512C2 (sv) 1994-10-31 1994-10-31 Halvledaranordning med ett flytande kollektorområde

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AU (1) AU3857595A (zh)
CA (1) CA2204136A1 (zh)
FI (1) FI971753A0 (zh)
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EP1142026B1 (de) * 1998-12-04 2007-11-14 Infineon Technologies AG Leistungshalbleiterschalter
US7760103B2 (en) * 2001-10-26 2010-07-20 Innovative American Technology, Inc. Multi-stage system for verification of container contents
US8350352B2 (en) 2009-11-02 2013-01-08 Analog Devices, Inc. Bipolar transistor
US9099489B2 (en) * 2012-07-10 2015-08-04 Freescale Semiconductor Inc. Bipolar transistor with high breakdown voltage
CN108155226A (zh) * 2017-12-22 2018-06-12 杭州士兰微电子股份有限公司 Npn型三极管及其制造方法

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US4861731A (en) * 1988-02-02 1989-08-29 General Motors Corporation Method of fabricating a lateral dual gate thyristor
US5341022A (en) * 1992-05-15 1994-08-23 Mitsubishi Denki Kabushiki Kaisha Bipolar transistor having a high ion concentration buried floating collector and method of fabricating the same

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US4819055A (en) * 1983-03-07 1989-04-04 Hitachi, Ltd. Semiconductor device having a PN junction formed on an insulator film
JPS6213071A (ja) * 1985-07-10 1987-01-21 Mitsubishi Electric Corp 半導体装置の製造方法
US4861731A (en) * 1988-02-02 1989-08-29 General Motors Corporation Method of fabricating a lateral dual gate thyristor
US5341022A (en) * 1992-05-15 1994-08-23 Mitsubishi Denki Kabushiki Kaisha Bipolar transistor having a high ion concentration buried floating collector and method of fabricating the same

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SE9403722L (sv) 1996-05-01
CN1165585A (zh) 1997-11-19
JPH10508155A (ja) 1998-08-04
EP0789933A2 (en) 1997-08-20
FI971753A (fi) 1997-04-24
SE513512C2 (sv) 2000-09-25
US5939759A (en) 1999-08-17
SE9403722D0 (sv) 1994-10-31
CA2204136A1 (en) 1996-05-09
FI971753A0 (fi) 1997-04-24
WO1996013862A1 (en) 1996-05-09
AU3857595A (en) 1996-05-23

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