CN1212787A - 具有倾斜pn结的双极型soi器件及制造这种器件的方法 - Google Patents
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Abstract
在一种双极型绝缘体上半导体晶体管器件(1)内,包括位于绝缘体(3)上的半导体晶片例如单晶硅晶片(2)内的发射区(4)、基区(5)、集电区(2)、和集电极接触区(6),基极－发射极和集电极－基极结相对于半导体晶片(2)和绝缘体(3)之间的界面倾斜。通过各向异性刻蚀器件以便在器件的一个边缘制备倾斜的表面(7)或具有倾斜侧壁的等同的V形槽。然后,通过向倾斜侧壁内部的材料中扩散适当的施主或受主原子。制备基极和发射极区域(5,4)。这种双极型绝缘体上的半导体晶体管器件结合的横向半导体器件的高速特性和纵向半导体器件的高压特性。
Description
本发明涉及双极型绝缘体上的半导体器件及其制造这种器件的方法。
现已提出计划设计大量的、在半导体衬底上无重掺杂掩埋层的双极型半导体器件。有两种基本类型的双极型半导体器件，即横向器件和纵向器件。
横向器件(参见如Stephen A.Parke,Chenming Hu,Ping K.Ko:“A High-performance Lateral Bipolar Transi stor Fabricated OnSimox”,IEEE Electron Dev.Lett.,14卷，33-35页，1993年一月，和R.Dekker,W.T.A.v.d.Einden和H.G.R.Mass:“An UltraLow Power Lateral Bipolar Emitter Technology on SOI”,1993 IEDM会议论文集，75-77页)适于高速应用，但只能承受很小的电压。
纵向器件(参见如Andrej Litwin和Torkel Arnborg：紧凑超高压兼容的双极SOI晶体管“Compact Very High Voltage CompatibleBipolar Silicon-On-Insulator Transistor”ISPSD’94,Davos,1994年六月，和美国专利NO.4,868,624)更适于承受高压和适中开关速度的应用。
隔离浅横向器件比隔离纵向器件更容易实现，这是因为利用简单的LOCOS或台面隔离代替了槽或结面隔离。然而，很难控制基极和发射极的掺杂，这是因为要利用横向扩散。横向器件的击穿电压BVceo比纵向器件更低，其中BVceo=BVcbo。另一方面，能够承受高电压的纵向器件具有开关速度低的缺点，这是因为受到电势锁定效应造成的横向载流子沿基极下面的半导体-绝缘体界面传输的渡越时间的限制(见Torkel Arnborg：带有完全耗尽的集电极的高速、高压双极SOI晶体管的模型与模拟“Modelling and Simulation of High Speed,HighVoltage Bipolar SOI Transistor with fully Depleted Collector”发表在1994年的IEDM会议论文集)。
本发明的一个目的是提供一种将横向半导体器件的高速特性和纵向半导体器件的高压特性相结合的双极型绝缘体上的半导体器件。
利用具有倾斜基极-发射极结面和集电极-基极结面的双极型绝缘体上的半导体器件可实现该目的。
通过制造包括具有倾斜构形的基区和发射区的双极型绝缘体上的半导体器件的方法也可以实现该目的。
下面参考附图以非限制性实施例的方式详细地介绍本发明，其中：
-图1为双极型绝缘体上半导体器件的剖面示意图，
-图2和3为在根据图1的双极型器件的发射极处计算出的掺杂剂分布图，
-图4为在根据图1的双极型器件的发射极处测量到的掺杂剂分布图。
图1图示出双极型绝缘体上半导体器件1的实施例，其中半导体为单晶硅晶片，由此器件1为绝缘体上硅(SOI)半导体器件。硅晶片用2表示，而绝缘体例如硅氧化层用3表示，位于硅晶片之下，从图中可以看出。图示的器件一般为矩形剖面。
硅晶片2包括发射极区4、基极区5和集电极接触区6，集电极是位于基极区5和集电极接触区6之间的体硅材料2的区域。在npn晶体管中，发射区4为如砷的n型掺杂，基区为如硼的p型掺杂，体硅材料为如砷的n型掺杂，集电极接触区6为如砷的n型重掺杂。在硅晶片2中，基极-发射极结面和集电极-基极结面相互平行，它们都与硅晶片2和绝缘体3之间的界面倾斜。这是由于薄发射极区或层4和薄基区或层5与硅晶片2和绝缘体3之间的界面倾斜的原因。
基极-发射极结面和集电极-基极结面与硅晶片2和绝缘体3之间的界面的倾斜角通常在45°±20°的范围内，即在25和65°之间。
发射极和基极区4,5位于具有倾斜表面7的晶片结构的上边缘线处，通过切掉矩形剖面的角部区域可以得到这种构形。发射极和基极区位于该倾斜表面7，基极区5为直接位于倾斜表面内的薄层，发射区4为直接位于发射区内的薄层，因此，发射极和基极区平行于倾斜表面7延伸。倾斜表面7仅为硅层2的表面，并没有延伸到绝缘层3。集电极接触区6位于与倾斜表面7所处的边缘相对的结构的上边缘线。
制造所示半导体器件1的方法包括各向异性刻蚀SOI膜，沿SOI膜的表面是(100)硅晶面。用KOH溶液进行刻蚀，以便制成倾斜表面7，使该表面总是沿硅晶片2的(111)晶面设置。仅在SOI膜的一个横向边缘处进行刻蚀，在刻蚀步骤之前需要施加合适的掩膜。在基极区5和发射极4上进行掺杂，以使它们与倾斜表面7平行，从而与硅晶片2中的(111)晶面平行，假设已包括在某个较早处理步骤中制成的集电极接触区6。平行的基极-发射极结面和集电极-基极结面的倾斜角由此与硅晶片2的(111)晶面相对于硅晶片2的上表面的倾斜角相同。最后以一些常规的方式如在合适的位置处重掺杂接触区和在这些区域的上部形成合金化或在合适的接触位置上形成多晶硅结构制备出发射极、基极和集电极接触(未显示)。该方法可以用于在晶片上制备晶体管，例如用于在同一芯片上具有不同组件的集成电路。然后进行各向异性刻蚀制备沿硅单晶材料的(111)晶面制作具有侧壁的V形槽。在V形槽中，其合适的掺杂剂扩散到硅材料中制备基区和发射区。该方法与制备晶体管的常规方法的不同之处主要在于在扩散步骤之前制备V形槽或制备具有斜壁的V形槽代替具有垂直于晶片表面的侧壁的矩形刻面槽。
图2示出了对于参考图1介绍的晶体管的典型实施例沿垂直于发射极4的倾斜表面7截取的掺杂分布的一维模拟曲线。画出的不同曲线示出了砷、硼和磷的浓度与距表面7距离的函数关系。此外，示出了净掺杂浓度。在图3的曲线中，示出了净施主浓度和净受主浓度与同一距离的函数关系。同样在此示出了净掺杂浓度。
在图4中，对于掺有砷和硼的npn晶体管，同样示出了掺杂剂原子的实际浓度测量值与距发射区的倾斜表面的同一垂直距离的函数关系。
然而，应该明白除了以上介绍的刻蚀以外，其它方法也可以用于制备倾斜的平行基极-发射极结面和集电极-基极结面。此外，除了硅晶片的(111)晶面还可以露出其它晶向面，用于制备要掺杂的倾斜表面，以获得平行于露出的晶向面的基区和发射区。
选择SOI膜的尺寸，使垂直于发射极-基极结面的电场减小。这样将增加半导体器件的击穿电压。由于它的几何图形，电荷沿电场的方向注入到集电极空间电荷区。由于不存在电势锁定，因此横向电场绝对不为零，通过漂移而不是象具有完全耗尽集电极的半导体器件那样通过扩散进行传输。该特性使以上介绍的半导体器件与横向半导体器件相比具有更快的速度。
此外，应该明白本发明并不限于在绝缘体上半导体器件中使用硅作为半导体材料。除硅之外，也可以同样使用例如GaAs或SiC。
Claims (6)
1．一种双极型绝缘体上半导体器件(1)，包括位于绝缘体(3)上的半导体晶片(2)内的发射区(4)、基区(5)和集电区，特征在于基极-发射极结面和集电极-基极结面相对于半导体晶片(2)和绝缘体(3)之间的界面倾斜。
2．根据权利要求1的器件，特征在于基极-发射极结面和集电极-基极结面的倾斜角在45°±20°的范围内。
3．根据权利要求1或2的器件，当半导体晶片由单晶硅(Si)制成时，特征在于基极-发射极结面和集电极-基极结面的倾斜角与硅晶片(2)的(111)晶面相对应。
4．一种由绝缘体(3)上的半导体晶片(2)制备双极型绝缘体上半导体器件的方法，特征在于掺杂晶片制备与半导体晶片(2)和绝缘体(3)之间的界面倾斜的基区(5)和发射区(4)。
5．根据权利要求4的方法，特征在于基极-发射极结面和集电极-基极结面的倾斜角在45°±20°的范围内。
6．根据权利要求4或5的器件，当半导体晶片由单晶硅(Si)制成时，特征在于在掺杂平行于露出的硅晶片(2)的(111)晶面的基区(5)和发射区(4)之前，在它的一个横向边缘处各向异性地刻蚀半导体晶片(2)使(111)晶面露出。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9600898A SE506510C2 (sv) | 1996-03-07 | 1996-03-07 | Halvledare innefattande lutande bas-emitter och kollektor- basövergångar och förfarande för att framställa en sådan |
| SE9600898-2 | 1996-03-07 |
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| CN1212787A true CN1212787A (zh) | 1999-03-31 |
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| CN97192844A Pending CN1212787A (zh) | 1996-03-07 | 1997-03-05 | 具有倾斜pn结的双极型soi器件及制造这种器件的方法 |
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| EP (1) | EP0963610A1 (zh) |
| JP (1) | JP2000506311A (zh) |
| KR (1) | KR19990087554A (zh) |
| CN (1) | CN1212787A (zh) |
| AU (1) | AU2049397A (zh) |
| CA (1) | CA2243998A1 (zh) |
| SE (1) | SE506510C2 (zh) |
| WO (1) | WO1997033319A1 (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100197001B1 (ko) * | 1996-05-02 | 1999-07-01 | 구본준 | 바이폴라소자 및 그 제조방법 |
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| DE1589453A1 (de) * | 1966-06-28 | 1970-04-02 | Asea Ab | Halbleiteranordnung |
| US5040034A (en) * | 1989-01-18 | 1991-08-13 | Nissan Motor Co., Ltd. | Semiconductor device |
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1996
- 1996-03-07 SE SE9600898A patent/SE506510C2/sv not_active IP Right Cessation
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1997
- 1997-03-05 CN CN97192844A patent/CN1212787A/zh active Pending
- 1997-03-05 CA CA002243998A patent/CA2243998A1/en not_active Abandoned
- 1997-03-05 WO PCT/SE1997/000377 patent/WO1997033319A1/en not_active Application Discontinuation
- 1997-03-05 KR KR1019980706992A patent/KR19990087554A/ko active IP Right Grant
- 1997-03-05 JP JP9531710A patent/JP2000506311A/ja active Pending
- 1997-03-05 EP EP97908624A patent/EP0963610A1/en not_active Withdrawn
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| Publication number | Publication date |
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| SE506510C2 (sv) | 1997-12-22 |
| AU2049397A (en) | 1997-09-22 |
| SE9600898D0 (sv) | 1996-03-07 |
| CA2243998A1 (en) | 1997-09-12 |
| SE9600898L (sv) | 1997-09-08 |
| JP2000506311A (ja) | 2000-05-23 |
| EP0963610A1 (en) | 1999-12-15 |
| KR19990087554A (ko) | 1999-12-27 |
| WO1997033319A1 (en) | 1997-09-12 |
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