CN1077723C - 在mosfet的硅衬底上形成低薄层电阻结的方法 - Google Patents

在mosfet的硅衬底上形成低薄层电阻结的方法 Download PDF

Info

Publication number
CN1077723C
CN1077723C CN96101496A CN96101496A CN1077723C CN 1077723 C CN1077723 C CN 1077723C CN 96101496 A CN96101496 A CN 96101496A CN 96101496 A CN96101496 A CN 96101496A CN 1077723 C CN1077723 C CN 1077723C
Authority
CN
China
Prior art keywords
silicon substrate
amorphous silicon
silicon layer
ion
sheet resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96101496A
Other languages
English (en)
Other versions
CN1138748A (zh
Inventor
李吉镐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of CN1138748A publication Critical patent/CN1138748A/zh
Application granted granted Critical
Publication of CN1077723C publication Critical patent/CN1077723C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供一种在硅衬底上形成低薄层电阻结的方法，该方法包括以下步骤：在所说硅衬底上形成非晶硅层；将杂质离子注入所说非晶硅层；将过渡金属离子注入所说非晶硅层；热处理所说非晶硅层和硅衬底，使过渡金属离于扩散到所说硅衬底的表面，使所说杂质离子扩散到所说硅衬底里。

Description

在MOSFET的硅衬底上形成低薄层电阻结的方法
本发明涉及形成具有浅结和低薄层电阻的半导体器件的方法，尤其涉及制造能防止结击穿和结漏电流增加的在MOSFET的硅衬底上形成低薄层电阻结的方法。
通常，MOS晶体管结形成于硅衬底和诸如源/漏区这样的有源区之间。
在常规MOSFET中，一般用硅化钛层来形成具有低薄层电阻的器件。在给硅衬底注入杂质离子后，通过第一热处理在那里形成结。接着在离子注入区形成钛层，并且通过第二热处理形成硅化钛层。
然而，在进行第二热处理时，掺杂进衬底的杂质离子又重新扩散到硅化钛层，之后硅化钛层和硅衬底间界面上的杂质浓度急据减小，从而生成了肖特基结。这样，就产生了一些象结击穿电压降低和结漏电流增加之类的问题。
此外，因为随半导体器件集成度变高，结的深度变浅，致使薄层电阻增加给发展高速度器件造成了更大困难。
本发明的一个目的是提供一种没有硅层消耗形成同时具有浅结和低薄层电阻的半导体器件的方法。
本发明的一个方面是，提供一种在硅衬底上形成低薄层电阻的结的方法，该方法包括以下步骤：在硅衬底上形成包括一栅极区、一源极区和一漏极区的MOSFET；在源/漏极区上形成一非晶硅层；将杂质离子注入所说非晶硅层；将过渡金属离子注入所说非晶硅层；热处理所说非晶硅层和硅衬底，从而使所说过渡金属离子扩散到所说硅衬底的表面和使所说杂质离子扩散进硅衬底。
从下面参照附图对实施例的描述可明显看出本发明的其它目的和方面。
图1A至1D是表示根据本发明的一个实施例形成MOSFET的方法的横截面图。
参照图1A至1D，下面对本发明的实施例进行详细描述。
首先，如图1A所示，在硅衬底1上由栅氧化层10，栅极11和侧壁氧化层12构成一个通用的MOSFET，这些是所属技术领域的普通技术人员所熟知的。在形成侧壁氧化层12之前，可以将杂质离子注入进硅衬底1来形成LDD(轻掺杂漏)结构，离子注入是用栅极11上的侧壁氧化层12和一绝缘层(未示出)作离子注入阻挡层。在形成源/漏区的暴露的硅衬底上淀积厚度为“T”即200-300的非晶硅层13。
接下来，如图1B所示，通过将BF2离子注入非晶硅层13，使硼离子14定位。当硼离子14注入进硅衬底1时，就会因为硼离子的小尺寸而发生严重的硼离子14的沟道作用。因此，要在硼离子14注入进硅衬底1的情况下形成浅结是很困难的。再看图1A，非晶硅层13对浅结的影响是利用沟道作用来防止硼离子14渗入硅衬底1。而且必须控制加速硼离子14的能量，以免它们渗入硅衬底1和非晶硅层13的界面。在一个优选实施例中，硼离子14的射入范围设置在非晶硅层13的一半厚处，即，硼离子14的射入深度为0.5T。
如图1C所示，为了在不消耗硅衬底1的情况下形成薄硅化物层，必须以小于硼离子14注入的能量将钨离子15注入进非晶硅层13。当然，像钛或钴这样的过渡金属离子可以代替钨离子15。特别是，必须控制钨离子15的能量才能使之不注入硅衬底1。在优选实施例中，钨离子15的射入范围设置在非晶硅层13的一半厚度处。
最后，如图1D所示，在将硼和钨离子15注入到非晶硅层13后，对晶片施行迅速热处理，使在非晶硅层13中的钨和硼离子15和14向硅衬底1扩散。由于硼离子14的扩散系数比钨离子15的高，就使源/漏区16在硅衬底1里形成，在源/漏区上面形成了硅化钨层17。
从上面的描述可以明显看出，本发明具有能通过形成具有低薄层电阻的浅结改进器件速度的很好效果。
尽管以上参照本发明所公开的优选实施例阐明了发明目的，但本领域技术人员很清楚，任何不脱离本发明权利要求书所公开的本发明的精神和范围的修正、增加和替代都是可能的。

Claims (5)

1、一种在MOSFET的硅衬底上形成低薄层电阻结的方法，
其特征在于，该方法包括以下步骤：
在硅衬底上形成包括一栅极区、一源极区和一漏极区的MOSFET；
在源/漏极区上形成一非晶硅层；
将杂质离子注入所说非晶硅层；
将过渡金属离子注入所说非晶硅层；和
热处理所说非晶硅层和硅衬底，使所说过渡金属离子扩散到所说硅衬底的表面，使所说杂质离子扩散进所说硅衬底。
2、根据权利要求1的方法，其特征在于，所说杂质离子为BF2离子。
3、根据权利要求1的方法，其特征在于，所说杂质离子的射入范围被设置在所说非晶硅层的半厚度处。
4、根据权利要求1的方法，其特征在于，所说过渡金属是钨、钛或钴之一。
5、根据权利要求1的方法，其特征在于，所说过渡金属离子的射入范围被设置在所说非晶硅层的半厚度处。
CN96101496A 1995-02-24 1996-02-24 在mosfet的硅衬底上形成低薄层电阻结的方法 Expired - Fee Related CN1077723C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR3738/1995 1995-02-24
KR3738/95 1995-02-24
KR1019950003738A KR0144020B1 (ko) 1995-02-24 1995-02-24 낮은 면저항을 갖는 접합 형성방법

Publications (2)

Publication Number Publication Date
CN1138748A CN1138748A (zh) 1996-12-25
CN1077723C true CN1077723C (zh) 2002-01-09

Family

ID=19408780

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96101496A Expired - Fee Related CN1077723C (zh) 1995-02-24 1996-02-24 在mosfet的硅衬底上形成低薄层电阻结的方法

Country Status (4)

Country Link
US (1) US5677213A (zh)
KR (1) KR0144020B1 (zh)
CN (1) CN1077723C (zh)
TW (1) TW369683B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100202633B1 (ko) * 1995-07-26 1999-06-15 구본준 반도체 소자 제조방법
TW320752B (en) * 1996-11-18 1997-11-21 United Microelectronics Corp Metal gate electrode process
US5891791A (en) * 1997-05-27 1999-04-06 Micron Technology, Inc. Contamination free source for shallow low energy junction implants
KR100268871B1 (ko) * 1997-09-26 2000-10-16 김영환 반도체소자의제조방법
US6025242A (en) * 1999-01-25 2000-02-15 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
US5998248A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
US6022771A (en) * 1999-01-25 2000-02-08 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions
US5998273A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions
KR100313510B1 (ko) * 1999-04-02 2001-11-07 김영환 반도체 소자의 제조방법
KR100505405B1 (ko) * 1999-06-23 2005-08-05 주식회사 하이닉스반도체 반도체 소자의 게이트 전극 형성방법
US6534402B1 (en) * 2001-11-01 2003-03-18 Winbond Electronics Corp. Method of fabricating self-aligned silicide
KR100475086B1 (ko) * 2002-08-09 2005-03-10 삼성전자주식회사 스플릿 게이트 sonos eeprom 및 그 제조방법
US7271443B2 (en) * 2004-08-25 2007-09-18 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method for the same
WO2007105157A2 (en) * 2006-03-14 2007-09-20 Nxp B.V. Source and drain formation
CN102074465B (zh) * 2009-11-24 2012-04-18 上海华虹Nec电子有限公司 一种双阱制造工艺方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04354328A (ja) * 1991-05-31 1992-12-08 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
EP0526043A1 (en) * 1991-07-16 1993-02-03 Kabushiki Kaisha Toshiba Semiconductor device with low resistance contact and method of manufacturing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208829A (ja) * 1985-03-14 1986-09-17 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2868796B2 (ja) * 1989-09-19 1999-03-10 富士通株式会社 半導体装置の製造方法
JPH0415917A (ja) * 1990-05-09 1992-01-21 Nec Corp シャロウジャンクションの形成方法
KR100209856B1 (ko) * 1990-08-31 1999-07-15 가나이 쓰도무 반도체장치의 제조방법
JPH06163576A (ja) * 1992-11-20 1994-06-10 Nippon Steel Corp 半導体装置の製造方法
US5393687A (en) * 1993-12-16 1995-02-28 Taiwan Semiconductor Manufacturing Company Method of making buried contact module with multiple poly si layers
US5439831A (en) * 1994-03-09 1995-08-08 Siemens Aktiengesellschaft Low junction leakage MOSFETs
US5536676A (en) * 1995-04-03 1996-07-16 National Science Council Low temperature formation of silicided shallow junctions by ion implantation into thin silicon films
US5585295A (en) * 1996-03-29 1996-12-17 Vanguard International Semiconductor Corporation Method for forming inverse-T gate lightly-doped drain (ITLDD) device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04354328A (ja) * 1991-05-31 1992-12-08 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
EP0526043A1 (en) * 1991-07-16 1993-02-03 Kabushiki Kaisha Toshiba Semiconductor device with low resistance contact and method of manufacturing the same

Also Published As

Publication number Publication date
KR0144020B1 (ko) 1998-08-17
KR960032621A (ko) 1996-09-17
US5677213A (en) 1997-10-14
CN1138748A (zh) 1996-12-25
TW369683B (en) 1999-09-11

Similar Documents

Publication Publication Date Title
CN1077723C (zh) 在mosfet的硅衬底上形成低薄层电阻结的方法
US7061058B2 (en) Forming a retrograde well in a transistor to enhance performance of the transistor
JP4708563B2 (ja) 薄くドープされたドレイントランジスタの有効なチャネル長さを減じる方法およびトランジスタを形成する方法
US5516711A (en) Method for forming LDD CMOS with oblique implantation
KR100268979B1 (ko) 반도체 셸로우 접합형성 방법과 셸로우소스 및 드레인 영역을 갖는 전계효과트랜지스터 제조방법
JP3205361B2 (ja) 縦方向電流によるパワーｍｏｓトランジスタを製造するための方法
KR100215163B1 (ko) 개선된 포켓 영역을 갖는 mos 전계 효과 트랜지스터 및 그 제조 방법
JPH0689977A (ja) 垂直ｄｍｏｓトランジスタ構造体とその製造法
US5821147A (en) Integrated circuit fabrication
JPH09232567A (ja) Ｍｏｓゲートパワーデバイス及びその製造方法
KR950034842A (ko) 저 접합 누설 금속산화물 반도체 전계효과 트랜지스터
US5541137A (en) Method of forming improved contacts from polysilicon to silicon or other polysilicon layers
CN1088914C (zh) 制造金属氧化物半导体场效应晶体管的方法
JP2807114B2 (ja) シリコン集積回路の製造に於ける欠陥形成の制御方法、酸化膜の品質及び欠陥形成の制御方法、二重拡散集積回路デバイスセルと、集積回路ｍｏｓｆｅｔセルの形成方法
US6261885B1 (en) Method for forming integrated circuit gate conductors from dual layers of polysilicon
US6396103B1 (en) Optimized single side pocket implant location for a field effect transistor
JPH05121436A (ja) 薄膜トランジスタおよびその製造方法
CN1319880A (zh) 反向短沟道效应的减少
JP2562688B2 (ja) 半導体装置の製造方法
US6410409B1 (en) Implanted barrier layer for retarding upward diffusion of substrate dopant
JPH09172176A (ja) Ｍｏｓデバイス製造方法
JP3397999B2 (ja) 半導体装置の製造方法
JP2544806B2 (ja) 半導体装置の製造方法
KR100327433B1 (ko) 반도체소자의 접합 형성방법
JP2608627B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20020109

Termination date: 20150224

EXPY Termination of patent right or utility model