CN106256019A - 用于将嵌入印刷电路板的构件接合的方法 - Google Patents

用于将嵌入印刷电路板的构件接合的方法 Download PDF

Info

Publication number
CN106256019A
CN106256019A CN201580023025.6A CN201580023025A CN106256019A CN 106256019 A CN106256019 A CN 106256019A CN 201580023025 A CN201580023025 A CN 201580023025A CN 106256019 A CN106256019 A CN 106256019A
Authority
CN
China
Prior art keywords
component
contact
layer
conductor layer
core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201580023025.6A
Other languages
English (en)
Inventor
吉罗德·温蒂妮格
安德烈亚斯·斯洛克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&S Austria Technologie und Systemtechnik AG
Original Assignee
AT&S Austria Technologie und Systemtechnik AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&S Austria Technologie und Systemtechnik AG filed Critical AT&S Austria Technologie und Systemtechnik AG
Publication of CN106256019A publication Critical patent/CN106256019A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

本发明涉及将嵌入印刷电路板(13)的构件(6)接合的方法，其包含以下步骤：a)提供核心(1)，其具有至少一层绝缘层(2)和至少一层施加至绝缘层(2)的导体层(3、4)；b)将最少一个构件(6)嵌入绝缘层(2)的凹处(5)，其中构件(6)的接点(8)是基本上设于核心(1)的具有该至少一层导电层(4)的外表面的平面中；c)在核心(1)的设置了该构件(6)的一外表面上施加可光刻的抗蚀剂(9)，同时填充构件(6)的接点之间的空间；d)通过将该可光刻的抗蚀剂(9)曝光和显影，清除覆盖接点(8)端面和导体层(4)区域的可光刻抗蚀剂(9)，使被其覆盖的该些端面和区域露出；e)通过施用半添加式工艺，将一层(10)导体物料沉积至已露出的接点(8)端面上以及导体层(4)的已露出的范围上，并至少在核心(1)的设置了构件(6)的那一外表面上形成导体图案(12‑12)，以及接点(8)和导体图案(12‑12)之间的互接路径(11)；以及f)将导体层(4+10)的不属于导体图案(12‑12)的部分移除。

Description

用于将嵌入印刷电路板的构件接合的方法
技术领域
本发明涉及用于将嵌入印刷电路板的构件接合的方法。
本发明还涉及印刷电路板，其具有至少一个绝缘层以及至少一个具导体路径的结构化导体层，并具有至少一个构件，其以粘合层嵌入至该印刷电路板的凹处内，其接点基本上位于印刷电路板的展示该至少一导体层的外表面的平面中，并且于构件的接点和导体层的导体路径之间具有导电的连接。
背景技术
专业人士对将构件，尤其是半导体晶片，嵌入印刷电路板结构中是很熟悉的，其中在本发明的范围中，研究的结构是：构件的接点是基本上位于印刷电路板外表面的一平面内的，亦称“表面嵌入式构件”(“surface embedded component”)。必须将构件的电接点与导体图案接合，对于此，已曾应用多种方法。
例如，DE 10 2006 009 723A1说明了将构件嵌入印刷电路板以及将其电接触的方法，其中于金属基质上施加第一绝缘层，以及导体图案。随后是于第一层中创建为晶片而设的窗口或切口，将晶片***其中并留下虚位，并以粘合剂将晶片固定至该基质。在这样做时，晶片的接点被设于背向基质的接合层上。在这构造上施加光刻(photostrukturierte)的第二绝缘层，其不覆盖晶片的接点，然后通过将导体物料电沉积至于晶片的接点和第一层上的导体图案之间以达成电接合。这已知的方法和所产生的产品具有缺点，缺点在于晶片和邻靠的层之间的隔空区域中留下空腔，这在叠上额外的层期间可能导至脱层的问题。
本发明的一目的在于建立一种方法，使用该种方法可容易地及具成本效益地在该些接点的平面中产生导体图案(包括各接合点)而没有脱层的风险。
发明内容
这目的是通过属于上文提及那种的方法达成，其中根据本发明包含以下步骤：
a)提供核心，其具有至少一层绝缘层和至少一层施加至该绝缘层的导电层；
b)将最少一个构件嵌入绝缘层的凹处，其中该构件的接点是基本上设于印刷电路板的具有该至少一层导电层的外表面的平面中；
c)在核心的设置了该构件的该一外表面上施加可光刻(photostrukturierbaren)的漆料，同时填充构件的接点之间的空间；
d)通过将该可光刻的漆料曝光和显影，清除覆盖接点端面和导体层区域的可光刻漆料，使被其覆盖的该些端面和区域露出；
e)采用半添加式工艺，将导体物料沉积至露出了的接点端面上以及导体层的露出了的区域上，并至少在核心的设置了构件的该一外表面上形成导体图案，以及形成连接接点和导体图案的互接路径；以及
f)将导体层的不属于导体图案的部分移除。
使用本发明，可将嵌入的构件于和嵌入处相同的位置或平面“接线”，以致可把印刷电路板设计为更薄，而不会出现上述的脱层风险的问题。
在这样做时，建议通过闪蚀(Flash-Etching)这种蚀刻工艺执行步骤f)中导体层的部分移除。
该可光刻漆料作为印刷电路板完成品的一部分具有额外功能，所以如果步骤c)中采用的可光刻漆料是基于环氧树脂的漆料，则是有利的。
在根据本发明的方法的一特别有利的变种中，可指定于步骤b)中采用粘合层将构件嵌入该核心的凹处，其中该粘合层完全包覆构件的所有表面—具接点的表面除外—并基本上延伸至印刷电路板的设有接点端面的表面的平面。
在一特别权宜的方式中，核心的凹处延伸穿过导体层，进入绝缘层中。
所述目的亦可通过属于上文提及該种的印刷电路板达成，其中根据本发明，该导体层的导体路径以及该些连接皆设于同一平面，其中该粘合层完全包覆该构件的所有表面，具接点的表面除外，其中构件的接点之间的空间以固化了的可光刻漆料填充，而额外的导电层被施加至该些接点的端面以及印刷电路板的导电层的导体路径的范围。
在优选的实施方案中，指定在构件外壁和印刷电路板凹处的内壁之间，该固化了的可光刻漆料覆盖粘合层的已露出的端面。
在本发明的一先进的实施方案中，该印刷电路板也是包含核心，其包含至少一层绝缘层及施加至该绝缘层上的至少一层导体层，其中该核心的设有至少一导体层的一外层具有凹处，其延伸穿过导体层进入绝缘层，其中以粘合层将构件嵌入核心的凹处内，且其中构件的接点基本上设于具有该至少一个导体层和该凹处的外表面的平面中。
附图说明
以下基于这方法和这印刷电路板的一以示图示出的实施例更详细地说明本发明及其进一步的优点。在示图中，
图1以经过一不完整部分的截面，示出于方法的头几步中制成的核心的截面，有构件嵌入于其内；
图2示出图1的结构在施加可光刻漆料后的情况；
图3示出将该可光刻漆料曝光和显影后的结构；
图4示出通过施行半添加式工艺将额外的导电物料沉积后的结构；而
图5示出将部分的导电镀层蚀去后的印刷电路板完成品的结构。
具体实施方式
现将参照示图解释根据本发明的方法以及本发明的印刷电路板。在这说明中，在以下的这代表性说明的语境中所用的术语“核心”应被理解为意指固化了的预浸渍物料，其于至少一表面上具有导体层(铜层)。
图1示出核心1的截面，其包含绝缘层2，其例如以FR 4之类等印刷电路板工业中常用的预浸渍物料构成；亦包含上导体层3和下导体层4。这里应留意，“上”和“下”这些词语只是代表示图中的方向，并用作简化说明。层的厚度例如是：绝缘层2一百微米，上导体层3和下导体层4一至五微米，一般2微米。
在核心1中形成凹处5，利用粘合层7将构件6嵌入该凹处，其中这粘合层的厚度例如为20至200微米。该构件6例如为半导体晶片，并于其外表面带有例如为铜焊盘的接点8，其中粘合层7包覆构件6的所有表面，具接点8的那些表面除外；该粘合层还基本上延伸至核心1的设有接点8的端面的表面的平面，在这例子中即为底部表面的平面。一可用的粘合剂例如为无溶剂或低溶剂量的环氧树脂粘合剂，其具有一般为120℃和150℃之间的玻璃软化点(Glaserweichungspunkt)，并将被压、填或注入凹处5中。置入构件6后，将以110℃至150℃的温度将这粘合剂固化。
在下一步中，将基于环氧树脂的可光刻的抗蚀剂9至少施加至核心1的具接点8的端面的外表面，这里参照图2。适于这用途的产品和物料例如有Huntsman公司商品名为的XB7081漆料，或Microchem公司的以用于光刻电铸(lithographischenGalvanikabformung(LIGA))闻名的SU-8光致抗蚀剂。如图示，抗蚀剂9填满构件6的接点8之间的所有空间，亦延伸横越下导体层4。
此后，可采用印刷电路板生产中常用的光刻工艺以创造图案(结构化)，这是以曝光开始，其以薄膜屏蔽或激光直接成像(LDI)执行。随后是显影、以合适的化学剂洗脱后获得图案，以及将物料完全固化。固化是通过常规的固化方法执行的，例如是热固化、UV固化或IR固化、施加激光幅射等。执行结构化和曝光的方式导致将露出接点8，更具体而言是露出其端面，这里参照图3。执行这结构化/曝光的方式导致该固化了的可光刻抗蚀剂9于构件6的外壁和核心1的凹处5的内壁之间覆盖粘合层7的露出的端面，并导致下导体层4再度露出。
在这曝光和显影后，根据期望的图案施行半添加式工艺，该工艺是用于施加导体物料的，例如铜。这样做，导致将一层(10)导体物料施加至期望的范围，特别是用于导体路径，其亦于形成从端面8开始至所其望的导体图案的互接路径11之下沉积。而下导体层4则在期望的导体路径或导体图案的范围内被扩大。这样的结果于图4示出。
由于下导体层4至层10的加厚了的部分(其用于形成导体路径)之间仍存有桥接4b，所以要以额外的步骤将这些桥接4b和其它不适用的导体物料移除。优选地，这是以所谓的“闪蚀”这种蚀刻工艺执行，意即将基层的铜箔蚀去，以及将电沉积的铜层小部分地移除。这蚀刻的过程例如以酸性环境执行，例如是添加了H2O2和稳定剂的HCl，其中基层薄膜的小微晶结构被溶解的速度远比电沉积的层被溶解的速度快，从而达成选择性的蚀刻。在这移除和蚀刻的过程后，亦清洁了接点9之间的表面和空间，而最后的导体路径12已显露出来并完全形成，如图5所示；其示出带有嵌入和接合了的构件6的印刷电路板完成品13。
在所示的例子中，只说明了下导体层4的结构化，但上导体层3亦可以同样方法图案化，这应该是明显的。亦可于两导体层之间形成通路(传导性馈送通路)，就如可形成额外的绝缘和导体层般。
最后，应理解，图1至5的示图总体而言只是详示某更大型的印刷电路板图案的某些部分，而实际上，可于印刷电路板的不同地方将多个构件嵌入和连接至导体图案。

Claims (8)

1.用于将嵌入印刷电路板(13)的构件(6)接合的方法，其特征在于以下步骤：
a)提供核心(1)，其具有至少一层绝缘层(2)和至少一层施加至绝缘层(2)的导体层(3、4)；
b)将最少一个构件(6)嵌入绝缘层(2)的凹处(5)，其中构件(6)的接点(8)是基本上设于核心(1)的具有该至少一层导电层(4)的外表面的平面中；
c)在核心(1)的设置了该构件(6)的一外表面上施加可光刻的抗蚀剂(9)，同时填充构件(6)的接点之间的空间；
d)通过将该可光刻的抗蚀剂(9)曝光和显影，清除覆盖接点(8)端面和导体层(4)区域的可光刻抗蚀剂(9)，使被其覆盖的该些端面和区域露出；
e)通过施用半添加式工艺，将一层(10)导体物料沉积至已露出的接点(8)端面上以及导体层(4)的已露出的范围上，并至少在核心(1)的设置了构件(6)的那一外表面上形成导体图案(12-12)，以及接点(8)和导体图案(12-12)之间的互接路径(11)；
以及
f)将导体层(4+10)的不属于导体图案(12-12)的部分移除。
2.如权利要求1所述的方法，其特征在于步骤f)中导体层(4+10)的区域移除是通过闪蚀发生的。
3.如权利要求1或2的方法，其特征在于步骤c)中采用的可光刻抗蚀剂(9)是基于环氧树脂的漆料。
4.如权利要求1至3之任一所述的方法，其特征在于在步骤b)中采用粘合层(7)将构件(6)嵌入该核心(1)的凹处(5)，其中该粘合层(7)完全包覆构件(6)的所有表面，具接点(8)的表面除外，并基本上延伸至印刷电路板(13)的设有接点端面的表面的平面。
5.如权利要求4所述的方法，其特征在于核心(1)的凹处(5)延伸穿过导体层(4)，进入绝缘层(2)中。
6.印刷电路板(13)，其具有至少一个绝缘层(2)以及至少一个具导体路径(12)的图形化导体层(4+10)，并具有至少一个构件(6)，其以粘合层(7)嵌入至该印刷电路板的凹处(5)进入绝缘层(2)内，接点(8)基本上位于印刷电路板(13)的具有该至少一导体层(4)及该凹处(5)的外表面的平面中，而于构件(6)的接点(8)和图形化导体层(4+10)的导体路径(12)之间具有导电的连接(11)，
其特征在于
该结构化导体层(4+10)的导体路径(12)以及该些导电连接(11)的表面皆处于同一平面；
该粘合层(7)完全包覆该构件(6)的所有表面，具接点(8)的表面除外；
构件(6)的接点(8)之间的空间以固化了的可光刻抗蚀剂(9)填充；而
额外的导电层(10)被施加至该些接点(8)的端面以及印刷电路板(13)的导电层(4)的导体路径(12)的范围。
7.如权利要求6所述的印刷电路板(13)，其特征在于在构件(6)外壁和凹处(5)内壁之间，以固化了的可光刻抗蚀剂(9)覆盖粘合层(7)的露出的端面。
8.如权利要求6或7所述的印刷电路板(13)，其进一步包含核心(1)，其包含至少一层绝缘层(2)及施加至该绝缘层(2)上的至少一层导体层(3、4)，其中该核心(1)的设有至少一层导体层(4)的一外层具有凹处(5)，其延伸穿过导体层(4)进入绝缘层(2)，其特征在于以粘合层(7)将构件(6)嵌入核心(1)的凹处(5)内，其中构件(6)的接点(8)基本上设于该核心(1)的具有该至少一个导体层(4)和该凹处(5)的外表面的平面中。
CN201580023025.6A 2014-02-27 2015-02-26 用于将嵌入印刷电路板的构件接合的方法 Pending CN106256019A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
ATA50152/2014A AT515447B1 (de) 2014-02-27 2014-02-27 Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte
ATA50152/2014 2014-02-27
PCT/AT2015/050052 WO2015127489A1 (de) 2014-02-27 2015-02-26 Verfahren zum kontaktieren eines in eine leiterplatte eingebetteten bauelements sowie leiterplatte

Publications (1)

Publication Number Publication Date
CN106256019A true CN106256019A (zh) 2016-12-21

Family

ID=52874873

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580023025.6A Pending CN106256019A (zh) 2014-02-27 2015-02-26 用于将嵌入印刷电路板的构件接合的方法

Country Status (5)

Country Link
US (1) US10187997B2 (zh)
EP (1) EP3111734B1 (zh)
CN (1) CN106256019A (zh)
AT (1) AT515447B1 (zh)
WO (1) WO2015127489A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112203433A (zh) * 2019-07-07 2021-01-08 深南电路股份有限公司 埋入式电路板的制造方法、埋入式电路板以及应用

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3075006A1 (de) 2013-11-27 2016-10-05 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Leiterplattenstruktur
AT515101B1 (de) 2013-12-12 2015-06-15 Austria Tech & System Tech Verfahren zum Einbetten einer Komponente in eine Leiterplatte
AT515447B1 (de) 2014-02-27 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte
US11523520B2 (en) 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
US11178772B2 (en) 2018-03-29 2021-11-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier connected with a separate tilted component carrier for short electric connection
CN113540029A (zh) * 2020-04-16 2021-10-22 奥特斯奥地利科技与***技术有限公司 部件承载件以及制造和设计部件承载件的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1156949A (zh) * 1995-11-16 1997-08-13 松下电器产业株式会社 印刷电路板及其安装体
US6309912B1 (en) * 2000-06-20 2001-10-30 Motorola, Inc. Method of interconnecting an embedded integrated circuit
US20080067666A1 (en) * 2006-09-19 2008-03-20 Phoenix Precision Technology Corporation Circuit board structure with embedded semiconductor chip and method for fabricating the same
US20090194318A1 (en) * 2008-02-04 2009-08-06 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method for manufacturing the same
WO2013029074A1 (de) * 2011-08-31 2013-03-07 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Verfahren zur integration eines bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt

Family Cites Families (127)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH667359A5 (de) 1985-03-27 1988-09-30 Ppc Electronic Ag Verfahren zur herstellung einer starre und flexible partien aufweisenden leiterplatte fuer gedruckte elektrische schaltungen.
DE3777995D1 (de) 1986-12-22 1992-05-07 Siemens Ag Verfahren zur befestigung von elektronischen bauelementen auf einem substrat, folie zur durchfuehrung des verfahrens und verfahren zur herstellung der folie.
US4931134A (en) 1989-08-15 1990-06-05 Parlex Corporation Method of using laser routing to form a rigid/flex circuit board
US5206188A (en) 1990-01-31 1993-04-27 Ibiden Co., Ltd. Method of manufacturing a high lead count circuit board
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
BE1007714A3 (nl) * 1993-11-09 1995-10-03 Philips Electronics Nv Werkwijze voor het vervaardigen van een plaat van elektrisch isolerend materiaal met een patroon van gaten en/of holtes.
US5645673A (en) 1995-06-02 1997-07-08 International Business Machines Corporation Lamination process for producing non-planar substrates
JPH09266268A (ja) 1996-03-28 1997-10-07 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置のパッケージ
DE19642488A1 (de) * 1996-10-15 1998-04-16 Bernd Klose Verfahren zur Kontaktierung von Mikrochips und zur Herstellung von Mehrlagen-Dünnschichtleiterplatten, insbesondere für superflache Multichip-Modul- und Chipcard-Anwendungen
US5868950A (en) 1996-11-08 1999-02-09 W. L. Gore & Associates, Inc. Method to correct astigmatism of fourth yag to enable formation of sub 25 micron micro-vias using masking techniques
JPH11150368A (ja) 1997-11-19 1999-06-02 Toshiba Chem Corp フレックスリジッド配線板の製造方法
US6281446B1 (en) 1998-02-16 2001-08-28 Matsushita Electric Industrial Co., Ltd. Multi-layered circuit board and method of manufacturing the same
US6120693A (en) 1998-11-06 2000-09-19 Alliedsignal Inc. Method of manufacturing an interlayer via and a laminate precursor useful for same
JP3656484B2 (ja) 1999-03-03 2005-06-08 株式会社村田製作所 セラミック多層基板の製造方法
JP2001053447A (ja) * 1999-08-05 2001-02-23 Iwaki Denshi Kk 部品内蔵型多層配線基板およびその製造方法
US6405429B1 (en) 1999-08-26 2002-06-18 Honeywell Inc. Microbeam assembly and associated method for integrated circuit interconnection to substrates
US6442033B1 (en) 1999-09-24 2002-08-27 Virginia Tech Intellectual Properties, Inc. Low-cost 3D flip-chip packaging technology for integrated power electronics modules
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
DE19954941C2 (de) 1999-11-16 2003-11-06 Fraunhofer Ges Forschung Verfahren zum Integrieren eines Chips innerhalb einer Leiterplatte
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
EP1990833A3 (en) * 2000-02-25 2010-09-29 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
US6384473B1 (en) 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6459593B1 (en) 2000-08-10 2002-10-01 Nortel Networks Limited Electronic circuit board
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
TW511415B (en) 2001-01-19 2002-11-21 Matsushita Electric Ind Co Ltd Component built-in module and its manufacturing method
FR2822338B1 (fr) 2001-03-14 2003-06-27 Sagem Procede pour connecter electriquement des plots de contact d'un composant microelectronique directement a des pistes de circuits imprimes, et plaque a circuits imprimes ainsi constituee
JP3963661B2 (ja) 2001-05-10 2007-08-22 株式会社荏原製作所 無電解めっき方法及び装置
JP3736679B2 (ja) 2001-07-18 2006-01-18 日立エーアイシー株式会社 プリント配線板
TW550997B (en) 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
JP3935353B2 (ja) 2001-12-26 2007-06-20 シャープ株式会社 フレキシブルビルドアップ配線板の製造方法
JP3941573B2 (ja) 2002-04-24 2007-07-04 宇部興産株式会社 フレキシブル両面基板の製造方法
JP2004031682A (ja) 2002-06-26 2004-01-29 Sony Corp プリント配線基板の製造方法
DE20221189U1 (de) 2002-09-19 2005-05-19 Ruwel Ag Leiterplatte mit mindestens einem starren Bereich und mindestens einem flexiblen Bereich
JP4209178B2 (ja) 2002-11-26 2009-01-14 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP2004200209A (ja) 2002-12-16 2004-07-15 Fuji Xerox Co Ltd 電極等の導電パターンの形成方法およびこれを用いた面発光型半導体レーザ並びにその製造方法
JP2004214249A (ja) 2002-12-27 2004-07-29 Renesas Technology Corp 半導体モジュール
US7894203B2 (en) 2003-02-26 2011-02-22 Ibiden Co., Ltd. Multilayer printed wiring board
JP4303610B2 (ja) 2003-05-19 2009-07-29 富士フイルム株式会社 多層配線基板、部品実装方法、及び、撮像装置
FI20031201A (fi) 2003-08-26 2005-02-27 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
US7652381B2 (en) 2003-11-13 2010-01-26 Interconnect Portfolio Llc Interconnect system without through-holes
WO2005050708A2 (en) 2003-11-13 2005-06-02 Silicon Pipe, Inc. Stair step printed circuit board structures for high speed signal transmissions
ITUD20040034A1 (it) 2004-02-27 2004-05-27 Eurotech Spa Scheda di espansione multistrato per apparecchiatura elettronica e relativo
US20050233122A1 (en) 2004-04-19 2005-10-20 Mikio Nishimura Manufacturing method of laminated substrate, and manufacturing apparatus of semiconductor device for module and laminated substrate for use therein
JP4251144B2 (ja) 2004-04-19 2009-04-08 パナソニック株式会社 積層基板の製造方法
FI20041680A (fi) 2004-04-27 2005-10-28 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
US20060008970A1 (en) 2004-07-08 2006-01-12 International Business Machines Corporation Optimized plating process for multilayer printed circuit boards having edge connectors
FI117812B (fi) 2004-08-05 2007-02-28 Imbera Electronics Oy Komponentin sisältävän kerroksen valmistaminen
TWI241007B (en) 2004-09-09 2005-10-01 Phoenix Prec Technology Corp Semiconductor device embedded structure and method for fabricating the same
US7326857B2 (en) 2004-11-18 2008-02-05 International Business Machines Corporation Method and structure for creating printed circuit boards with stepped thickness
JP4800606B2 (ja) 2004-11-19 2011-10-26 Ｏｋｉセミコンダクタ株式会社 素子内蔵基板の製造方法
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
JP2006237517A (ja) 2005-02-28 2006-09-07 Sanyo Electric Co Ltd 回路装置およびその製造方法
WO2006095852A1 (ja) 2005-03-10 2006-09-14 Kyocera Corporation 電子部品モジュール及びその製造方法
KR20060106891A (ko) 2005-04-04 2006-10-12 마츠시타 덴끼 산교 가부시키가이샤 광학 디바이스용 캐비티 구조체, 광학 디바이스 및 광학디바이스용 캐비티 구조체의 제조방법
FI122128B (fi) 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
JP4771135B2 (ja) 2006-01-12 2011-09-14 日立化成工業株式会社 プリント配線板、それを使用したｌｅｄ装置及びプリント配線板の製造方法
AT503191B1 (de) 2006-02-02 2008-07-15 Austria Tech & System Tech Leiterplattenelement mit wenigstens einem eingebetteten bauelement sowie verfahren zum einbetten zumindest eines bauelements in einem leiterplattenelement
DE102006009723A1 (de) 2006-03-02 2007-09-06 Siemens Ag Verfahren zum Herstellen und planaren Kontaktieren einer elektronischen Vorrichtung und entsprechend hergestellte Vorrichtung
US7977579B2 (en) 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system
JP4954765B2 (ja) 2006-04-25 2012-06-20 日本特殊陶業株式会社 配線基板の製造方法
JP5082321B2 (ja) 2006-07-28 2012-11-28 大日本印刷株式会社 多層プリント配線板及びその製造方法
GB2485087B (en) 2006-08-30 2012-06-13 Denso Corp Power electronic package having two substrates with multiple semiconductor chips and electronic components
JP2008166736A (ja) 2006-12-06 2008-07-17 Hitachi Via Mechanics Ltd プリント基板の製造方法およびプリント基板加工機
AT11664U1 (de) 2007-02-16 2011-02-15 Austria Tech & System Tech Verfahren zum entfernen eines teilbereichs einer flächigen materialschicht sowie mehrlagige struktur und verwendung hiefür
AT11663U1 (de) 2007-02-16 2011-02-15 Austria Tech & System Tech Haftverhinderungsmaterial, verfahren zum entfernen eines teilbereichs einer flächigen materialschicht sowie mehrlagige struktur und verwendung hiefür
DE102007010731A1 (de) 2007-02-26 2008-08-28 Würth Elektronik GmbH & Co. KG Verfahren zum Einbetten von Chips und Leiterplatte
KR100885899B1 (ko) 2007-04-27 2009-02-26 삼성전기주식회사 인쇄회로기판 및 그 제조 방법
JP5013973B2 (ja) 2007-05-31 2012-08-29 株式会社メイコー プリント配線板及びその製造方法、並びに、このプリント配線板を用いた電子部品収容基板及びその製造方法
US8237259B2 (en) 2007-06-13 2012-08-07 Infineon Technologies Ag Embedded chip package
JP2009021426A (ja) 2007-07-12 2009-01-29 Sharp Corp チップ部品型ｌｅｄ及びその製造方法
TWI345432B (en) 2007-07-26 2011-07-11 Nan Ya Printed Circuit Board Corp Method for manufacturing a rigid-flex circuit board
US7935893B2 (en) 2008-02-14 2011-05-03 Ibiden Co., Ltd. Method of manufacturing printed wiring board with built-in electronic component
CN101547574B (zh) 2008-03-28 2011-03-30 富葵精密组件(深圳)有限公司 电路板基板及具有断差结构的电路板的制作方法
KR20090117237A (ko) 2008-05-09 2009-11-12 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조방법
AT10247U8 (de) 2008-05-30 2008-12-15 Austria Tech & System Tech Verfahren zur integration wenigstens eines elektronischen bauteils in eine leiterplatte sowie leiterplatte
WO2009147936A1 (ja) 2008-06-02 2009-12-10 イビデン株式会社 多層プリント配線板の製造方法
DE102008040906A1 (de) 2008-07-31 2010-02-04 Robert Bosch Gmbh Leiterplatine mit elektronischem Bauelement
JP2010114434A (ja) 2008-10-08 2010-05-20 Ngk Spark Plug Co Ltd 部品内蔵配線基板及びその製造方法
AT12316U1 (de) 2008-10-30 2012-03-15 Austria Tech & System Tech Verfahren zur integration eines elektronischen bauteils in eine leiterplatte
KR20110076979A (ko) 2008-10-30 2011-07-06 에이티 앤 에스 오스트리아 테크놀로지 앤 시스템테크니크 악치엔게젤샤프트 인쇄회로기판에 전자부품을 통합하는 방법
TWI458400B (zh) 2008-10-31 2014-10-21 Taiyo Yuden Kk Printed circuit board and manufacturing method thereof
FI122216B (fi) 2009-01-05 2011-10-14 Imbera Electronics Oy Rigid-flex moduuli
AT12322U1 (de) 2009-01-27 2012-03-15 Dcc Dev Circuits & Components Gmbh Verfahren zur herstellung einer mehrlagigen leiterplatte, haftverhinderungsmaterial sowie mehrlagige leiterplatte und verwendung eines derartigen verfahrens
JP2010206124A (ja) 2009-03-06 2010-09-16 Sumitomo Bakelite Co Ltd 多層回路基板の製造方法及び多層回路基板
TWI392404B (zh) 2009-04-02 2013-04-01 Unimicron Technology Corp 線路板及其製作方法
US8186042B2 (en) 2009-05-06 2012-05-29 Bae Systems Information And Electronic Systems Integration Inc. Manufacturing method of a printed board assembly
US7863735B1 (en) 2009-08-07 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof
JP5296636B2 (ja) * 2009-08-21 2013-09-25 新光電気工業株式会社 半導体パッケージの製造方法
KR101095130B1 (ko) 2009-12-01 2011-12-16 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
US8664043B2 (en) 2009-12-01 2014-03-04 Infineon Technologies Ag Method of manufacturing a laminate electronic device including separating a carrier into a plurality of parts
JP5490525B2 (ja) 2009-12-28 2014-05-14 日本シイエムケイ株式会社 部品内蔵型多層プリント配線板及びその製造方法
CN102131348A (zh) 2010-01-20 2011-07-20 奥特斯(中国)有限公司 用于制造刚性-柔性的印刷电路板的方法
JP2011148930A (ja) 2010-01-22 2011-08-04 Nitto Denko Corp 粘着シート
US8354743B2 (en) 2010-01-27 2013-01-15 Honeywell International Inc. Multi-tiered integrated circuit package
CN102860144B (zh) 2010-02-12 2016-03-02 Lg伊诺特有限公司 具有腔的pcb及其制造方法
US8227344B2 (en) 2010-02-26 2012-07-24 Tokyo Electron Limited Hybrid in-situ dry cleaning of oxidized surface layers
KR101067109B1 (ko) 2010-04-26 2011-09-26 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
US8519270B2 (en) 2010-05-19 2013-08-27 Unimicron Technology Corp. Circuit board and manufacturing method thereof
KR101085733B1 (ko) * 2010-05-28 2011-11-21 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조방법
US8289727B2 (en) 2010-06-11 2012-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package substrate
KR101710178B1 (ko) 2010-06-29 2017-02-24 삼성전자 주식회사 임베디이드 칩 온 칩 패키지 및 이를 포함하는 패키지 온 패키지
EP2416633A1 (de) 2010-08-04 2012-02-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Verfahren ur Festlegung und/oder Einbettung eines elektronischen Bauteils sowie Kleber zur Verwendung in einem derartigen Verfahren
JP2012044102A (ja) 2010-08-23 2012-03-01 Hitachi Cable Ltd 発光装置及びその製造方法並びに配線基板
DE102010042567B3 (de) 2010-10-18 2012-03-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen eines Chip-Package und Chip-Package
AT13430U1 (de) 2010-11-19 2013-12-15 Austria Tech & System Tech Verfahren zum festlegen eines bauteils in bzw. an einer leiterplatte sowie leiterplatte
US8735739B2 (en) 2011-01-13 2014-05-27 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
JP5830864B2 (ja) 2011-01-20 2015-12-09 大日本印刷株式会社 キャパシタ内蔵配線板、キャパシタ内蔵配線板の製造方法
AT13055U1 (de) * 2011-01-26 2013-05-15 Austria Tech & System Tech Verfahren zur integration eines elektronischen bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt
JP5540276B2 (ja) 2011-03-31 2014-07-02 Ｔｄｋ株式会社 電子部品内蔵基板及びその製造方法
AT13432U1 (de) 2011-08-31 2013-12-15 Austria Tech & System Tech Verfahren zur integration eines bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt
KR101253514B1 (ko) 2011-10-27 2013-04-11 아페리오(주) 열팽창수축률 차이로 인한 기판 휨 문제 해결방법 및 이를 적용한 전자부품 내장형 인쇄회로기판
US8975711B2 (en) 2011-12-08 2015-03-10 Infineon Technologies Ag Device including two power semiconductor chips and manufacturing thereof
US9040837B2 (en) 2011-12-14 2015-05-26 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
AT13434U1 (de) 2012-02-21 2013-12-15 Austria Tech & System Tech Verfahren zur Herstellung einer Leiterplatte und Verwendung eines derartigen Verfahrens
US20130256884A1 (en) * 2012-03-27 2013-10-03 Intel Mobile Communications GmbH Grid fan-out wafer level package and methods of manufacturing a grid fan-out wafer level package
AT513047B1 (de) 2012-07-02 2014-01-15 Austria Tech & System Tech Verfahren zum Einbetten zumindest eines Bauteils in eine Leiterplatte
CN203072250U (zh) 2012-12-20 2013-07-17 奥特斯(中国)有限公司 用于生产印制电路板的半成品及印制电路板
CN203015273U (zh) 2012-12-24 2013-06-19 奥特斯(中国)有限公司 印制电路板
CN203072246U (zh) 2012-12-31 2013-07-17 奥特斯(中国)有限公司 用于生产印制电路板的半成品
CN203206586U (zh) 2013-02-27 2013-09-18 奥特斯(中国)有限公司 用于生产印制电路板的半成品
KR20140110553A (ko) 2013-03-08 2014-09-17 삼성디스플레이 주식회사 이방성 도전 필름, 표시 장치, 및 표시 장치의 제조 방법
AT514085B1 (de) 2013-06-11 2014-10-15 Austria Tech & System Tech Leistungsmodul
EP3075006A1 (de) 2013-11-27 2016-10-05 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Leiterplattenstruktur
US9949376B2 (en) 2013-12-06 2018-04-17 Second Sight Medical Products, Inc. Cortical implant system for brain stimulation and recording
AT515101B1 (de) 2013-12-12 2015-06-15 Austria Tech & System Tech Verfahren zum Einbetten einer Komponente in eine Leiterplatte
AT515372B1 (de) 2014-01-29 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zur Herstellung einer Leiterplatte
AT515447B1 (de) 2014-02-27 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1156949A (zh) * 1995-11-16 1997-08-13 松下电器产业株式会社 印刷电路板及其安装体
US6309912B1 (en) * 2000-06-20 2001-10-30 Motorola, Inc. Method of interconnecting an embedded integrated circuit
US20080067666A1 (en) * 2006-09-19 2008-03-20 Phoenix Precision Technology Corporation Circuit board structure with embedded semiconductor chip and method for fabricating the same
US20090194318A1 (en) * 2008-02-04 2009-08-06 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method for manufacturing the same
WO2013029074A1 (de) * 2011-08-31 2013-03-07 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Verfahren zur integration eines bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112203433A (zh) * 2019-07-07 2021-01-08 深南电路股份有限公司 埋入式电路板的制造方法、埋入式电路板以及应用
US11632861B2 (en) 2019-07-07 2023-04-18 Shennan Circuits Co., Ltd. Method for manufacturing embedded circuit board, embedded circuit board, and application

Also Published As

Publication number Publication date
AT515447B1 (de) 2019-10-15
US10187997B2 (en) 2019-01-22
EP3111734B1 (de) 2018-01-24
EP3111734A1 (de) 2017-01-04
US20170048984A1 (en) 2017-02-16
AT515447A1 (de) 2015-09-15
WO2015127489A1 (de) 2015-09-03

Similar Documents

Publication Publication Date Title
CN106256019A (zh) 用于将嵌入印刷电路板的构件接合的方法
EP3148298B1 (en) Manufacturing method of printing circuit board with micro-radiators
KR100796983B1 (ko) 인쇄회로기판 및 그 제조방법
FI119714B (fi) Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi
JP2008522396A (ja) 電子モジュールの製造方法
TW200826770A (en) Method for forming transcriptional circuit and method for manufacturing circuit board
US11570904B2 (en) Method for contacting and rewiring an electronic component embedded into a printed circuit board
DE102015120745B4 (de) Chip-Schutzumhüllung und -verfahren
US20230189448A1 (en) Method for Making Contact with a Component Embedded in a Printed Circuit Board
US20150090688A1 (en) Method of fabricating printed circuit board (pcb) substrate having a cavity
CN104183557B (zh) 模块及其制造方法
JP5294285B1 (ja) コイル素子、コイル素子集合体及びコイル部品の製造方法
KR20090096809A (ko) 반도체 부품 내장형 인쇄회로기판 제조 방법
US8677615B2 (en) Method for embedding electrical components
CN1607898A (zh) 电路底板的制造方法及电路底板
CN106328625A (zh) 封装基板及其制作方法
TW201720256A (zh) 柔性電路板製作方法
TWI376178B (en) Method for manufacturing printed circuit board
CN103779240B (zh) 制造电路板的方法及使用其制造的芯片封装件和电路板
JP2005045163A (ja) 多層回路板の製造方法
JP2006179782A (ja) 半導体基板の製造方法
WO2012148332A1 (en) Manufacturing method for printed circuit boards
CN109906506A (zh) 电子部件及其制造方法
JP2006296128A (ja) 静電モータ用電極の製造方法、静電モータ用電極及び静電モータ
US10049935B2 (en) Integrated circuit package having pin up interconnect

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB03 Change of inventor or designer information

Inventor after: Weidinger Gerald

Inventor after: Zluc Andreas

Inventor after: Stahr Johannes

Inventor before: Weidinger Gerald

Inventor before: Zluc Andreas

CB03 Change of inventor or designer information
RJ01 Rejection of invention patent application after publication

Application publication date: 20161221

RJ01 Rejection of invention patent application after publication