CN105489618B - 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法 - Google Patents

薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法 Download PDF

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CN105489618B
CN105489618B CN201610046347.9A CN201610046347A CN105489618B CN 105489618 B CN105489618 B CN 105489618B CN 201610046347 A CN201610046347 A CN 201610046347A CN 105489618 B CN105489618 B CN 105489618B
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CN105489618A (zh
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姚江波
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种薄膜晶体管阵列基板及其制备方法。该方法包括：提供基板，基板包括相对设置的第一表面及第二表面；形成栅极，栅极设置在第一表面上；形成第一绝缘层，第一绝缘层覆盖在栅极上；在第一绝缘层上形成金属氧化物半导体层；对金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为源极和漏极，未经过离子注入的金属氧化物半导体层的区域为有源层；形成第二绝缘层，第二绝缘层覆盖源极、漏极及有源层；在第二绝缘层上开设用于裸露源极或漏极的贯孔；形成像素电极，像素电极设置在第二绝缘层上，并通过贯孔与源极或漏极连接。

Description

薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法
技术领域
本发明涉及液晶显示领域，尤其涉及一种薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法。
背景技术
在液晶显示领域，薄膜晶体管阵列基板(Thin Film Transistor Array)包括呈阵列分布的多个薄膜晶体管(Thin Film Transistor，TFT)。薄膜晶体管一般用作开关元件来控制像素电极的作业，或者用作驱动元件来驱动像素。薄膜晶体管阵列基板中的薄膜晶体管的有源层之上通常覆盖蚀刻保护层，目的是为了在进行源极和栅极蚀刻时保护所述有源层不受破坏，在这种结构的薄膜晶体管中通常需要将蚀刻阻挡层图案化，从而增加了一道掩膜板工序来进行蚀刻阻挡层的图案化，从而增加了所述薄膜晶体管阵列基板的制备时间。
发明内容
本发明提供一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
基板，所述基板包括相对设置的第一表面及第二表面；
栅极，设置在所述第一表面上；
第一绝缘层，覆盖在所述栅极上；
有源层，设置在所述第一绝缘层远离所述基板的表面上；
源极和漏极，所述源极和所述漏极分别设置在所述第一绝缘层上且分别设置于所述有源层的相对的两端，并且所述源极和所述漏极分别与所述有源层的端面接触；
第二绝缘层，所述第二绝缘层覆盖所述有源层、所述源极及所述漏极，所述第二绝缘层上设置用于裸露所述源极或所述漏极的贯孔；
像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接。
其中，所述薄膜晶体管阵列基板还包括：
所述第二绝缘层上开设有第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置，所述像素电极通过所述第二贯孔与所述漏极连接；
所述薄膜晶体管阵列基板还包括第一电极，所述第一电极通过所述第一贯孔与所述源极相连。
其中，所述第一电极与所述像素电极在同一工序中制备。
其中，所述有源层包括金属氧化物半导体，所述源极和漏极包括经离子注入的金属氧化物半导体。
其中，所述有源层包括铟镓锌氧化物、铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
本发明还提供了一种薄膜晶体管阵列基板的制备方法，所述薄膜晶体管阵列基板的制备方法包括：
提供基板，所述基板包括相对设置的第一表面及第二表面；
形成栅极，所述栅极设置在所述第一表面上；
形成第一绝缘层，所述第一绝缘层覆盖在所述栅极上；
在所述第一绝缘层上形成金属氧化物半导体层；
对所述金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为源极和漏极，未经过离子注入的金属氧化物半导体层的区域为有源层；
形成第二绝缘层，所述第二绝缘层覆盖所述源极、所述漏极及所述有源层；
在所述第二绝缘层上开设用于裸露所述源极或所述漏极的贯孔；
形成像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接。
其中，所述步骤“在所述第二绝缘层上开设用于裸露所述源极或所述漏极的贯孔”包括：
在所述第二绝缘层上开设第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置；
相应地，所述步骤“形成像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接”包括：
形成像素电极，所述像素电极设置在所述第二绝缘层上，且所述像素电极通过所述第二贯孔与所述漏极连接；
所述薄膜晶体管阵列基板的制备方法还包括：
形成第一电极，所述第一电极通过所述第一贯孔与所述源极相连。
其中，所述步骤“对所述金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为源极和漏极，未经过离子注入的金属氧化物半导体层的区域形成有源层”包括：
在所述金属氧化物半导体层上覆盖第一光阻层；
图案化所述第一光阻层，以露出所述金属氧化物半导体层的两端区域；
以图案化的所述第一光阻层为掩膜对所述金属氧化物半导体层进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为所述源极和所述漏极，未经过离子注入的金属氧化物半导体的区域为有源层；
剥离所述第一光阻层。
其中，所述步骤“在所述第二绝缘层上开设第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置”包括：
在所述第二绝缘层上覆盖第二光阻层；
图案化所述第二光阻层，以移除对应所述源极及所述漏极正上方的第二光阻层，以漏出部分第二绝缘层；
以图案化的第二光阻层为掩膜，蚀刻所述第二绝缘层，以在所述第二绝缘层上开设所述第一贯孔及所述第二贯孔；
剥离所述第二光阻层。
其中，所述像素电极与所述第一电极在同一工序中制备：
形成透明导电层，所述透明导电层覆盖所述第二绝缘层、所述源极及所述漏极；
图案化所述透明导电层，保留设置在所述源极上及所述漏极上的透明导电层，以及与设置在所述漏极上的透明导电层相连的透明导电层，其中，设置在所述源极上的透明导电层为所述第一电极，设置在所述漏极上的透明导电层为所述像素电极。
相较于现有技术，本发明的薄膜晶体管阵列基板的制备方法在第一绝缘层(栅极绝缘层)上形成金属氧化物半导体层，并对金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别形成源极和漏极，未经过离子注入的金属氧化物半导体层的区域为有源层。由此可见，所述源极和所述漏极的形成与所述有源层的形成可以在同一工序中制备，不需要额外增加所述源极和所述漏极制备时的阻挡层图案化的工序，从而节约了薄膜晶体管阵列基板的制备时间。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管阵列基板的剖面结构示意图。
图2为本发明一较佳实施方式的薄膜晶体管阵列基板的制备方法的流程图。
图3至图17为薄膜晶体管阵列基板的制备方法的各流程对应的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的薄膜晶体管阵列基板的剖面结构示意图。所述薄膜晶体管阵列基板100包括基板110、栅极120、第一绝缘层130、有源层140、源极150、漏极160、第二绝缘层170及像素电极190。所述基板110包括相对设置的第一表面110a及第二表面110b，所述栅极120设置在所述第一表面110a上，所述第一绝缘层130覆盖在所述栅极120上。所述有源层140设置在所述第一绝缘层130远离所述基板110的表面上。所述源极150和所述漏极160分别设置在所述第一绝缘层130上且分别设置于所述有源层140的相对的两端，并且所述源极150和所述漏极160分别与所述有源层140的端面接触。所述源极150及所述漏极160与所述有源层140位于同一层。所述第二绝缘层170覆盖所述有源层140、所述源极150及所述漏极160，所述第二绝缘层170上设置有用于裸露所述源极150或所述漏极160的贯孔。所述像素电极190设置在所述第二绝缘层170上，并通过所述贯孔与所述源极150或者所述漏极160连接。
具体地，所述第二绝缘层170上开设有第一贯孔171及第二贯孔172，所述第一贯孔171对应所述源极150设置，所述第二贯孔172对应所述漏极160设置。所述像素电极190通过所述第二贯孔172与所述漏极160连接。所述薄膜晶体管阵列基板100还包括第一电极180，所述第一电极180通过所述第一贯孔171与所述源极150连接。所述第一电极180用于改善所述源极150的导电性能。优选地，所述第一电极180与所述像素电极190在同一工序中制备。
所述基板110可以为玻璃基板，也可以为塑料基板或者是其他绝缘基板。
可以理解地，在本实施方式中所述薄膜晶体管阵列基板100除所述基板110以外的其他部件(即，所述栅极120、所述第一绝缘层130、所述有源层、所述源极150、所述漏极160、所述第二绝缘层170、所述第一电极180及所述像素电极190)直接或者间接设置在所述基板110的第一表面110a为例进行说明，在其他实施方式中，所述薄膜晶体管阵列基板100除所述基板110以外的其他部件也可以之间或间接设置在所述基板110的第二表面110b。
在其他实施方式中，所述薄膜晶体管阵列基板100还包括一缓冲层(图未示)，所述缓冲层设置在所述第一表面110a上。所述缓冲层用于缓冲在所述基板110上制作所述薄膜晶体管阵列基板100的其他结构的过程中受到的应力，以避免所述基板110的损坏或者破裂。此时，所述薄膜晶体管阵列基板100中的所述栅极120、所述第一绝缘层130、所述有源层140、所述源极150、所述漏极160、所述第二绝缘层170、所述第一电极180及所述像素电极190通过所述缓冲层直接或者间接设置在所述基板110的第一表面110a上。或者所述缓冲层设置在所述第二表面110b上，所述薄膜晶体管阵列基板100中的所述栅极120、所述第一绝缘层130、所述有源层140、所述源极150、所述漏极160、所述第二绝缘层170、所述第一电极180及所述像素电极190通过所述缓冲层直接或者间接设置在所述基板110的第二表面110b上。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
所述栅极120设置在所述第一表面110a上，所述栅极120的材质为金属或者为金属合金。在一实施方式中，所述栅极120的材质选自铜、钨、铬、铝及其组合的其中之一。
所述第一绝缘层130为栅极绝缘层，所述第一绝缘层130的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
所述第二绝缘层170的材质选自氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。可以理解地，所述第二绝缘层170与所述第一绝缘层130的材质可以相同也可以不同。
在本实施方式中，所述有源层140包括金属氧化物半导体，在一实施方式中，所述有源层140包括铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。优选地，所述源极150和所述漏极160包括经离子注入的金属氧化物半导体。所述源极150、所述漏极160及所述有源层140位于同一层。在一实施方式中，所述离子注入可以为氢离子注入。对金属氧化物半导体层进行离子注入可以使得进行离子注入的区域具有金属导电的特性。另外，因通过将金属氧化物半导体层进行离子注入而得到的所述源极150及所述漏极160导电性能均一性较差，因此，对应所述源极150形成第一电极180及对应所述漏极160形成像素电极190能够提升所述源极150及所述漏极160的导电性能。
下面结合图1及前述对薄膜晶体管阵列基板的相关描述对本发明的薄膜晶体管阵列基板的制备方法进行描述。请一并参阅图2，图2为本发明一较佳实施方式的薄膜晶体管阵列基板的制备方法的流程图。所述薄膜晶体管阵列基板的制备方法包括如下步骤。
步骤S110，提供基板110，所述基板110包括相对设置的第一表面110a及第二表面110b。请一并参阅图3，所述基板110可以为但不仅限于为玻璃基板、塑料基板或者是其他绝缘基板。
步骤S120，形成栅极120，所述栅极120设置在所述第一表面110a上。请参阅图4。所述栅极120可以通过如下步骤形成。首先，在所述基板110的第一表面110a上形成一整层的金属层，将一整层的金属层进行图案化以形成本实施方式中设置在所述第一表面110a上的栅极120。
步骤S130，形成第一绝缘层130，所述第一绝缘层130覆盖在所述栅极120上。请参阅图5。
步骤S140，在所述第一绝缘层130上形成金属氧化物半导体层210。请参阅图6。
步骤S150，对所述金属氧化物半导体层210的两端区域进行离子注入，经过离子注入的金属氧化物半导体层210的两端区域分别为源极150和漏极160，未经过离子注入的金属氧化物半导体层的区域为有源层140。对金属氧化物半导体层210进行离子注入可以使得进行离子注入的区域具有金属导电的特性。所述离子注入可以为氢离子注入。
具体地，所述步骤S150包括如下步骤。
步骤S151，在所述金属氧化物半导体层210上覆盖第一光阻层220。请参阅图7。
步骤S152，图案化所述第一光阻层220，以漏出所述金属氧化物半导体层210的两端区域。请参阅图8。
步骤S153，以图案化的所述第一光阻层210为掩膜对所述金属氧化物半导体层210进行离子注入(在图9中以箭头表示)，经过离子注入的金属氧化物半导体层210的两端区域分别为所述源极150和所述漏极160，未经过离子注入的金属氧化物半导体层的区域为有源层140。请参阅图9。
步骤S154，剥离所述第一光阻层220。请参阅图10。
步骤160，形成第二绝缘层170，所述第二绝缘层170覆盖所述源极150、所述漏极160及所述有源层140。请参阅图11。
步骤S170，在所述第二绝缘层170上开设用于裸露所述源极150或者所述漏极160的贯孔。
具体地，所述步骤S170包括：步骤S171，在所述第二绝缘层170上开设第一贯孔171及第二贯孔172，所述第一贯孔171对应所述源极150设置，所述第二贯孔172对应所述漏极160设置。
所述步骤S171具体包括如下步骤。
步骤S171a，在所述第二绝缘层170上覆盖第二光阻层230。请参阅图12。
步骤S171b，图案化所述第二光阻层230，以移除对应所述源极150和所述漏极160正上方的第二光阻层230，以漏出部分第二绝缘层170。请参阅图13。
步骤S171c，以图案化的第二光阻层230为掩膜蚀刻所述第二绝缘层170，以在所述第二绝缘层170上开设所述第一贯孔171及所述第二贯孔172。请参阅图14。
步骤S171d，剥离所述第二光阻层230。请参阅图15。
步骤S180，形成像素电极190，所述像素电极190设置在所述第二绝缘层170上，并通过所述贯孔与所述源极150或所述漏极160连接。
与所述步骤S171相应，所述步骤S180包括：步骤S181，形成像素电极190，所述像素电极190设置在所述第二绝缘层170上，且所述第二像素电极190通过所述第二贯孔172与所述漏极160连接。
相应地，所述薄膜晶体管阵列基板的制备方法还包括：
步骤S190，形成第一电极180，所述第一电极180通过所述第一贯孔171与所述源极150相连。
优选地，所述像素电极190和所述第一电极180在同一制备工序中制备。换句话说，所述步骤S180和所述步骤S190可以为同一制备工序。具体地，制备所述像素电极190及所述第一电极180包括如下步骤。
步骤a，形成透明导电层240，所述透明导电层240覆盖所述第二绝缘层170、所述源极150及所述漏极160。请参阅图16。所述透明导电材料可以包括铟镓锌氧化物、铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
步骤b，图案化所述透明导电层240，保留设置在所述源极150及所述漏极160上的透明导电层240，以及与设置在所述漏极160上的透明导电层相连的透明导电层，其中，设置在所述源极150上且与所述源极150相连的透明导电层240为所述第一电极180，与所述漏极160相连的透明导电层240为所述像素电极190。请参阅图17。
在其他实施方式中，所述薄膜晶体管阵列基板的制备方法还包括：形成缓冲层，所述缓冲层设置在所述基板110的第一表面110a上。所述缓冲层用于缓冲在所述基板110上制作所述薄膜晶体管阵列基板100的其他结构的过程中受到的应力，以避免所述基板110的损坏或者破裂。此时，所述薄膜晶体管阵列基板的制备方法中的所述栅极120、所述第一绝缘层130、所述有源层、所述源极150、所述漏极160、所述第二绝缘层170、所述第一电极180及所述像素电极190通过所述缓冲层直接或者间接制备在所述基板110的第一表面110a上。或者，所述缓冲层设置在所述第二表面110b上，所述薄膜晶体管阵列基板100中的所述栅极120、所述第一绝缘层130、所述有源层、所述源极150、所述漏极160、所述第二绝缘层170、所述第一电极180及所述像素电极190通过所述缓冲层直接或者间接设置在所述基板110的第二表面110b上。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
在本发明提供的实施例中，像素电极通过第二贯孔与漏极连接，第一电极通过第一贯孔与源极连接，但可以理解的是，像素电极也可以通过第一贯孔与源极连接，第一电极通过第二贯孔与漏极连接以改善漏极的导电性能，其结构和制作方法与本申请实施例类似，在此不再赘述。
相较于现有技术，本发明的薄膜晶体管阵列基板的制备方法在第一绝缘层130(栅极绝缘层)上形成金属氧化物半导体层210，并对金属氧化物半导体层210的两端区域进行离子注入，经过离子注入的金属氧化物半导体层210的两端区域分别形成源极150和漏极160，未经过离子注入的金属氧化物半导体层210的区域为有源层140。由此可见，所述源极150和所述漏极160的形成与所述有源层140的形成可以在同一工序中制备，不需要额外增加所述源极150和所述漏极160制备时的阻挡层图案化的工序，从而节约了薄膜晶体管阵列基板的制备时间。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (8)

1.一种薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板包括：
基板，所述基板包括相对设置的第一表面及第二表面；
栅极，设置在所述第一表面上；
第一绝缘层，覆盖在所述栅极上；
有源层，设置在所述第一绝缘层远离所述基板的表面上；
源极和漏极，所述源极和所述漏极分别设置在所述第一绝缘层上且分别设置于所述有源层的相对的两端，并且所述源极和所述漏极分别与所述有源层的端面接触；
第二绝缘层，所述第二绝缘层覆盖所述有源层、所述源极及所述漏极，所述第二绝缘层上设置有用于裸露所述源极或所述漏极的贯孔；
像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述漏极连接，其中，所述第二绝缘层上开设有第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置，所述像素电极通过所述第二贯孔与所述漏极连接；
所述薄膜晶体管阵列基板还包括第一电极，所述第一电极通过所述第一贯孔与所述源极相连，所述第一电极用于改善所述源极的导电性能。
2.如权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述第一电极与所述像素电极在同一工序中制备。
3.如权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述有源层包括金属氧化物半导体；所述源极和漏极包括经离子注入的金属氧化物半导体。
4.如权利要求2所述的薄膜晶体管阵列基板，其特征在于，所述有源层包括铟镓锌氧化物、铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
5.一种薄膜晶体管阵列基板的制备方法，其特征在于，所述薄膜晶体管阵列基板的制备方法包括：
提供基板，所述基板包括相对设置的第一表面及第二表面；
形成栅极，所述栅极设置在所述第一表面上；
形成第一绝缘层，所述第一绝缘层覆盖在所述栅极上；
在所述第一绝缘层上形成金属氧化物半导体层；
对所述金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为源极和漏极，未经过离子注入的金属氧化物半导体层的区域为有源层；
形成第二绝缘层，所述第二绝缘层覆盖所述源极、所述漏极及所述有源层；
在所述第二绝缘层上开设用于裸露所述源极或所述漏极的贯孔；
形成像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述漏极连接；
其中，“在所述第二绝缘层上开设用于裸露所述源极或所述漏极的贯孔”包括：
在所述第二绝缘层上开设第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置；
相应地，“形成像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接”包括：
形成像素电极，所述像素电极设置在所述第二绝缘层上，且所述像素电极通过所述第二贯孔与所述漏极连接；
所述薄膜晶体管阵列基板的制备方法还包括：
形成第一电极，所述第一电极通过所述第一贯孔与所述源极相连，所述第一电极用于改善所述源极的导电性能。
6.如权利要求5所述的薄膜晶体管阵列基板的制备方法，其特征在于，“对所述金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为源极和漏极，未经过离子注入的金属氧化物半导体层的区域形成有源层”包括：
在所述金属氧化物半导体层上覆盖第一光阻层；
图案化所述第一光阻层，以露出所述金属氧化物半导体层的两端区域；
以图案化的所述第一光阻层为掩膜对所述金属氧化物半导体层进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为所述源极和所述漏极，未经过离子注入的金属氧化物半导体的区域为有源层；
剥离所述第一光阻层。
7.如权利要求5所述的薄膜晶体管阵列基板的制备方法，其特征在于，“在所述第二绝缘层上开设第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置”包括：
在所述第二绝缘层上覆盖第二光阻层；
图案化所述第二光阻层，以移除对应所述源极及所述漏极正上方的第二光阻层，以漏出部分第二绝缘层；
以图案化的第二光阻层为掩膜，蚀刻所述第二绝缘层，以在所述第二绝缘层上开设所述第一贯孔及所述第二贯孔；
剥离所述第二光阻层。
8.如权利要求7所述的薄膜晶体管阵列基板的制备方法，其特征在于，所述像素电极与所述第一电极在同一工序中制备：
形成透明导电层，所述透明导电层覆盖所述第二绝缘层、所述源极及所述漏极；
图案化所述透明导电层，保留设置在所述源极上及所述漏极上的透明导电层，以及与设置在所述漏极上的透明导电层相连的透明导电层，其中，设置在所述源极上的透明导电层为所述第一电极，设置在所述漏极上的透明导电层为所述像素电极。
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