CN105140271B - 薄膜晶体管、薄膜晶体管的制造方法及显示装置 - Google Patents

薄膜晶体管、薄膜晶体管的制造方法及显示装置 Download PDF

Info

Publication number
CN105140271B
CN105140271B CN201510420701.5A CN201510420701A CN105140271B CN 105140271 B CN105140271 B CN 105140271B CN 201510420701 A CN201510420701 A CN 201510420701A CN 105140271 B CN105140271 B CN 105140271B
Authority
CN
China
Prior art keywords
layer
oxide
tft
thin film
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510420701.5A
Other languages
English (en)
Other versions
CN105140271A (zh
Inventor
李文辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201510420701.5A priority Critical patent/CN105140271B/zh
Priority to PCT/CN2015/085737 priority patent/WO2017008345A1/zh
Priority to US14/905,802 priority patent/US20170170330A1/en
Publication of CN105140271A publication Critical patent/CN105140271A/zh
Application granted granted Critical
Publication of CN105140271B publication Critical patent/CN105140271B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02565Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42Bombardment with radiation
    • H01L21/423Bombardment with radiation with high-energy radiation
    • H01L21/425Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/22Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
    • H01L29/227Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds further characterised by the doping material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供一种薄膜晶体管的制造方法,其包括在所述基板上形成第一金属层,通过构图工艺使第一金属层形成包括栅极的图案;在上述基板及第一金属层上形成栅极绝缘层,栅极绝缘层覆盖所述基板的表面及所述栅极;在所述栅极绝缘层上形成正投影于所述栅极的氧化物导体层;在形成栅极绝缘层的基板上形成第二金属层,图案化所述第二金属层,形成所述薄膜晶体管的源极及漏极,其中,所述源极和漏极均覆盖部分所述氧化物导体层;对未覆盖源极与漏极且位于源极与漏极之间的氧化物导体层进行等离子表面处理,使所述未覆盖源极与漏极的氧化物导体层形成第一氧化物沟道层;在所述基板及所述图案化的第二金属层上形成的绝缘保护层,对所述绝缘保护层进行图案化。

Description

薄膜晶体管、薄膜晶体管的制造方法及显示装置
技术领域
本发明涉及薄膜晶体管的制造领域,尤其涉及一种薄膜晶体管、薄膜晶体管的制造方法及显示装置。
背景技术
目前广泛应用的Oxide薄膜晶体管采用氧化物半导体作为有源层,具有迁移率大、开态电流高、开关特性更优、均匀性更好的特点,可以适用于需要快速响应和较大电流的应用,如高频、高分辨率、大尺寸的显示器以及有机发光显示器等。现有技术中薄膜晶体管包括栅线及栅极,半导体层,源漏极,钝化层及像素电极等。当在制造过程中采用惯用的电阻值低的金属材料构成的源漏电极层和氧化物半导体膜来直接接触的薄膜晶体管结构时,容易在源漏电极层和氧化物半导体膜的接触面形成肖特基结的现象,影响薄膜晶体管的导电性能。
发明内容
本发明提供一种薄膜晶体管的制造方法,避免在源漏电极层和氧化物半导体膜的接触面形成肖特基结的现象,保证薄膜晶体管性能。
本发明还提供一种薄膜晶体管及显示装置
本发明提供一种薄膜晶体管的制造方法,所述薄膜晶体管的制造方法包括:
提供一基板;
在所述基板上形成第一金属层,通过构图工艺使第一金属层形成包括栅极的图案;
在上述基板及第一金属层上形成栅极绝缘层,栅极绝缘层覆盖所述基板的表面及所述栅极;
在所述栅极绝缘层上形成正投影于所述栅极的氧化物导体层;其中,所述氧化物导体层采用物理气相沉积方式形成;
在形成栅极绝缘层的基板上形成第二金属层,图案化所述第二金属层,形成所述薄膜晶体管的源极及漏极,其中,所述源极和漏极均覆盖部分所述氧化物导体层;
对未覆盖源极与漏极且位于源极与漏极之间的氧化物导体层进行等离子表面处理,使所述未覆盖源极与漏极的氧化物导体层形成第一氧化物沟道层;
在所述基板及所述图案化的第二金属层上形成的绝缘保护层,对所述绝缘保护层进行图案化。
其中,所述等离子表面处理采用氩气与氧气混合体。
其中,所述氧化物导体层的材料为含氧量在0至20%之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。
其中,在步骤“在所述栅极绝缘层上形成正投影于所述栅极的氧化物导体层”之前,所述薄膜晶体管的制造方法还包括在所述栅极绝缘层上形成正投影于所述栅极的第二氧化物沟道层的步骤;其中,所述第二氧化物沟道层位于栅极与所述氧化物导体层之间,并且第二氧化物沟道层正投影于氧化物导体层。
其中,所述第二氧化物沟道层的材料为含氧量为4%-50%之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。
其中,所述的薄膜晶体管的制造方法还包括在所述基板及所述图案化的第二金属层上形成的绝缘保护层,对所述绝缘保护层进行图案化的步骤。
其中,所述栅极绝缘层与所述绝缘保护层采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
本发明提供一种薄膜晶体管,所述薄膜晶体管包括:
一栅极;
一栅绝缘层,覆盖所述栅极;
一氧化物层,覆盖于所述栅绝缘层上且位于所述栅极正上方,所述氧化物层包括一氧化物沟道层以及位于所述氧化物沟道层相对两侧的氧化物导体层;以及
一源极与一漏极,位于所述栅绝缘层与所述氧化物沟道层相对两侧的化物导体层上,且所述源极与所述漏极彼此电性绝缘。
本发明提供一种薄膜晶体管,所述薄膜晶体管包括:
一栅极;
一栅绝缘层,覆盖所述栅极;
一第二氧化物沟道层,覆盖于所述栅绝缘层上且位于所述栅极正上方;
一氧化物层,覆盖于所述第二氧化物沟道层正上方,所述氧化物层包括一第一氧化物沟道层以及位于所述第一氧化物沟道层相对两侧的氧化物导体层;以及
一源极与一漏极,位于所述栅绝缘层与所述第一氧化物沟道层相对两侧的氧化物导体层上,且所述源极与所述漏极彼此电性绝缘。
本发明提供一种显示装置,其包括以上所述的薄膜晶体管。
本发明本发明的薄膜晶体管的制造方法在栅极绝缘层上形成含氧量少的氧化物导体层与源极和漏极接触,保证源极和漏极与氧化物导体层良好电性接触,在通过等离子表面处理方式将未被覆盖的氧化物导体层位于所述源极和漏极之间的部分形成含氧量高的氧化物沟道层,即氧化物半导体层,实现晶体管的良好的导电性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的制造方法的流程图。
图2至图8为本发明较佳实施方式的薄膜晶体管方法的各个制造流程中薄膜晶体管的截面示意图。
图9为本发明另一较佳实施方式的薄膜晶体管的制造方法的流程图。
图10为图9所述的薄膜晶体管的制造方法的形成的薄膜晶体管截面示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
请参阅图1,其为本发明一较佳实施方式的薄膜晶体管的制造方法的流程图。所述薄膜晶体管属于氧化物半导体结构晶体管。在阐述具体制备方法之前,应所述理解,在本发明中,所述图案化即是指构图工艺,可包括光刻工艺,或,包括光刻工艺以及刻蚀步骤,同时还可以包括打印、喷墨等其他用于形成预定图形的工艺;光刻工艺,是指包括成膜、曝光、显影,等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
所述薄膜晶体管的制造方法制造方法包括如下步骤。
步骤S1,提供一基板10。请一并参阅图2,在本实施方式中,所述基板10为一玻璃基板。可以理解地,在其他实施方式中,所述基板10并不仅限于为玻璃基板。
请一并参阅图3,步骤S2,在所述基板10上形成第一金属层(图未示),通过构图工艺使第一金属12层形成包括栅极12的图案;具体的,在所述基板10的一表面上形成所述第一金属层,以作为所述薄膜晶体管10的栅极12。所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一。本实施方式中通过现有技术的涂光阻、曝光、显影等构图工艺对所述第一金属层图案化形成栅极12。
请一并参阅图4,步骤S3,在上述基板10及图案化的第一金属层上形成栅极绝缘层13,栅极绝缘层13覆盖所述基板10的表面及所述栅极。具体的在所述基板10未覆盖所述第一金属层的表面及所述栅极12上形成所述栅极绝缘层130。所述栅极绝缘层13的材质选择氧化硅、氮化硅层,氮氧化硅层及其组合的其中之一。
请一并参阅图5,步骤S4,在所述栅极绝缘层13上形成正投影于所述栅极12的氧化物导体层14;其中,所述氧化物导体层14采用物理气相沉积方式形成。本实施例中,所述氧化物导体层14的材料为含氧量在0至20%之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。优选的,所述所述氧化物导体层14采用含氧量0-%10的氧化铟镓锌(IGZO)。
请一并参阅图6,步骤S5,在成型栅极绝缘层13的基板上形成第二金属层(图未示),图案化所述第二金属层,形成所述薄膜晶体管的源极15及漏极16,其中,所述源极15和漏极16均覆盖部分所述氧化物导体层14。
具体的,所述第二金属层与所述氧化物导体层14及所述栅极绝缘层13依次层叠设置。通过现有技术的构图工艺对所述第二金属层进行图案化形成如图所示的源极15和漏极16。所述第二金属层的材质选自铜、钨、铬、铝及其组合的其中之一。
请一并参阅图7,步骤S6,对未覆盖源极15与漏极16且位于源极15与漏极16之间的氧化物导体层14进行等离子表面处理,使所述未覆盖源极15与漏极16的氧化物导体层14形成第一氧化物沟道层17。
其中,通过进行等离子表面处理后的所述氧化物导体层14用于形成所述薄膜晶体管的源极15和漏极16之间导通或者断开的通道。所述等离子表面处理是采用氩气与氧气混合体,目的是将位于源极15与漏极16之间的未覆盖源极15与漏极16的氧化物导体层14部分进行补氧修复,形成含氧量较高的氧化物半导体,即所述的第一氧化物沟道层17。本实施例中,所述第一氧化物沟道层17用于源极15和漏极16之间导通或者断开的通道。所述第一氧化物沟道层17两侧分别与所述源极15及漏极16接触的氧化物导体层14部分相当于欧姆接触层的作用,源极15和漏极16可分别通过位于其下的氧化物导体层14与第一氧化物沟道层17形成一良好的欧姆接触(ohmic contact),具有低阻止,实现源极15通过第一氧化物沟道层17到漏极16良好的通电性能。
本实施例中,第二金属层的材料一般是金属材料。但,本发明不限于此,在其他实施例中,第二金属层的材料也可以使用其他导电材料,如合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物或是金属材料与其它导材料的堆叠层。
请参阅图8,步骤S7,在所述基板10及所述图案化的第二金属层(源极15和漏极16)上形成的绝缘保护层19,对所述绝缘保护层19进行图案化。所述栅极绝缘层13与所述绝缘保护层19采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。到此步骤,本实施例中的薄膜晶体管制造方法完成。
进一步的,所述栅极绝缘层13与所述绝缘保护层19采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
本发明的薄膜晶体管的制造方法在栅极绝缘层13上形成含氧量少的氧化物导体层14与源极15和漏极16接触,保证源极15和漏极16与氧化物导体层14良好电性接触,在通过等离子表面处理方式将未被覆盖的氧化物导体层14位于所述源极15和漏极16之间的部分形成含氧量高的氧化物沟道层,即氧化物半导体层,实现晶体管的良好的导电性能。
针对上述薄膜晶体管制造方法,本发明还涉及一种薄膜晶体管,其包括一栅极,一栅绝缘层,覆盖所述栅极;一氧化物层,覆盖于所述栅绝缘层上且位于所述栅极正上方,所述氧化物层包括一氧化物沟道层以及位于所述氧化物沟道层相对两侧的化物导体层;以及一源极与一漏极,位于所述栅绝缘层与所述氧化物沟道层相对两侧的化物导体层上,且所述源极与所述漏极彼此电性绝缘。
请参阅图9,本发明的另一实施例中,与上述方法不同的在于,在步骤S3与步骤S4之间,所述薄膜晶体管的制造方法还包括在步骤S3A,所述栅极绝缘层13上形成正投影于所述栅极12的第二氧化物沟道层18的步骤;其中,所述第二氧化物沟道层18位于栅极12与所述氧化物导体层14之间,并且第二氧化物沟道层18正投影于氧化物导体层14。所述源极15及漏极16分别与所述第一氧化物沟道层17两侧的氧化物导体层14部分接触,所述所述第一氧化物沟道层17与第二氧化物沟道层18共同构成所述晶体管的沟道。
其中,所述第二氧化物沟道层18的材料为含氧量为4%-50%之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。本实施例中,优选的所述第二氧化物沟道层170的材料为含氧量为5%-200%之间的氧化铟镓锌(IGZO)制成。
请参阅图10,针对本实施方式的薄膜晶体管的制造方法本发明还提供一种薄膜晶体管,其包括一栅极,一栅绝缘层,覆盖所述栅极;一第二氧化物沟道层,覆盖于所述栅绝缘层上且位于所述栅极正上方;一氧化物层,覆盖于所述栅绝缘层上且位于所述栅极正上方,所述氧化物层包括一第一氧化物沟道层以及位于所述第一氧化物沟道层相对两侧的化物导体层;以及一源极与一漏极,位于所述栅绝缘层与所述第一氧化物沟道层相对两侧的氧化物导体层上,且所述源极与所述漏极彼此电性绝缘。
本发明还包括以上两个方式的薄膜晶体管的显示装置,通过本发明实施例薄膜晶体管的制造方法形成的显示装置,可以为:液晶面板、液晶电视、液晶显示器、OLED面板、OLED电视、电子纸、数码相框、手机等。
以上所揭露的仅为本发明较佳实施例而已,当然不能以此来限定本发明之权利范围,本领域普通技术人员可以理解实现上述实施例的全部或部分流程,并依本发明权利要求所作的等同变化,仍属于发明所涵盖的范围。

Claims (6)

1.一种薄膜晶体管的制造方法,其特征在于,所述薄膜晶体管的制造方法包括:
提供一基板;
在所述基板上形成第一金属层,通过构图工艺使第一金属层形成包括栅极的图案;
在上述基板及第一金属层上形成栅极绝缘层,栅极绝缘层覆盖所述基板的表面及所述栅极;
在所述栅极绝缘层上形成正投影于所述栅极的氧化物导体层;其中,所述氧化物导体层采用物理气相沉积方式形成,且所述氧化物导体层的材料为含氧量在0至20%之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO);
在形成栅极绝缘层的基板上形成第二金属层,图案化所述第二金属层,形成所述薄膜晶体管的源极及漏极,其中,所述源极和漏极均覆盖部分所述氧化物导体层;
对未覆盖源极与漏极且位于源极与漏极之间的氧化物导体层进行等离子表面处理,使所述未覆盖源极与漏极的氧化物导体层形成第一氧化物沟道层;
在所述基板及所述图案化的第二金属层上形成的绝缘保护层,对所述绝缘保护层进行图案化。
2.如权利要求1所述的薄膜晶体管的制造方法,其特征在于,所述等离子表面处理采用氩气与氧气混合体。
3.如权利要求1所述的薄膜晶体管的制造方法,其特征在于,在步骤“在所述栅极绝缘层上形成正投影于所述栅极的氧化物导体层”之前,所述薄膜晶体管的制造方法还包括在所述栅极绝缘层上形成正投影于所述栅极的第二氧化物沟道层的步骤;其中,所述第二氧化物沟道层位于栅极与所述氧化物导体层之间,并且第二氧化物沟道层正投影于氧化物导体层。
4.如权利要求3所述的薄膜晶体管的制造方法,其特征在于,所述第二氧化物沟道层的材料为含氧量为4%-50%之间的氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。
5.如权利要求1所述的薄膜晶体管的制造方法,其特征在于,所述的薄膜晶体管的制造方法还包括在所述基板及所述图案化的第二金属层上形成的绝缘保护层,对所述绝缘保护层进行图案化的步骤。
6.如权利要求5所述的薄膜晶体管的制造方法,其特征在于,所述栅极绝缘层与所述绝缘保护层采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
CN201510420701.5A 2015-07-16 2015-07-16 薄膜晶体管、薄膜晶体管的制造方法及显示装置 Active CN105140271B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201510420701.5A CN105140271B (zh) 2015-07-16 2015-07-16 薄膜晶体管、薄膜晶体管的制造方法及显示装置
PCT/CN2015/085737 WO2017008345A1 (zh) 2015-07-16 2015-07-31 薄膜晶体管、薄膜晶体管的制造方法及显示装置
US14/905,802 US20170170330A1 (en) 2015-07-16 2015-07-31 Thin film transistors (tfts), manufacturing methods of tfts, and display devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510420701.5A CN105140271B (zh) 2015-07-16 2015-07-16 薄膜晶体管、薄膜晶体管的制造方法及显示装置

Publications (2)

Publication Number Publication Date
CN105140271A CN105140271A (zh) 2015-12-09
CN105140271B true CN105140271B (zh) 2019-03-26

Family

ID=54725561

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510420701.5A Active CN105140271B (zh) 2015-07-16 2015-07-16 薄膜晶体管、薄膜晶体管的制造方法及显示装置

Country Status (3)

Country Link
US (1) US20170170330A1 (zh)
CN (1) CN105140271B (zh)
WO (1) WO2017008345A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105655257A (zh) * 2016-01-13 2016-06-08 深圳市华星光电技术有限公司 薄膜晶体管结构的制造方法
CN105489618B (zh) * 2016-01-22 2019-04-26 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法
CN106057679A (zh) * 2016-06-17 2016-10-26 深圳市华星光电技术有限公司 氧化物半导体薄膜晶体管的制作方法
CN106549063B (zh) * 2016-11-04 2019-07-05 上海禾馥电子有限公司 一种氧化物薄膜晶体管
CN107980174A (zh) * 2016-11-23 2018-05-01 深圳市柔宇科技有限公司 Tft阵列基板制作方法及tft阵列基板
CN109698204B (zh) * 2017-10-24 2021-09-07 元太科技工业股份有限公司 驱动基板及显示装置
TWI659254B (zh) 2017-10-24 2019-05-11 元太科技工業股份有限公司 驅動基板及顯示裝置
CN110098126A (zh) * 2019-05-22 2019-08-06 成都中电熊猫显示科技有限公司 一种薄膜晶体管的制作方法及薄膜晶体管和显示装置
CN114023768A (zh) * 2021-10-26 2022-02-08 惠州华星光电显示有限公司 阵列基板及其制备方法和显示面板
WO2023092554A1 (zh) * 2021-11-29 2023-06-01 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102891183A (zh) * 2012-10-25 2013-01-23 深圳市华星光电技术有限公司 薄膜晶体管及主动矩阵式平面显示装置
CN103545380A (zh) * 2013-09-23 2014-01-29 友达光电股份有限公司 薄膜晶体管及其制作方法
CN104637952A (zh) * 2013-11-07 2015-05-20 乐金显示有限公司 阵列基板及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4302347B2 (ja) * 2001-12-18 2009-07-22 シャープ株式会社 薄膜トランジスタ基板及びその製造方法
KR101093253B1 (ko) * 2004-09-02 2011-12-14 엘지디스플레이 주식회사 횡전계 방식 액정 표시 장치 및 그 제조 방법
JP5078246B2 (ja) * 2005-09-29 2012-11-21 株式会社半導体エネルギー研究所 半導体装置、及び半導体装置の作製方法
KR101345376B1 (ko) * 2007-05-29 2013-12-24 삼성전자주식회사 ZnO 계 박막 트랜지스터 및 그 제조방법
JP5325446B2 (ja) * 2008-04-16 2013-10-23 株式会社日立製作所 半導体装置及びその製造方法
US9082857B2 (en) * 2008-09-01 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an oxide semiconductor layer
KR101631454B1 (ko) * 2008-10-31 2016-06-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 논리회로
JP2010140919A (ja) * 2008-12-09 2010-06-24 Hitachi Ltd 酸化物半導体装置及びその製造方法並びにアクティブマトリクス基板
CN101533858A (zh) * 2009-04-03 2009-09-16 北京大学深圳研究生院 一种薄膜晶体管及其制作方法、图像显示装置
CN102403363A (zh) * 2011-10-27 2012-04-04 华南理工大学 双层氧化物薄膜晶体管及其制备方法
US9123691B2 (en) * 2012-01-19 2015-09-01 E Ink Holdings Inc. Thin-film transistor and method for manufacturing the same
CN104253158B (zh) * 2013-06-27 2017-10-27 鸿富锦精密工业(深圳)有限公司 薄膜晶体管及其制造方法
US20150001533A1 (en) * 2013-06-28 2015-01-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
TWI573226B (zh) * 2013-07-26 2017-03-01 鴻海精密工業股份有限公司 薄膜電晶體基板及其製作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102891183A (zh) * 2012-10-25 2013-01-23 深圳市华星光电技术有限公司 薄膜晶体管及主动矩阵式平面显示装置
CN103545380A (zh) * 2013-09-23 2014-01-29 友达光电股份有限公司 薄膜晶体管及其制作方法
CN104637952A (zh) * 2013-11-07 2015-05-20 乐金显示有限公司 阵列基板及其制造方法

Also Published As

Publication number Publication date
WO2017008345A1 (zh) 2017-01-19
CN105140271A (zh) 2015-12-09
US20170170330A1 (en) 2017-06-15

Similar Documents

Publication Publication Date Title
CN105140271B (zh) 薄膜晶体管、薄膜晶体管的制造方法及显示装置
US10748938B2 (en) Array substrate, method of manufacturing the same and display device
US10707236B2 (en) Array substrate, manufacturing method therefor and display device
CN104966698B (zh) 阵列基板、阵列基板的制造方法及显示装置
US9246007B2 (en) Oxide thin film transistor and method for manufacturing the same, array substrate, and display apparatus
US10622483B2 (en) Thin film transistor, array substrate and display device
US10204973B2 (en) Display device and thin-film transistors substrate
Yu et al. Amorphous InGaZnO thin-film transistors compatible with roll-to-roll fabrication at room temperature
JP2014131047A (ja) 薄膜トランジスタ、および薄膜トランジスタ表示板
CN103730510B (zh) 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN106935659B (zh) 薄膜晶体管及其制造方法、阵列基板以及显示装置
US20170162612A1 (en) Preparation Method of Oxide Thin-Film Transistor
US9704998B2 (en) Thin film transistor and method of manufacturing the same, display substrate, and display apparatus
CN109920856B (zh) 薄膜晶体管及其制造方法、阵列基板和显示装置
US20150311345A1 (en) Thin film transistor and method of fabricating the same, display substrate and display device
CN103956386A (zh) 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
US20190088784A1 (en) Thin film transistor, method for manufacturing the same, base substrate and display device
CN105428423B (zh) 薄膜晶体管及其制造方法
KR20150007000A (ko) 박막 트랜지스터 기판 및 박막 트랜지스터 기판의 제조 방법
CN113241351A (zh) 阵列基板及其制备方法、显示装置
CN104392928A (zh) 薄膜晶体管的制造方法
TW201324740A (zh) 半導體元件及其製造方法
US20220140114A1 (en) Method for manufacturing oxide semiconductor thin film transistor
TW201813000A (zh) 薄膜電晶體基板及其製備方法
CN109192668A (zh) 薄膜晶体管及其制造方法、显示面板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant