CN107980174A - Tft阵列基板制作方法及tft阵列基板 - Google Patents
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Abstract
一种TFT阵列基板及其制作方法，包括，在基板(10)上依次形成栅极(11)、绝缘层(12)及氧化物导体层(13)；其中氧化物层正投影于该栅极；在该氧化物导体层上依次形成蚀刻阻挡层(14)及第二金属层(15)；图案化该第二金属层形成沟道(151)；对与该沟道相对位置的氧化物导体层区域处理，形成半导体沟道。
Description
技术领域
本发明涉及触控面板制造技术领域，尤其涉及一种TFT阵列基板制作方法及TFT阵列基板。
背景技术
现有氧化物半导体TFT(Thin Film Transistor)器件，常采用具有刻蚀阻挡层(ESL)的结构，该刻蚀阻挡层可以保护半导体层，可以防止第二道金属蚀刻时损伤半导体。但是，具有刻蚀阻挡层结构的TFT，沟道长度偏大，造成TFT导电能力下降，从而需要设计较大尺寸的TFT，影响开口率。
发明内容
基于上述问题，本申请提供一种TFT阵列基板制作方法及TFT阵列基板，减小TFT阵列基板沟道长度，提高开口率。
本申请所述的TFT阵列基板制作方法包括，在基板上依次形成栅极、绝缘层及氧化物导体层；其中氧化物层正投影于所述栅极；
在所述氧化物导体层上依次形成蚀刻阻挡层及第二金属层；
图案化所述第二金属层形成沟道；
对与所述沟道相对位置的氧化物导体层区域处理，形成半导体沟道。
其中，所述对与所述沟道相对位置的氧化物导体层区域处理，形成半导体沟道是增加所述沟道相对位置的氧化物导体层区域含氧量，使沟道对应的氧化物导体层区域变成半导体而形成所述半导体沟道。
其中，所述增加所述沟道相对位置的氧化物导体层含氧量的方式包括：在高氧气环境下对沟道处高温烘烤。
其中，所述增加所述沟道相对位置的氧化物导体层含氧量的方式包括：以图案化的第二金属层为掩膜板对沟道进行等离子处理。
其中，所述等离子为O2或N2O。
其中，所述步骤在基板上依次形成栅极、绝缘层及氧化物导体层中，所述氧化物导体层通过低温溅镀形成。
其中，所述步骤在基板上依次形成栅极、绝缘层及氧化物导体层中，包括溅镀形成氧化物半导体基层薄膜，对氧化物半导体基层薄膜高温烘烤的步骤。
其中，所述对氧化物半导体基层薄膜高温烘烤的步骤为真空烘烤，或在N2环境下烘烤。
其中，步骤在所述氧化物导体层上形成蚀刻阻挡中，包括在所述氧化物导体层及绝缘层上形成阻挡层材料层，对阻挡材料层图案化形成蚀刻阻挡层的步骤。
本申请所述的TFT阵列基板包括基板、依次形成于基板表面的栅极、栅极绝缘层、氧化物层、蚀刻阻挡层及具有图形的第二金属层；所述第二金属层上形成有沟道；所述氧化物层包括与所述沟道相对位置的半导体区域及位于所述半导体区域两侧的氧化物导体区域，所述沟道与半导体区域形成半导体沟道。
本申请所述的TFT阵列基板制造方法中，以第二道金属电极作掩模，先定义沟道长度，在根据沟道处理氧化物导体层形成半导体沟道，进而减小TFT沟道长度，提高开口率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例的TFT阵列基板制作方法的流程图。
图2至图5是本申请TFT阵列基板制作方法的各个步骤截面示意图。
图6是图1所示的TFT阵列基板制作方法形成的TFT阵列基板截面示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述。
本申请实施例涉及的TFT阵列基板制作方法可以为但不限于手机、电脑、显示器或电子阅读器等液晶显示器中，本申请实施例对此不作具体限定。
请参阅图1与图2，本发明提供一种TFT阵列基板制作方法，包括，
步骤S1，在基板10上依次形成栅极11、绝缘层12及氧化物导体层13；其中氧化物导体层13正投影于所述栅极11。
其中，氧化物导体层13形成方式为：通过低温溅镀形成，即在低氧气环境下，溅镀成膜，氧化物半导体基层薄膜氧含量降低，氧空缺较多，偏向导体特性，进而形成氧化物导体层13。
或者是，通过步骤溅镀形成氧化物半导体基层薄膜13，及步骤对氧化物半导体基层薄膜高温烘烤形成。所述对氧化物导体层高温烘烤的步骤为真空烘烤，或在N2环境下烘烤。即，在常规溅镀成氧化物半导体基层薄膜，然后在低氧环境下高温烘烤，如真空烘烤，或N2气氛下烘烤，氧化物半导体基层薄膜氧含量降低，氧空缺较多，偏向导体特性，进而形成氧化物导体层13。当然，也不限于本申请列举的上述两种方式，还可以包含其它可以形成氧化物导体层的实施方式。
请参阅图3与图4，步骤S2，在所述氧化物导体层13上依次形成蚀刻阻挡层14及第二金属层15。本步骤中，包括步骤：在所述氧化物导体层13及绝缘层12上形成阻挡层材料层，以及步骤：对阻挡材料层图案化形成蚀刻阻挡层14。
步骤S3，图案化所述第二金属层15形成沟道151。其中，在所述蚀刻阻挡层14上形成第二金属层(图未示)，通过显影、曝光、蚀刻等工艺形成图案化所述第二金属层15，在此过程中，图案化的第二金属层15上设有光阻层。该光阻层可以在下一个步骤进行后去除，也可以在此步骤完成后去除。本实施例中，图案化所述第二金属层15主要为形成源极线及漏极线。该光阻层可在下一个步骤(步骤S4)进行后去除，这样可以起到保护图案化的第二金属层15的作用。
请参阅图5，步骤S4，对与所述沟道151相对位置的氧化物导体层区域处理，形成半导体沟道16。最后剥离所述光阻层(图未示)。
本申请中，所述对与所述沟道151相对位置的氧化物导体层区域处理，形成半导体沟道层是增加所述沟道151相对位置的氧化物导体层区域含氧量，以使部分氧穿透所述蚀刻阻挡层与氧化物导体层结合，所述沟道对应的氧化物导体层区域变成半导体金而形成所述半导体沟道16。主要原理是，对沟道进行处理，使沟道处氧化物层含氧量增加，氧空缺减少，可移动电子减少，使氧化物导体呈半导体特性。具体处理方法一种是：
以图案化的第二金属,15为掩膜板对沟道151进行等离子处理。所述等离子为O2或N2O。即在刻蚀阻挡层14较薄(可以根据设计形成)的情况下，等离子可以渗透穿过刻蚀阻挡层，与氧化物导体层的氧化物结合，减少氧空缺，减少可移动电子，形成半导体，进而形成半导体沟道。
另一种是：在高氧气环境下对沟道151处高温烘烤。也就是说在高氧氛围下高温烘烤，部分氧可以渗透穿过刻蚀阻挡层14，与氧化物结合，减少氧空缺，减少可移动电子，形成半导体沟道16。本申请所述的高温或者低温均是指本领域内常用的高温或低温数据。
本申请所述的TFT阵列基板制造方法中，在栅极绝缘层后，制作氧化物导体层，然后制作第二道金属，以第二道金属电极作掩模，定义沟道长度，在根据沟道星创处理氧化物导体层形成半导体沟道，进而减小TFT沟道长度，提高TFT导电能力，从而可以设计较小尺寸的TFT，提高开口率。
参阅图5，本申请还提供一种TFT阵列基板，其包括基板10、依次形成于基板10表面的栅极11、栅极绝缘层12、氧化物层13、蚀刻阻挡层14及第二金属层15；所述第二金属层15上形成有沟道151；所述氧化物层13包括与所述沟道151相对位置的半导体区域及位于所述半导体区域两侧的氧化物导体区域131，所述沟道与半导体区域形成半导体沟道16。
以上所述是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。
Claims (10)
1.一种TFT阵列基板制作方法，其特征在于，包括，在基板上依次形成栅极、绝缘层及氧化物导体层；
在所述氧化物导体层上依次形成蚀刻阻挡层及第二金属层；
图案化所述第二金属层形成沟道；
对与所述沟道相对位置的氧化物导体层区域处理，形成半导体沟道。
2.如权利要求1所述的TFT阵列基板制作方法，其特征在于，所述对与所述沟道相对位置的氧化物导体层区域处理，形成半导体沟道是增加所述沟道相对位置的氧化物导体层区域含氧量，以使部分氧穿透所述蚀刻阻挡层与氧化物导体层结合，所述沟道对应的氧化物导体层区域变成半导体而形成所述半导体沟道。
3.如权利要求2所述的TFT阵列基板制作方法，其特征在于，所述增加所述沟道相对位置的氧化物导体层含氧量的方式包括：在高氧气环境下对沟道处高温烘烤。
4.如权利要求2所述的TFT阵列基板制作方法，其特征在于，所述增加所述沟道相对位置的氧化物导体层含氧量的方式包括：以图案化的第二金属层为掩膜板对沟道进行等离子处理。
5.如权利要求4所述的TFT阵列基板制作方法，其特征在于，所述等离子为O2或N2O。
6.如权利要求1所述的TFT阵列基板制作方法，其特征在于，所述步骤在基板上依次形成栅极、绝缘层及氧化物导体层中，所述氧化物导体层通过低温溅镀形成。
7.如权利要求1所述的TFT阵列基板制作方法，其特征在于，所述步骤在基板上依次形成栅极、绝缘层及氧化物导体层中，包括溅镀形成氧化物半导体基层薄膜，对氧化物半导体基层薄膜高温烘烤的步骤。
8.如权利要求7所述的TFT阵列基板制作方法，其特征在于，所述对氧化物半导体基层薄膜高温烘烤的步骤为真空烘烤，或在N2环境下烘烤。
9.如权利要求1所述的TFT阵列基板制作方法，其特征在于，步骤在所述氧化物导体层上形成蚀刻阻挡中，包括在所述氧化物导体层及绝缘层上形成阻挡层材料层，对阻挡材料层图案化形成蚀刻阻挡层的步骤。
10.一种TFT阵列基板，其特征在于，包括基板、依次形成于基板表面的栅极、栅极绝缘层、氧化物层、蚀刻阻挡层及具有图形的第二金属层；所述第二金属层上形成有沟道；所述氧化物层包括与所述沟道相对位置的半导体区域及位于所述半导体区域两侧的氧化物导体区域，所述沟道与半导体区域形成半导体沟道。
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