CN105047714B - 垂直半导体器件 - Google Patents
垂直半导体器件 Download PDFInfo
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- CN105047714B CN105047714B CN201510178778.6A CN201510178778A CN105047714B CN 105047714 B CN105047714 B CN 105047714B CN 201510178778 A CN201510178778 A CN 201510178778A CN 105047714 B CN105047714 B CN 105047714B
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Abstract
一种垂直半导体器件,包括半导体主体,其包括第一表面、相对于第一表面的第二表面、以及在基本上垂直于第一表面的垂直方向上延伸的边缘、有源区域、在有源区域和边缘之间在基本平行于第一表面的水平方向上布置的***区域,以及与第一表面相邻地布置并从有源区域延伸至***区域的pn结。在***区域中,半导体器件还包括布置与第一表面相邻的第一导电区域,与第一表面相邻地布置并在水平方向上布置在第一导电区域和边缘之间的第二导电区域、以及钝化结构,其在垂直截面中包括至少部分地覆盖第一导电区域的第一部分,至少部分地覆盖第二导电区域的第二部分。第一部分具有与第二部分不同的层组成和/或不同于第二部分的第二厚度的第一厚度。
Description
技术领域
本发明的实施例涉及垂直半导体器件,具体涉及具有有源区域和***区域的垂直功率半导体器件,该***区域具有边缘端接结构并且包围有源区域。
背景技术
半导体晶体管(特别是诸如金属氧化物半导体场效应晶体管(MOSFET)或绝缘栅双极晶体管(IGBT)之类的场效应可控开关器件)已被用于各种应用,其包括但不限于作为电源和功率变换器、电动汽车、空调以及甚至音响***中的开关的用途。特别地,对于能够开关大电流和/或在较高电压下操作的功率器件而言,通常期望低导通状态电阻Ron,高击穿电压Ubd,和/或高稳健性。
诸如,HVMOS功率晶体管、功率二极管和功率IGBT之类的功率半导体器件的电学特性(特别是它们的阻断能力(击穿电压Ubd))在操作期间可能变化。这种不利的情况可能是由于从封装或从外部穿透进入半导体器件的移动电荷(离子、带电分子)和/或由于金属电极的腐蚀所致。电荷可以在能量上最有利的位置累积,该位置例如在边缘端接中,其中,电荷大规模地改变电场分布。对于产品研发而言,存在标准化的稳健性测试,特别是HTRB(高温反向偏置),H3TRB(高温高温反向偏置)和HTS(高温存储)测试。在这些测试中,许多功率部件在抵抗外部电荷的稳健性与抵抗湿度相关的腐蚀的稳健性之间示出不足的权衡。因此,存在一种需要,以改进功率半导体器件。
发明内容
根据垂直半导体器件的实施例,垂直半导体器件包括半导体主体,其包括第一表面、相对于第一表面的第二表面、以及在基本上垂直于第一表面的垂直方向上延伸的边缘、有源区域、在有源区域和边缘之间在基本平行于的第一表面的水平方向上布置的***区域,以及与第一表面相邻并从有源区域延伸至***区域地布置的pn结。在***区域中,半导体器件还包括与第一表面相邻布置的第一导电区域、与第一表面相邻地布置并且在第一导电区域和边缘之间在水平方向上布置的第二导电区域,以及在垂直截面中包括至少部分地覆盖第一导电区域的第一部分和至少部分地覆盖第二导电区域的第二部分的钝化结构。第一部分具有与第二部分不同的层组成和/或与第二部分的第二厚度不同的第一厚度。
根据垂直半导体器件的一个实施例,垂直半导体器件包括半导体主体,其包括第一表面、相对于第一表面的第二表面、以及在基本上垂直于第一表面的垂直方向上延伸的边缘、有源区域、在有源区域和边缘之间在基本平行于第一表面的水平方向上布置的***区域、以及与第一表面相邻地布置并从有源区域延伸至***区域的pn结、在第一表面上布置并且与第二半导体区域欧姆接触的第一金属化结构、以及在第二表面上布置的第二金属化结构,该pn结形成于半导体主体的第一半导体区域和第二半导体区域之间。在***区域中,半导体器件还包括布置在第一表面上的至少一个场板、以及至少部分地覆盖场板并且在至少一个场板的表面处具有变化的厚度的钝化结构。
根据用于形成垂直半导体器件的方法的一个实施例,本方法包括,提供垂直半导体器件包括半导体主体,其包括第一表面、相对于第一表面的第二表面,有源区域、包围有源区域的***区域、与第一表面相邻布置并从有源区域延伸至***区域的pn结,在第一表面上形成第一介电层,在***区域中在第一介电层上形成场板,将第一钝化层沉积在场板上,以及至少在场板的部分处至少减小第一钝化层的厚度。
在阅读下面具体的说明书以及查看附图之后,本领域的技术人员将意识到附加的特征以及优点。
附图说明
附图中的部件并不必然成比例,而是被用于强调示出本发明的原理。另外,在附图中,相同的参考标记指定对应的部分。在附图中:
图1示出根据一个实施例的半导体器件的半导体主体的垂直截面;
图2示出根据一个实施例的垂直半导体器件的半导体主体的垂直截面;
图3示出根据一个实施例的垂直半导体器件的半导体主体的垂直截面;
图4示出根据一个实施例的垂直半导体器件的半导体主体的垂直截面;
图5示出根据一个实施例的垂直半导体器件的半导体主体的垂直截面;
图6示出根据一个实施例的垂直半导体器件的半导体主体的垂直截面;
图7示出根据一个实施例的垂直半导体器件的半导体主体的垂直截面;
图8示出根据一个实施例的垂直半导体器件的半导体主体的垂直截面;
图9至图12示出在根据一些实施例的方法的方法步骤期间半导体主体的垂直截面。
具体实施方式
下面的详细描述中,参考形成说明书的一部分的附图,并且将本发明可实践的具体实施方式以说明的方式示出。在这方面,参考所描述的附图的方位,使用方向性的术语,如“顶部”、“底部”、“前面”、“后面”、“靠前”、“靠后”等。由于可以将实施例中的部件在多个不同定向上进行定位,因此,使用的方向性术语仅用于说明性目的而非限定性目的。应该可以理解,可以使用其它实施例,并且可以做出结构性或逻辑性的改变而不偏离本发明范围。本文下述具体的实施方式不应理解为限定性的,并且本发明的范围由所附权利要求书所限定。
现将具体地参考各种实施例,在附图中示出实施例的一个或多个示例。每个示例通过阐述的方式被提供,并且并不旨为本发明的限定。例如,作为一个实施例的部分而示出的或描述的特征可以被用于其它实施例上,或与其它实施例结合产生另外的实施例。本发明旨在包括这种修改与改变。使用特定语言描述的示例不应理解为对随附的权利要求书的范围的限定。为清楚起见,如果没有特定地指出,相同的元件或制造步骤在不同的附图中由相同的参考标记指出。
如在本说明书中使用的术语“水平”旨在描述基本上平行于半导体衬底或主体的第一或主水平面。例如,这可以是晶片或裸片。
如在本说明书中使用的术语“垂直”旨在描述基本上被垂直于第一表面布置的定向,即,平行于半导体衬底或主体的第一表面的法线方向。同样,如在本说明中被使用的术语“水平”旨在描述基本上平行于第一表面布置的定向。
在本说明书中,半导体主体的半导体衬底的第二表面被看作由下端表面或背面表面形成,而第一表面被看作由半导体衬底的上端、正面或主表面形成。因此,在本说明书中使用的术语“之上”和“之下”描述了参考该定向的一个结构性特征与另一个结构性特征的相对位置。
在本说明书中,n掺杂指第一导电类型,而p掺杂指第二导电类型。备选地,可使用相反的掺杂关系形成半导体器件,使得第一导电类型可以是p掺杂,并且第二导电类型可以是n掺杂。此外,一些图中通过在掺杂类型旁边指出“+”或“-”来示出相对的掺杂浓度。例如,“n-”表示低于“n”掺杂区域的掺杂浓度的掺杂浓度,而”“n+”掺杂区域具有高于“n”掺杂区域的掺杂浓度的掺杂浓度。然而,除非特别指出,指出相对的掺杂浓度并不表示相同的相对掺杂浓度的掺杂区域必须具有相同的绝对的掺杂浓度。例如,两个不同的n+掺杂区域可以具有不同的绝对掺杂浓度。同样适用于,例如,n+掺杂区域和p+掺杂区域。
本说明书中描述的特定实施例涉及但不限于场效应半导体器件,特别地涉及场效应补偿半导体器件及其制造方法。在本说明书范围内,术语“半导体器件”和“半导体部件”可以被同义地使用。场效应半导体器件通常是诸如垂直MOSFET之类的垂直半导体器件,其具有布置在第一表面上的绝缘的栅极电极和源极金属化结构,以及布置在相对于第一表面布置的第二表面上的漏极金属化结构。通常,场效应半导体器件是功率半导体器件,其具有包含用于承载和/或控制负载电流的多个MOSFET单元的有源区域。此外,功率半导体器件通常具有***区域,当从上面观察时,其具有至少部分地包围有源区域的至少一个边缘端接结构。
如本说明书中使用的术语“功率半导体器件”旨在描述具有高电压和/或高电流开关能力的单个芯片上的半导体器件。换言之,功率半导体器件旨在用于高电流(通常在安培范围)和/或高于大约10V或甚至高于大约100V或500V的电压。在本说明书内,术语“功率半导体器件”和“功率半导体部件”可以被同义地使用。
如本说明书中使用的术语“边缘端接结构”旨在描述一种提供过渡区域的结构,在过渡区域中,围绕半导体器件有源区域的高电场逐渐改变至处于或邻近器件边缘电位,和/或在诸如接地之类的参考电位与例如处于半导体器件边缘和/或背面的高电压之间。例如,边缘端接结构可以通过将电场线扩展经过终止区域来降低在换向结的终止区域周围的电场强度。
如本说明书中使用的术语“场效应”旨在描述第一导电类型的导电“沟道”的电场调节形式和/或第二导电类型的半导体区域中的沟道形状,通常是第二导电类型的主体区域。由于场效应,形成穿过沟道区域的单极电流路径,和/或该单极电流路径在第一导电类型的源极区域和第一导电类型的漂移区域被控制。漂移区域可以与漏极区域接触。漂移区域和漏极区域与漏极电极(漏极金属化)低欧姆接触。源极区域与源极电极(源极金属化)低欧姆接触。在本说明书的上下文中,术语“欧姆接触”旨在描述,当没有电压或仅很小的探测电压被施加到和/或跨接到半导体器件时,在半导体器件的各个元件或部分之间存在低欧姆的欧姆电流路径。在本说明书中,术语“欧姆接触”,“电阻性电接触”,“电耦合”以及“电阻性电连接”被同义地使用。
在本说明书的上下文中,术语“MOS”(金属氧化物半导体)应被理解为包括更一般性的术语“MIS”(金属绝缘体半导体)。例如,输入MOSFET(金属氧化物半导体场效应晶体管)应被理解为包括具有非氧化物的栅极绝缘体的FET,即,术语MOSFET可分别被用于更一般性的IGFET(隔离栅场效应晶体管)和MISFET(金属绝缘半导体场效应晶体管)的术语含义。用于MOSFET栅极材料的术语“金属”应被理解为包括或包含导电材料,如金属、合金、掺杂多晶半导体,以及如金属硅化物的金属半导体化合物。
在本说明书的上下文中,术语“栅极电极”旨在描述位于主体区域旁边且与其绝缘的电极,该栅极电极被配置为形成和/或控制穿过主体区域的沟道区域。
在本说明书的上下文中,术语“场电极”旨在描述与半导体区域(通常是漂移区域)相邻、与半导体区域部分地绝缘的电极,并且该场电极被配置为通过充电至适当的电压来扩展半导体区域中的耗尽区域,该适当的电压相对于n型半导体区域的周围半导体区域通常为负电压。
在本说明书的上下文中,术语“台面(mesa)”或“台面区域”旨在描述在延伸至垂直截面中的半导体衬底或主体的两个相邻的沟槽(trench)之间的半导体区域。
如本说明书中使用的术语“换向”旨在描述将半导体器件的电流从导通方向的切换,其中,例如,pn负载结,例如在MOSFET的主体区域和漂移区域之间的pn结被正向地偏置到相反方向或pn负载结被反向偏置的阻断方向。如本说明书中使用的术语“硬换向”旨在描述以至少大约109V/s的速率换向,更通常地,以至少大约5*109V/s的速率换向。
在下文中,主要参考硅(Si)半导体器件,对涉及半导体器件的实施例以及用于形成半导体器件的制造方法进行阐述。相应地,单晶半导体区域或层通常为单晶Si区域或Si层。然而,应该理解,半导体主体可以是任意适合制造半导体器件的半导体材料。这种材料的示例包括但不限于:例如,基础半导体材料,诸如硅(Si)或锗(Ge);IV族化合物半导体材料,诸如碳化硅(SiC)或锗化硅(SiGe);二元、三元或四元III-V族半导体材料,诸如氮化镓(GaN)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、磷化铟镓(InGaP)、氮化铝镓(AlGaN)、铝氮化铟(AlInN)、铟镓氮(InGaN)、铝镓氮化铟(AlGaInN)或砷化铟镓磷化物(InGaAsP);以及二元或三元的II-VI族半导体材料,诸如碲化镉(CdTe)和碲化汞镉(HgCdTe)。上述半导体材料也称作同质结的半导体材料。当将两个不同半导体材料组合时,形成异质结半导体。异质结半导体的示例包括但不限于:氮化铝镓(AlGaN)-铝镓铟氮化物(AlGaInN)、铟镓氮(InGaN)-铝镓铟氮化物(AlGaN)、铟镓氮(InGaN)-氮化镓(GaN)、氮化铝镓(AlGaN)-氮化镓(GaN)、铟镓氮(InGaN)-氮化铝镓(AlGaN)、硅-碳化硅(SixC1-x)和硅-SiGe异质结的半导体材料。对于功率半导体的应用而言,当前主要使用Si、SiC、GaAs和GaN材料。如果半导体主体包括高带隙材料,诸如SiC或GaN,其分别具有高击穿电场强度和高临界雪崩电场强度,则可选择较高的相应半导体区域的掺杂,其降低了在下面也称导通电阻Ron的导通状态电阻Ron。
参考图1说明半导体器件100的第一实施例。图1示出半导体器件100的半导体主体40的垂直截面。半导体主体40在面向垂直方向上的第一表面101和相对于第一表面101布置的第二表面102之间延伸。在基本上平行于第一表面101的水平方向上,半导体主体40由边缘41(例如锯齿边缘)界定,半导体主体在第一表面101和第二表面102之间延伸。半导体主体40具有有源区域110和布置于有源区域和边缘41之间的***区域120。通常,当从上方观察时,***区域120包围有源区域110。
通常形成源极金属化结构10的第一金属化结构被布置在第一表面101上面。通常形成漏极金属化结构11的第二金属化结构被布置在第二表面102上面,即,相对于源极金属化结构10。此外,多个栅极电极12可以被布置在有源区域110中的第一表面101上,并且与源极金属化结构10和半导体主体40通过相应栅极介电区域5绝缘。栅极电极12与未在图1中示出的栅极金属化连接,栅极金属化通常同样被布置在第一表面101上。相应地,半导体器件100可以作为3端子器件(晶体管)操作。为清楚起见,图1中示出了有效区域110的多个晶体管单元(单位单元)中的仅几个晶体管单元。
半导体主体40通常包括块状单晶材料3和形成在其上的至少一个外延层1。由于可以在外延层或多个层的沉积期间对掺杂浓度进行调整,因此利用该外延层1提供定制材料的背景掺杂的更多自由度。
备选地,具有对应于漂移区域掺杂的起始电阻率的厚晶片可以被用于器件的制造,其中,通过在晶片正面上的器件结构实现之后的薄化工艺来调节器件的最终厚度。例如,通过离子注入以及随后的激光退火工艺可以在薄化工艺之后实现晶片背面的高掺杂层。
pn结14形成于通常形成漂移区域的半导体主体40的n型第一半导体区域1和n型第二半导体区域2之间。pn结14被布置为第一表面101相邻,从有源区域110延伸至***区域120,并且在第一金属化结构10和第二金属化结构11之间形成整流结。
在示例性实施例中,在有源区域110和***区域120中,第二半导体区域2延伸至第一表面101。第二半导体区域2的最内侧部分可以形成最外侧晶体管单元的主体区域。
在参考了场效应半导体器件的实施例中,有源区域110可以通过绝缘栅极电极5、12的存在而被定义,绝缘栅极电极5、12被配置为在相邻的p型主体区域2a中在与源极金属化结构10欧姆接触的邻接的n型源极区域(未在图1中示出)和漂移区域1(第一半导体区域1)之间形成和/或改变沟道区域。然而,掺杂关系也可相反。有源区域110也可以通过诸如二极管单元、MOSFET单元和IGBT单元之类的有源单元的存在而被定义,用于在源极金属化结构10和漏极金属化结构11之间承载负载电流。
如图1所示,有源区域110的主体区域2a和第二半导体区域2可以经由相应导电插塞10a连接至源极金属化结构10。
在图1中示出的示例性实施例中,有源区域110的晶体管单元被作为具有布置在第一表面101上的相应栅极电极12的n沟道DMOS结构被实现。
根据另一实施例,栅极电极12和栅极介电材料5形成于从第一表面101延伸至半导体主体40的相应沟槽中。在该实施例中,主体区域2a和源极区域与相应沟槽的上面部分邻接,而漂移区域1与相应沟槽的下面部分邻接。在该实施例中,漂移区域1可以不延伸至有源区域110中的第一表面101。
在图1所示的示例性实施例中,半导体主体40可以包括延伸至第二表面102并且与漏极金属化结构11欧姆接触的高掺杂的n型漏极区域3。
额外地,n型场截止(field-stop)区域(未在图1中示出)可以被布置在漏极区域3和漂移区域1之间。漏极区域3,可选的场截止区域3和漂移区域1(第一半导体区域1)通常被布置在有源区域110和***区域120中,并且可以延伸至边界41。
在参考二极管的实施例中,半导体主体40可以包括被布置在有源区域110中并且与阳极金属化结构10欧姆接触的多个p型阳极区域2a,以及延伸至第二表面102并且与阴极金属化结构11欧姆接触的高掺杂n型阴极区域3。
在参考IGBTs的实施例中,半导体主体40包括高掺杂p型集电极区域3,而不是n型的漏极区域。在这些实施例中,第一金属化结构10与第二金属化结构11分别形成发射极金属化结构10和集电极金属化结构11。
在参考具有集成续流二极管的IGBT的实施例中,半导体主体40包括在第二表面102具有一个或多个p型集电极部分的高掺杂层3,以及与形成公用的集电极-阳极金属化结构11的第二金属化结构11欧姆接触的一个或多个n型阴极区域。
第二金属化结构11通常被布置在有源区域110和***区域120中。第二金属化结构11甚至可以分别完全覆盖第二表面102并且延伸至边缘41。
在图1中所示的示例性实施例中,半导体器件100在***区域120中包括两个第一导电区域20、21以及第二导电区域22,第二导电区域22被布置在第一表面101上并且与半导体主体40通过被布置在第一表面101上的第一介电层5分开,并且被实现为场板。相应地,提供给半导体器件10边缘端接结构,以确保足够高的击穿电压。例如,与边缘41最靠近布置的第二导电区域22可以例如经由半导体主体40与第二金属化结构11(漏极金属化结构)欧姆接触,而最内的第一导电区域20可以与栅极金属化结构(未在图1中示出)和多晶硅栅极接触层16欧姆接触,并且导电区域21可以是浮置的。
第一介电层5通常是氧化硅层,例如,热氧化层。
通常,第一和第二导电区域20、21、22由相同的材料制成,和/或可以具有分别与源极金属化结构10和栅极金属化结构11相同的组成。
当从上方观察时,第一和第二导电区域20、21、22通常围绕有源区域110。
第一和第二导电区域20、21、22可以基本上为环形(ring-shaped)的,例如,当从上方观察时为环状(annular)。在这些实施例中,第一和第二导电区域20、21、22基于接触可以分别形成栅极环20、浮置环21以及漏极环22。
源极金属化结构10的最外侧部分10可以形成源极场板。半导体器件100基于设计也可以包括分离的源极环。
根据一个实施例,钝化结构6、7具有覆盖第一导电区域20、21的第一部分(内侧部分)和覆盖第二导电区域22的第二部分(外侧部分)。
在示例性实施例中,第一部分具有大于第二部分的第二厚度的第一厚度。
第一和第二部分可以共用至少一个钝化层7,即,包括连续的钝化层7的相应部分。
钝化结构6、7的第一和第二部分的厚度通常在导电区域20、21、22的邻接表面(层厚度)的法线方向被测量,并且如果没有明确指明,则该厚度可以指最小厚度、最大厚度或平均厚度。当对覆盖不同的第一和第二导电区域20、21、22的钝化结构6、7的厚度进行比较时,使用相同的定义。
通常地,钝化结构6、7的第一和第二部分(钝化结构6、7的内侧和外侧部分)的厚度相差至少50%,更通常地,相差至少大约5倍,甚至更通常地,相差至少大约10倍。例如,钝化结构6、7的第二部分的厚度可以低于大约100nm,例如在5nm至15nm或20nm的范围内,并且钝化结构6、7的第一部分的厚度可以在大约200nm至800nm的范围内。
此外,半导体器件100的第一导电区域20、21被两个层6、7的层叠覆盖,其中第一钝化层6直接覆盖第一导电区域20、21,并且第二钝化层7被布置于其上,而第二导电区域22直接由第二钝化层7覆盖。
第一钝化层6和第二钝化层7通常由诸如氧化硅、氮化硅、氮氧化硅或半绝缘性的材料(诸如类金刚石碳)之类的不同材料制成。
在图1中所示的示例性实施例中,第一钝化层6厚于第二钝化层7。在其它一些实施例中,第一钝化层6薄于第二钝化层7。第一和第二钝化层6、7也可以具有基本相同的厚度。
此外,钝化结构6、7可以具有多于两个钝化层6、7。
如图1所示,钝化结构6、7和钝化层7、6分别通常同样覆盖有源区域110中的源极金属化结构10。
在一个实施例中,钝化结构6、7的第一部分被形成为氧化物-氮化物-层叠6、7,其具有大约100nm至大约5μm的厚度的氧化物6,更通常地,在大约100nm至大约3μm的范围内;并且氮化物7的厚度在大约100nm至大约1μm的范围内,并且钝化结构6、7的第二部分由具有从0至约100nm范围的厚度的氮化物7形成。
第二介电层9(例如,诸如酰亚胺(imide)层之类的有机介电层)通常被布置在***区域120和有源区域110中的钝化结构6、7上。第一介电层5和第二介电层9也同样分别被称为另外的介电层5和另外的介电层9。
此外,密封层19(例如,模制化合物和绝缘胶)通常被布置在***区域120和有源区域110中的介电层9上。
由于与内侧导电区域20,21相比在外侧导电区域22上使用较薄的钝化结构,因此可以实现抵抗外部电荷穿透以及抵抗潮湿导致的损坏的良好的稳健性。这是由数值仿真确认。
图2示出垂直半导体器件200的垂直截面。半导体器件200与上面针对图1阐述的半导体器件100相似,并且也可以作为功率场效应晶体管操作。然而,半导体器件200的钝化结构6,7由一个钝化层6形成,仅该钝化层具有在第二导电区域22上(旁边)与第一导电区域20,21和有源区域110相比较低的厚度。
此外,高n掺杂沟道截止区域4被布置在与第一表面101和边缘41相邻的第一半导体区域1中。在其它一些实施例中,沟道截止区域4是高p掺杂的。
图3示出垂直半导体器件300的垂直截面。半导体300与上面针对图1阐述的半导体器件100相似,并且也可以被作为功率场效应晶体管操作。然而,在半导体器件300的***区域120中不存在栅极场板21。
此外,半导体器件300的第一导电区域由在***区域120中形成源极场板的第一金属化结构10的最外侧部分20形成。
图4示出穿过垂直半导体器件400的垂直截面。半导体400与上述针对图1阐述的半导体器件100相似,并且也可以作为功率场效应晶体管操作。然而,在半导体器件400的***区域120中只存在一个第一导电区域20。
此外,钝化结构6,7的厚度在第二导电区域上是变化的。在第二导电区域22的内侧边缘区域中,钝化结构6,7的厚度与更靠近芯片边缘41的区域相比较厚。因此,在第二导电区域22(场板)处提供较厚的钝化结构,其中,期望在半导体器件400的阻断模式(将pn结14反向偏置)期间的相对较高的电场。
相应地,可以进一步改进在抵抗外部电荷的稳健性与抵抗潮湿相关的腐蚀的稳健性之间的权衡。
根据一个实施例,半导体器件400的***区域120包括场板20,其由具有变化的厚度的钝化结构6,7覆盖。
图5示出垂直半导体器件500的垂直截面。半导体500与上述针对图4阐述的半导体器件400相似,并且也可以被作为功率场效应晶体管操作。然而,钝化结构6仅由第一钝化层6形成。
此外,钝化结构6仅覆盖第一导电区域20的边缘部分。
根据一个实施例,半导体器件500的***区域120包括场板20,22,场板中的每一个仅部分地由钝化结构6覆盖。
此外,钝化结构6至少在垂直界面中可能是如图5中所示的不连续的。
图6示出垂直半导体器件600的垂直截面。半导体器件600与上述针对图1阐述的半导体器件100相似。半导体器件600可以被作为功率二极管或作为功率场效应晶体管操作。然而,钝化结构6,7通过第一钝化层6的部分形成在第一导电区域20,21上,并且通过较薄的第二钝化层7形成在第二导电区域上。
第一导电区域20,21可以是浮置的半导体区域。
此外,半导体器件600具有延伸至第一表面101和边缘41的较高掺杂的场截止半导体区域4a。
在图6中所示的示例性实施例中,当从上方观察时,第二半导体区域2和第一半导体区域20,21不重叠。
图7示出垂直半导体器件700的垂直截面。半导体器件700与上述针对图6阐述的半导体器件600相似。然而,当从上方观察时,第二半导体区域2与第一导电区域20,21实际上重叠。场板20,21可以具有与下面p掺杂的第二半导体区域2的欧姆接触。
图8示出垂直半导体器件800的垂直截面。半导体器件800与上述针对图6阐述的半导体器件600相似。
在图8中示出的示例性实施例中,三个浮置的第一半导体区域20,21,21’被布置在半导体器件800的***区域120中的第一表面101上,三个浮置的第一半导体区域与三个(p型)浮置保护环4b重叠,每个保护环与第一半导体区域1形成相应的pn结。场板20,21,21’可以具有与保护环4b的欧姆接触。
针对图9至图12,在相应的半导体主体40的垂直截面中被示出用于形成垂直半导体器件900的方法的方法步骤。为清楚起见,附图中的每个附图仅示出通常在晶片层级被并行制造的多个半导体器件900的一个半导体器件的左边部分。
在第一步骤中,提供在第一或上表面101和与主表面101相对布置的第二或背表面(未示出)之间延伸的半导体衬底或晶片40,例如,硅晶片。通常,晶片40包括延伸至第一表面101的第一导电类型(n型)的第一半导体层1、在第一表面处并且与第一半导体层1形成pn节的(p型)第二半导体区域2、以及延伸至半导体晶片40的第二表面的较高掺杂的第三半导体层(未示出)。
图10示出了例如通过热氧化在第一表面101上形成第一介电层5之后的半导体结构900。所示边缘41对应于后面形成的锯齿边缘。
在示例性实施例中,pn结14延伸至***区域120中的第一表面101。
此后,一个或多个场板20、21、22可以形成在第一介电层5上。这通常包括沉积诸如金属层之类的高导电层和掩膜蚀刻。
如图10中所示,场板20、21、22通常与第一金属化结构10共同形成在第一表面101上。
在参考形成功率场效应半导体器件的实施例中,具有相应栅极电极的多个场效应结构通常在分别形成场板20、21、22和第一金属化结构10之前在与第一表面101相邻的有源区域110中形成。
此后,第一钝化层6可以使用CVD工艺被沉积在场板20、21、22上,例如作为保形层。所获得的半导体结构900在图11中被示出。
此后,可以例如通过掩膜蚀刻来减小最外侧场板22的至少最外侧部分的第一钝化层6的厚度。所获得的半导体结构900在图12中被示出,图12示出如下实施例,其中第一钝化层6的厚度减小,使得在最外侧场板22处(具有比另外的场板20、21距有源区域更远的距离,并且在锯切之后与边缘41最接近)的第一钝化层6的最小厚度小于在另外的场板20、21处的最小厚度,而第一钝化层6的最大厚度在场板20、21、22上基本上相同。
在其它实施例中,第一钝化层6在最外侧场板22的所有邻接的表面上被薄化至基本相同的分数,例如,小于约50%,更通常地小于约20%,并且甚至更通常地小于约10%。
此后,或在形成第一钝化层6之前,第二钝化层(未示出)可以形成在第一钝化层6上,或形成在场板20、21、22上,例如,作为保形层。在这些实施例中,第一钝化层6也可以从最外侧场板22完全去除。第二钝化层通常薄于第一钝化层,例如,至少薄约5或甚至10倍。
此后,可以在第一钝化层6和第二钝化层上分别形成第二介电层。
此后,可以在第二介电层上沉积密封化合物。
此后,可以在第二表面102上形成与第二半导体区域2欧姆接触的第二金属化和最外侧场板22。
此后,可以通过锯切将晶片40分割成分离的半导体器件900。
尽管公开了本发明的各种实施例,但做出将实现本发明的一些优点的部分优点而不偏离本发明的主旨和范围的不同的变化以及改变对本领域的技术人员将是显而易见的。适当地替换执行相同功能的其它部件对本领域的技术人员是显而易见的。应该提及,参考特定附图阐述的特征可以与其它附图的特征组合,甚至在那些没有明确提及的情况下。这些针对本发明的发明性概念的改变旨在被随附的权利要求书所涵盖。
空间性相对术语,诸如“下方”、“下面”、“下部”、“上方”、“上部”等被用于简化说明,以阐述一个元件相对于第二元件的定位。这些术语旨在包含除了不同于附图中描绘的那些方位之外,器件的不同方位。此外,术语,诸如“第一”、“第二”等同样被用于描述各种元件、区域、部分等,并且并不旨为限定性的。整个说明书中,相同术语指出相同的元件。
如本文中使用的,术语“具有”、“包含”、“包括”等是开放性术语,其指出所述元件或特征的存在,但并不暗示额外的元件或特征。除非在上下文中明确指出,否则冠词“一个”、“一种”以及“这个”旨在包括复数以及单数形式。
通过记住上述变化以及应用,应该理解,本发明并不由前述说明书,也不由附图所限定。而是,本发明仅由随附的权利要求书以及它们的合法的等同方案所限定。
Claims (14)
1.一种垂直半导体器件(100-400,600-800),所述器件包括:
-半导体主体(40),所述半导体主体包括第一表面(101)、与所述第一表面相对的第二表面(102)、在垂直于所述第一表面的垂直方向上延伸的边缘(41)、有源区域(110)、在所述有源区域和所述边缘之间在平行于所述第一表面的水平方向上布置的***区域(120)、以及与所述第一表面相邻并且从所述有源区域延伸至所述***区域中的pn结(14);
其中在所述***区域(120)中,所述半导体器件还包括:
-第一导电区域(20、21),与所述第一表面相邻地布置;
-第二导电区域(22),与所述第一表面相邻地布置,并且在所述第一导电区域和所述边缘之间在所述水平方向上布置,从而在所述第二导电区域和所述边缘之间不具有其它导电区域;以及
-钝化结构(6、7),包括至少部分地覆盖所述第一导电区域(20、21)的第一钝化层、以及至少部分地覆盖所述第二导电区域(22)的第二钝化层,其中,所述第一钝化层包括与所述第二钝化层的第二厚度不同的第一厚度。
2.根据权利要求1所述的垂直半导体器件,其中,所述第一导电区域和所述第二导电区域中的至少一个被布置在所述第一表面上并且被形成为场板。
3.根据权利要求1所述的垂直半导体器件,进一步包括布置在所述钝化结构(6、7)上的介电层(9)。
4.根据权利要求1所述的垂直半导体器件,其中,所述第二厚度小于所述第一厚度。
5.根据权利要求1所述的垂直半导体器件,其中,所述第二厚度与所述第一厚度相差至少50%。
6.根据权利要求1所述的垂直半导体器件,其中,所述第二厚度低于100nm,并且其中所述第一厚度在从200nm至800nm的范围内。
7.根据权利要求3所述的垂直半导体器件,其中,所述介电层(9)包括有机材料。
8.根据权利要求1所述的垂直半导体器件,其中,所述第一钝化层仅覆盖所述第一导电区域。
9.根据权利要求1所述的垂直半导体器件,其中pn结在所述***区域中延伸至所述第一表面。
10.根据权利要求1所述的垂直半导体器件,其中所述有源区域包括多个IGBT单元、MOSFET单元和/或二极管单元。
11.根据权利要求1所述的垂直半导体器件,其中,所述第二钝化层完全覆盖所述第二导电区域。
12.根据权利要求11所述的垂直半导体器件,其中,所述第二钝化层完全还覆盖所述第一导电区域。
13.根据权利要求1所述的垂直半导体器件,进一步包括在所述半导体主体与所述第一导电区域和所述第二导电区域之间布置的介电层(5),从而所述第一导电区域和所述第二导电区域均不与所述半导体主体直接接触。
14.根据权利要求1所述的垂直半导体器件,其中,所述钝化结构包括无机材料。
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US20150303260A1 (en) | 2015-10-22 |
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