CN105023900A - 埋入硅基板扇出型封装结构及其制造方法 - Google Patents
埋入硅基板扇出型封装结构及其制造方法 Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 98
- 239000010703 silicon Substances 0.000 title claims abstract description 98
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 97
- 239000000758 substrate Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000004806 packaging method and process Methods 0.000 title abstract description 18
- 229920000642 polymer Polymers 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000003292 glue Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 34
- 239000010949 copper Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 19
- 239000004816 latex Substances 0.000 claims description 16
- 229920000126 latex Polymers 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229920001940 conductive polymer Polymers 0.000 claims description 3
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 21
- 239000011159 matrix material Substances 0.000 abstract description 9
- 239000004033 plastic Substances 0.000 abstract description 4
- 230000005855 radiation Effects 0.000 abstract 2
- 230000002411 adverse Effects 0.000 abstract 1
- 239000012778 molding material Substances 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 238000005538 encapsulation Methods 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 239000000206 moulding compound Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241001133184 Colletotrichum agaves Species 0.000 description 1
- 241000595008 Nanium Species 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001502 supplementing effect Effects 0.000 description 1
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Abstract
本发明公开了一种埋入硅基板扇出型封装结构及其制造方法,采用硅基体取代模塑料作为扇出的基体,充分利用硅基体的优势,能够制作精细布线。利用成熟的硅刻蚀工艺,可以精确刻蚀孔、槽等结构。通过将芯片埋入硅基体上的凹槽内,将聚合物胶填充芯片与凹槽侧壁之间的间隙,并把部分焊球扇出到硅基体表面,能够提高封装可靠性,工艺简单,成本低。由于硅基体的散热性好及具有更小的翘曲,有利于提高封装的散热性,克服不良翘曲,获得更小的布线线宽,适于高密度封装。工艺上,本发明可以取消圆片塑封,拆键合工艺,降低工艺难度,从而显著降低成本,提高成品率。
Description
技术领域
本发明涉及半导体封装技术领域,具体是涉及一种埋入硅基板扇出型封装结构及其制造方法。
背景技术
随着芯片变得越来越小,I/O数越来越多,芯片级封装已不能满足I/O扇出的要求。扇出型圆片级封装技术(FOWLP)是对圆片级芯片尺寸封装技术的补充,通过再构圆片的方式将芯片I/O端口引出,在重构的包封体上形成焊球或凸点终端阵列,在一定范围内可代替传统的引线键合焊球阵列(WBBGA)封装或倒装芯片焊球阵列(FCBGA)封装(<500I/Os)封装结构,特别适用于蓬勃发展的便携式消费电子领域。
FOWLP工艺在2008年就开始应用,主要是英飞凌无线(后来的英特尔的无线部门)的eWLB(Embedded Wafer Level BGA)技术,封装代工主要在STATS Chip PAC、NANIUM进行,主要应用是英特尔无线部门的基带芯片封装。随着FOWLP工艺技术逐渐成熟,成本不断降低,同时加上芯片工艺的不断提升(基带芯片和移动终端应用处理器芯片已经进入28nm量产),FOWLP可能出现爆发性增长。为了实现成本降低将会朝着大面板尺寸的封装工艺(Panel Size Fan-out WLP,PWLP)发展,并可能通过使用封装基板工艺实现。
标准的eWLB工艺流程如下:首先在一个载片上贴膜,然后把芯片焊盘面朝下放置于膜上;使用圆片级注塑工艺,将芯片埋入到模塑料中;固化模塑料,移除载片。之后对埋有芯片的模塑料圆片进行晶圆级工艺。在芯片焊盘暴露的一侧进行钝化、金属再布线、制备凸点底部金属层,植球,最后切片完成封装。
专利US20080308917与专利US2015003000使用聚合物等塑封材料包覆若干芯片,使芯片嵌入其中,再进行晶圆级工艺,该方法主要问题有以下几点。首先,聚合物胶圆片的翘曲问题,使用硅或者玻璃载片可以帮助减少翘曲,但带来临时键合和拆键合复杂工艺。研发新型低翘曲模塑料,材料成本高。其次,对于10×10mm到12×12mm扇出封装体,板级可靠性具有很大挑战,特别是与温度循环相关的测试,对于eWLB产品,板级连接后需要底部填充胶来提高可靠性。再次,对于使用聚合物胶圆片对产率具有很大影响。在注塑以及模塑料固化过程中芯片偏移是一个主要的工艺障碍。另一个要点是选择再布线介质材料,因为重构圆片需要适应再布线工艺制程,标准的晶圆级介质不能直接应用。
专利CN 104037133 A公开了一种扇出封装结构,该结构是在硅载板上开槽,芯片倒置于槽底,芯片焊盘电性通过线路引到硅载板表面;槽内用塑封材料填充,在塑封材料表面制作重布线金属,将线路电性导出。该结构及制程十分复杂,成本较高。
为解决上述问题,需要开发新的扇出型方案,具有很好的工艺加工性,更好的可靠性,降低成本。
发明内容
为了解决上述技术问题,本发明提出一种埋入硅基板扇出型封装结构及其制造方法,采用硅基体取代模塑料作为扇出的基体,充分利用硅基体的优势,能够制作精细布线,利用成熟的硅刻蚀工艺,可以精确刻蚀孔、槽等结构;且散热性能好。工艺上,还可以取消圆片塑封,拆键合工艺,降低工艺难度,从而显著降低成本,提高成品率。
本发明的技术方案是这样实现的:
一种埋入硅基板扇出型封装结构,包括一硅基体,所述硅基体具有第一表面和与其相对的第二表面,所述第一表面上形成有至少一个向所述第二表面延伸的凹槽,所述凹槽侧面与底面垂直或接近垂直,所述凹槽内放置有至少一颗芯片,所述芯片的焊盘面与所述凹槽底面反向,且所述芯片的焊盘面接近所述第一表面;所述芯片底部与所述凹槽底部之间设有一层粘附层,所述芯片侧面与所述凹槽的侧壁之间具有间隙,该间隙内填充有第一介质层;所述芯片及所述第一表面上形成有第二介质层;所述第二介质层上形成有至少一层与所述芯片的焊盘连接的金属布线,最外一层金属布线上覆盖有一层钝化层,且该金属布线上形成有用于植焊球的凸点下金属层,所述钝化层上开设有对应该凸点下金属层的开口,所述凸点下金属层上植有焊球或凸点;且至少有一个焊球或凸点及其对应的凸点下金属层位于所述硅基体的第一表面上。
作为本发明的进一步改进,所述凹槽的侧壁与所述芯片之间的距离大于1微米。
作为本发明的进一步改进,所述凹槽的槽底与所述硅基体的第二表面之间的距离大于1微米。
作为本发明的进一步改进,所述芯片的焊盘面和所述硅基体的第一表面之间的高度差小于50微米。
作为本发明的进一步改进,所述第一介质层的材料为聚合物胶。
作为本发明的进一步改进,所述第一介质层及所述第二介质层的材料均为同一种聚合物胶。
作为本发明的进一步改进,所述粘附层的厚度小于50微米,大于1微米。
作为本发明的进一步改进,所述粘附层为非导电聚合物胶或薄膜。
作为本发明的进一步改进,所述金属布线的材质为铜或铝。
作为本发明的进一步改进,所述焊球为铜柱焊料凸点或焊料球。
作为本发明的进一步改进,所述凸点下金属层为Ni/Au、Cr/W/Cu、Ti/W/Cu/Ni/Au、Ti/Cu中的一种。
一种埋入硅基板扇出型封装结构的制作方法,包括如下步骤:
A.提供一硅基体圆片,所述硅基体圆片具有第一表面和与其相对的第二表面,在所述硅基体圆片的第一表面刻蚀形成至少一个具有设定形状和深度的凹槽;
B.在所述凹槽内放置至少一个待封装的芯片,使所述芯片的焊盘面朝上,芯片背面涂布有一定厚度的粘附胶,芯片与凹槽底部粘接并固化,形成粘附层,所述芯片的焊盘面接近所述硅基体的第一表面,且所述芯片与所述凹槽的侧壁之间具有间隙;
C.通过涂布工艺,在所述凹槽的侧壁与所述芯片之间的间隙内填充聚合物胶,固化后形成一层绝缘的第一介质层;
D.在所述芯片的焊盘面上以及所述硅基体的第一表面上,形成一层绝缘的第二介质层;
E.打开所述芯片的焊盘上面的第二介质层,并在第二介质层上面制作连接芯片的焊盘的金属布线;
F.在所述金属布线上面制作一层钝化层,在该金属布线上需要植焊球的位置打开钝化层,在露出的金属布线上制备所需的凸点下金属层,然后进行凸点制备或植焊球,最后切片,形成一埋入硅基板扇出型封装结构。
作为本发明的进一步改进,在凸点制备或植焊球前后,将所述硅基体圆片的第二表面减薄,减薄后,凹槽底部到硅基体的第二表面之间的厚度大于1微米。
作为本发明的进一步改进,将待封装的芯片圆片减薄至设定厚度,然后在芯片圆片的非焊盘面刷粘附胶,划片后形成单颗芯片,通过拾取工具将带有粘附胶的芯片放置于所述硅基体上凹槽内。
作为本发明的进一步改进,在所述凹槽的侧壁与所述芯片之间的空隙内填充聚合物胶在真空环境下实施。
作为本发明的进一步改进,所述第二介质层为可光刻材料。
本发明的有益效果是:本发明提供一种埋入硅基板扇出型封装结构及其制造方法,采用硅基体取代模塑料作为扇出的基体,充分利用硅基体的优势,能够制作精细布线。利用成熟的硅刻蚀工艺,可以精确刻蚀孔、槽等结构。通过将芯片埋入硅基体上的凹槽内,并把部分焊球扇出到硅基体表面,能够提高封装可靠性,工艺简单,成本低。由于硅基体的散热性好,有利于提高封装的散热性。由于硅基体圆片具有更小的翘曲,可以获得更小的布线线宽,适于高密度封装。工艺上,本发明可以取消圆片塑封,拆键合工艺,降低工艺难度,从而显著降低成本,提高成品率。通过聚合物胶填充芯片与凹槽侧壁之间的间隙,防止芯片偏移;较佳的,芯片通过粘附层与凹槽底部黏结,可以更好的固定芯片,防止芯片偏移。较佳的,通过同一种聚合物胶形成第一介质层及第二介质层,可以提高封装体的可靠性。
附图说明
图1为本发明一个芯片埋入一个凹槽的扇出型封装结构;
图2为本发明两个芯片埋入一个凹槽的扇出型封装结构;
图3为本发明两个不同芯片分别埋入两个凹槽的扇出型封装结构。
结合附图,作以下说明:
1——硅基体 101——第一表面
102——第二表面 2——芯片
201——焊盘 3——第一介质层
4——第二介质层 5——金属布线
6——钝化层 7——焊球或凸点
8——粘附层
具体实施方式
为了能够更清楚地理解本发明的技术内容,特举以下实施例详细说明,其目的仅在于更好理解本发明的内容而非限制本发明的保护范围。实施例附图的结构中各组成部分未按正常比例缩放,故不代表实施例中各结构的实际相对大小。
实施例1
如图1所示,一种埋入硅基板扇出型封装结构,包括一硅基体1,所述硅基体具有第一表面101和与其相对的第二表面102,所述第一表面上形成有一个向所述第二表面延伸的凹槽,该凹槽最好为直槽或侧壁与底面角度在80度~120度的斜槽,这里不做限制。本实施例示意图为直槽形状。所述凹槽内放置有一颗芯片2,所述芯片的焊盘面朝上,且所述芯片的焊盘面接近所述第一表面;所述芯片与所述凹槽的槽底之间具有粘附层8,芯片通过粘附层与凹槽底部黏结,可以更好的固定芯片,防止芯片偏移。
所述芯片与所述凹槽的侧壁之间具有间隙,该间隙内填充有第一介质层3;所述芯片及所述第一表面上铺设有绝缘的第二介质层4;所述第二介质层上形成有至少一层与所述芯片的焊盘201连接的金属布线5,最外一层金属布线上覆盖有一层钝化层6,且该金属布线上形成有用于植焊球的凸点下金属层,所述钝化层上开设有对应该凸点下金属层的开口,所述开口内植有焊球或凸点7;且至少有一个焊球或凸点及其对应的凸点下金属层位于所述第一表面上。
优选的,所述凹槽的侧壁与所述芯片之间的距离大于1微米,以方便芯片放入凹槽槽底。
优选的,所述凹槽的槽底与所述硅基体的第二表面之间的距离大于1微米,以利于硅基体对芯片的支撑。
优选的,所述芯片的焊盘面和所述硅基体的第一表面之间的高度差小于50微米,以保证封装体表面材料的均一性。
优选的,所述第一介质层的材料为聚合物胶,附加真空涂布,使凹槽间隙内填充满该聚合物胶,以固定芯片,同时保证绝缘性能。
优选的,所述第一介质层及所述第二介质层的材料均为同一种聚合物胶,以提高封装体的可靠性。
优选的,所述粘附层为非导电聚合物胶或薄膜,粘接芯片与凹槽底面,保证在接下来的工艺中,芯片位置不发生偏移,以便于获得较好的对准精度,获得更细的再布线线条。聚合物胶可以通过在芯片晶圆背面涂布方式制备,薄膜可以通过在芯片晶圆背面压膜方式制备。
优选的,所述金属布线的材质为铜或铝。
优选的,所述焊球为铜柱焊料凸点或焊料球。
优选的,所述凸点下金属层为Ni/Au、Cr/W/Cu、Ti/W/Cu/Ni/Au、Ti/Cu中的一种,图示未画出,其中Ni/Au意为先形成一层金属镍,再在金属镍上形成一层金属金,同理Cr/W/Cu意为依次形成金属铬、金属钨、金属铜三层金属层,Ti/W/Cu/Ni/Au意为依次形成金属钛、金属钨、金属铜、金属镍、金属金五层金属层,Ti/Cu意为依次形成金属钛、金属铜两层金属层。
作为一种优选实施例,该埋入硅基板扇出型封装结构的制造方法按如下步骤实施:
A.提供一硅基体圆片,所述硅基体圆片具有第一表面和与其相对的第二表面,在所述硅基体圆片的第一表面刻蚀形成至少一个具有设定形状和深度的凹槽;
B.在所述凹槽内放置至少一个待封装的芯片,使所述芯片的焊盘面朝上,芯片背面涂布有一定厚度的粘附胶,芯片与凹槽底部粘接并固化,形成粘附层,所述芯片的焊盘面接近所述硅基体的第一表面,且所述芯片与所述凹槽的侧壁之间具有间隙;
C.通过涂布工艺,在所述凹槽的侧壁与所述芯片之间的间隙内填充胶体,固化后形成一层绝缘的第一介质层;
D.在所述芯片的焊盘面上以及所述硅基体的第一表面上,形成一层绝缘的第二介质层;
E.打开所述芯片的焊盘上面的第二介质层,并在第二介质层上面制作连接芯片的焊盘的金属布线;
F.在所述金属布线上面制作一层钝化层,在该金属布线上需要植焊球的位置打开钝化层,在露出的金属布线上制备所需的凸点下金属层,然后进行凸点制备或植焊球,最后切片,形成一埋入硅基板扇出型封装结构。
较佳的,步骤C中涂布工艺采用聚合物胶,步骤D中第二介质层与第一介质层为同一种聚合物胶,以提高封装体的可靠性。
优选的,在凸点制备或植焊球前后,将硅基体圆片的第二表面减薄到所需厚度。较佳的,减薄后,凹槽底部到硅基体的第二表面之间的厚度大于1微米。
优选的,将待封装的芯片圆片减薄至设定厚度,然后在芯片圆片的非焊盘面刷粘附胶,划片后形成单颗芯片,通过拾取工具将带有粘附胶的芯片放置于所述硅基体上凹槽内。
优选的,在所述凹槽的侧壁与所述芯片之间的空隙内填充胶体在真空环境下实施,可以减少气泡,确保间隙填充效果。
优选的,所述第二介质层为可光刻材料,钝化层为可光刻材料。以便使用光刻制程形成开口,暴露出芯片的焊盘,使金属布线连接焊盘。
实施例2
如图2所示,本实施例2包含实施例1的所有技术特征,其区别在于,硅基体的第一表面的一个凹槽内埋入有两颗芯片2,两颗芯片大小、功能可以相同或相异。该实施例可扩展封装体的功能。
实施例3
如图3所示,本实施例3包含实施例1的所有技术特征,其区别在于,硅基体的第一表面形成有两个凹槽,每个凹槽内分别埋入一颗芯片2,这两颗芯片大小、功能可以相同或相异。该实施例可扩展封装体的功能,同时降低两芯片之间的信号干扰。
本发明提供一种埋入硅基板扇出型封装结构及其制造方法,采用硅基体取代模塑料作为扇出的基体,充分利用硅基体的优势,能够制作精细布线。利用成熟的硅刻蚀工艺,可以精确刻蚀孔、槽等结构。通过将芯片埋入硅基体上的凹槽内,芯片通过粘附层与凹槽底部黏结固定,防止芯片偏移,通过再布线把芯片的I/O扇出到芯片和硅基体的表面,能够提高封装可靠性,工艺简单,成本低。由于硅基体的散热性好,有利于提高封装的散热性。由于硅基体圆片具有更小的翘曲,可以获得更小的布线线宽,适于高密度封装。工艺上,本发明可以取消圆片塑封,拆键合工艺,降低工艺难度,从而显著降低成本,提高成品率。通过聚合物胶填充芯片与凹槽侧壁之间的间隙,可防止芯片偏移;较佳的,通过同一种聚合物胶形成第一介质层及第二介质层,可以提高封装体的可靠性。
以上实施例是参照附图,对本发明的优选实施例进行详细说明。本领域的技术人员通过对上述实施例进行各种形式上的修改或变更,但不背离本发明的实质的情况下,都落在本发明的保护范围之内。
Claims (16)
1.一种埋入硅基板扇出型封装结构,其特征在于:包括一硅基体(1),所述硅基体具有第一表面(101)和与其相对的第二表面(102),所述第一表面上形成有至少一个向所述第二表面延伸的凹槽,所述凹槽侧面与底面垂直或接近垂直,所述凹槽内放置有至少一颗芯片(2),所述芯片的焊盘面与所述凹槽底面反向,且所述芯片的焊盘面接近所述第一表面;所述芯片底部与所述凹槽底部之间设有一层粘附层(8),所述芯片侧面与所述凹槽的侧壁之间具有间隙,该间隙内填充有第一介质层(3);所述芯片及所述第一表面上形成有第二介质层(4);所述第二介质层上形成有至少一层与所述芯片的焊盘(201)连接的金属布线(5),最外一层金属布线上覆盖有一层钝化层(6),且该金属布线上形成有用于植焊球的凸点下金属层,所述钝化层上开设有对应该凸点下金属层的开口,所述凸点下金属层上植有焊球或凸点(7);且至少有一个焊球或凸点及其对应的凸点下金属层位于所述硅基体的第一表面上。
2.根据权利要求1所述的埋入硅基板扇出型封装结构,其特征在于:所述凹槽的侧壁与所述芯片之间的距离大于1微米。
3.根据权利要求1所述的埋入硅基板扇出型封装结构,其特征在于:所述凹槽的槽底与所述硅基体的第二表面之间的距离大于1微米。
4.根据权利要求1所述的埋入硅基板扇出型封装结构,其特征在于:所述芯片的焊盘面和所述硅基体的第一表面之间的高度差小于50微米。
5.根据权利要求1所述的埋入硅基板扇出型封装结构,其特征在于:所述第一介质层的材料为聚合物胶。
6.根据权利要求1所述的埋入硅基板扇出型封装结构,其特征在于:所述第一介质层及所述第二介质层的材料均为同一种聚合物胶。
7.根据权利要求1所述的埋入硅基板扇出型封装结构,其特征在于:所述粘附层(8)的厚度小于50微米,大于1微米。
8.根据权利要求1所述的埋入硅基板扇出型封装结构,其特征在于:所述粘附层为非导电聚合物胶或薄膜。
9.根据权利要求1所述的一种埋入硅基板扇出型封装结构,其特征在于:所述金属布线的材质为铜或铝。
10.根据权利要求1所述的一种埋入硅基板扇出型封装结构,其特征在于:所述焊球为铜柱焊料凸点或焊料球。
11.根据权利要求1所述的一种埋入硅基板扇出型封装结构,其特征在于:所述凸点下金属层为Ni/Au、Cr/W/Cu、Ti/W/Cu/Ni/Au、Ti/Cu中的一种。
12.一种埋入硅基板扇出型封装结构的制作方法,其特征在于,包括如下步骤:
A.提供一硅基体圆片,所述硅基体圆片具有第一表面和与其相对的第二表面,在所述硅基体圆片的第一表面刻蚀形成至少一个具有设定形状和深度的凹槽;
B.在所述凹槽内放置至少一个待封装的芯片,使所述芯片的焊盘面朝上,芯片背面涂布有一定厚度的粘附胶,芯片与凹槽底部粘接并固化,形成粘附层,所述芯片的焊盘面接近所述硅基体的第一表面,且所述芯片与所述凹槽的侧壁之间具有间隙;
C.通过涂布工艺,在所述凹槽的侧壁与所述芯片之间的间隙内填充聚合物胶,固化后形成一层绝缘的第一介质层;
D.在所述芯片的焊盘面上以及所述硅基体的第一表面上,形成一层绝缘的第二介质层;
E.打开所述芯片的焊盘上面的第二介质层,并在第二介质层上面制作连接芯片的焊盘的金属布线;
F.在所述金属布线上面制作一层钝化层,在该金属布线上需要植焊球的位置打开钝化层,在露出的金属布线上制备所需的凸点下金属层,然后进行凸点制备或植焊球,最后切片,形成一埋入硅基板扇出型封装结构。
13.根据权利要求12所述的埋入硅基板扇出型封装结构的制作方法,其特征在于,在凸点制备或植焊球前后,将所述硅基体圆片的第二表面减薄,减薄后,凹槽底部到硅基体的第二表面之间的厚度大于1微米。
14.根据权利要求12所述的埋入硅基板扇出型封装结构的制作方法,其特征在于,将待封装的芯片圆片减薄至设定厚度,然后在芯片圆片的非焊盘面刷粘附胶,划片后形成单颗芯片,通过拾取工具将带有粘附胶的芯片放置于所述硅基体上凹槽内。
15.根据权利要求12所述的埋入硅基板扇出型封装结构的制作方法,其特征在于,在所述凹槽的侧壁与所述芯片之间的空隙内填充聚合物胶在真空环境下实施。
16.根据权利要求12所述的埋入硅基板扇出型封装结构的制作方法,其特征在于,所述第二介质层为可光刻材料。
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US11705365B2 (en) | 2021-05-18 | 2023-07-18 | Applied Materials, Inc. | Methods of micro-via formation for advanced packaging |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6400034B1 (en) * | 1999-07-12 | 2002-06-04 | Nec Corporation | Semiconductor device |
CN1691343A (zh) * | 2004-04-28 | 2005-11-02 | 育霈科技股份有限公司 | 图像感应器模块与晶圆级封装的结构及其形成方法 |
CN103646943A (zh) * | 2013-09-30 | 2014-03-19 | 南通富士通微电子股份有限公司 | 晶圆封装结构 |
CN204885147U (zh) * | 2015-08-11 | 2015-12-16 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型封装结构 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020070443A1 (en) * | 2000-12-08 | 2002-06-13 | Xiao-Chun Mu | Microelectronic package having an integrated heat sink and build-up layers |
JP4659488B2 (ja) * | 2005-03-02 | 2011-03-30 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
TWI352406B (en) * | 2006-11-16 | 2011-11-11 | Nan Ya Printed Circuit Board Corp | Embedded chip package with improved heat dissipati |
US20090230554A1 (en) * | 2008-03-13 | 2009-09-17 | Broadcom Corporation | Wafer-level redistribution packaging with die-containing openings |
US8847376B2 (en) * | 2010-07-23 | 2014-09-30 | Tessera, Inc. | Microelectronic elements with post-assembly planarization |
US8518746B2 (en) * | 2010-09-02 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die |
CN102110673B (zh) * | 2010-10-27 | 2014-01-29 | 中国科学院上海微***与信息技术研究所 | 使用光敏bcb为介质层的圆片级mmcm封装结构及方法 |
JP5636265B2 (ja) * | 2010-11-15 | 2014-12-03 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
CN104600058B (zh) * | 2015-02-03 | 2017-02-22 | 华天科技(昆山)电子有限公司 | 多芯片半导体封装结构及制作方法 |
CN105023900A (zh) * | 2015-08-11 | 2015-11-04 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型封装结构及其制造方法 |
CN105575913B (zh) * | 2016-02-23 | 2019-02-01 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型3d封装结构 |
-
2015
- 2015-08-11 CN CN201510486674.1A patent/CN105023900A/zh active Pending
-
2016
- 2016-06-15 KR KR1020187005298A patent/KR20180037988A/ko not_active Application Discontinuation
- 2016-06-15 EP EP16834516.3A patent/EP3336893A4/en not_active Withdrawn
- 2016-06-15 JP JP2018507534A patent/JP2018523315A/ja active Pending
- 2016-06-15 WO PCT/CN2016/085925 patent/WO2017024892A1/zh active Application Filing
-
2018
- 2018-02-11 US US15/893,691 patent/US20180182727A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6400034B1 (en) * | 1999-07-12 | 2002-06-04 | Nec Corporation | Semiconductor device |
CN1691343A (zh) * | 2004-04-28 | 2005-11-02 | 育霈科技股份有限公司 | 图像感应器模块与晶圆级封装的结构及其形成方法 |
CN103646943A (zh) * | 2013-09-30 | 2014-03-19 | 南通富士通微电子股份有限公司 | 晶圆封装结构 |
CN204885147U (zh) * | 2015-08-11 | 2015-12-16 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型封装结构 |
Cited By (35)
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US10559525B2 (en) | 2016-02-23 | 2020-02-11 | Huatian Technology (Kunshan) Electronics Co., Ltd. | Embedded silicon substrate fan-out type 3D packaging structure |
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CN113629005A (zh) * | 2021-06-29 | 2021-11-09 | 北京大学 | 扇出型封装填埋方法 |
CN113471160A (zh) * | 2021-06-29 | 2021-10-01 | 矽磐微电子(重庆)有限公司 | 芯片封装结构及其制作方法 |
WO2023065160A1 (zh) * | 2021-10-20 | 2023-04-27 | 庆鼎精密电子(淮安)有限公司 | 内埋电路板及其制作方法 |
CN114347491A (zh) * | 2022-02-14 | 2022-04-15 | 无锡宝通智能物联科技有限公司 | 用于输送带快速植入rfid芯片的方法 |
CN115346952A (zh) * | 2022-10-18 | 2022-11-15 | 合肥圣达电子科技实业有限公司 | 一种用于大功率大电流器件的封装结构及其制备方法 |
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WO2017024892A1 (zh) | 2017-02-16 |
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US20180182727A1 (en) | 2018-06-28 |
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JP2018523315A (ja) | 2018-08-16 |
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