CN110729255A - 一种键合墙体扇出器件的三维封装结构和方法 - Google Patents

一种键合墙体扇出器件的三维封装结构和方法 Download PDF

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CN110729255A
CN110729255A CN201910730417.6A CN201910730417A CN110729255A CN 110729255 A CN110729255 A CN 110729255A CN 201910730417 A CN201910730417 A CN 201910730417A CN 110729255 A CN110729255 A CN 110729255A
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于大全
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Xiamen Yun Tian Semiconductor Technology Co Ltd
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Priority to PCT/CN2020/107866 priority patent/WO2021023306A1/zh
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Abstract

一种键合墙体扇出器件的三维封装结构和方法，器件第一表面具有功能区和若干焊盘；其特征在于：器件除第一表面外具有包封材料；在器件第一表面制备有墙体结构并延展至包封材料第一表面，该墙体结构局部覆盖至少一焊盘且在焊盘处设有第一开口；设置有一盖板与墙体结构粘结，并在器件的功能区形成空腔结构，盖板上具有至少一个与第一开口相通的第二开口；盖板表面设置有金属互连结构通过第一开口、第二开口与焊盘电性连接。本发明能提高整体结构可靠性，降低风险、降低成本。

Description

一种键合墙体扇出器件的三维封装结构和方法
技术领域
本发明涉及半导体封装领域，特别是一种键合墙体扇出器件的三维封装结构和方法。
背景技术
对于众多MEMS，例如加速度计，RF开关，陀螺仪，以及多种传感器，例如滤波器，CMOS图像传感器，都需要形成一个保护空腔，用来保护器件，并为器件提供真空或气密工作环境。随着技术的发展，芯片的尺寸越来越小，而对于很多器件，比如SAW滤波器，CMOS图像传感器，密封墙体不能设置在器件表面，因此，用来形成空腔的墙体尺寸越来越窄，键合面积的减少对结合力，对器件的可靠性带来极大影响。必须要寻找新的低成本，高可靠性解决方案。
扇出型封装技术是目前的一个主流先进封装技术。随着芯片集成度的进一步提高、I/O数的进一步增加，传统晶圆级封装(WLCSP)的难以满足产品要求，需要解决WLCSP中I/O数过多与芯片面积过小的矛盾。英飞凌于2004年提出晶圆级扇出eWLB(Embedded WaferLevel BGA)技术(专利号US6727576B2)。该技术的主要特点是在芯片四周利用模塑料和芯片表面构建一个新的扇出平面，把金属布线从芯片引到扇出表面。扇出型封装技术原则上不再受芯片尺寸的限制，I/O数目，以及焊球节距都可以不再受限于芯片尺寸。由于不采用基板，封装的厚度降低，具有优良的成本，电性优势。
随着FOWLP工艺技术逐渐成熟，成本不断降低，同时加上芯片工艺的不断提升，FOWLP将出现爆发性增长。为节距传统AP处理器PoP封装的厚度，提高电性能，在FOWLP技术基础上，进一步开发了在模塑料上制作通孔互连的三维FOWLP堆叠技术。代表性的是台积电研发的InFO技术，为苹果A10,A11,A12 处理器提供封装服务，带动了整个业界研发三维FOWLP堆叠技术的热潮。
发明内容
本发明的主要目的在于克服现有技术中的上述缺陷，提出一种提高可靠性、降低风险和成本的一种键合墙体扇出器件的三维封装结构和方法。
本发明采用如下技术方案：
一种键合墙体扇出器件的三维封装结构，器件第一表面具有功能区和若干焊盘；其特征在于：器件除第一表面外具有包封材料；在器件第一表面制备有墙体结构并延展至包封材料第一表面，该墙体结构局部覆盖至少一焊盘且在焊盘处设有第一开口；设置有一盖板与墙体结构粘结，并在器件的功能区形成空腔结构，盖板上具有至少一个与第一开口相通的第二开口；盖板表面设置有金属互连结构通过第一开口、第二开口与焊盘电性连接。
优选的，所述盖板为聚合物膜、玻璃、硅或陶瓷。
优选的，所述墙体结构为聚合物、玻璃、陶瓷或绝缘体。
优选的，所述器件的材质为铌酸锂、钽酸锂、玻璃或硅。
优选的，所述包封材料为聚合物、塑封料、环氧树脂或玻璃浆料。
优选的，所述金属互连结构包括导电线路、钝化层和信号端口；该导电线路与盖板间绝缘，该导电线路布设于盖板表面并延伸至第二开口、第一开口以与焊盘电性连接；该钝化层覆盖导电线路和盖板的外露表面，并设有第三开口；信号端口位于第三开口处以与导电线路电性连接。
优选的，所述信号端口为BGA焊球、镍钯金、镍金或钛铜焊盘。
一种键合墙体扇出器件的三维封装方法，其特征在于：包括
1)将器件圆片进行划片；
2)通过拾取和放置，将器件放置于临时载板；
3)将器件进行包封；
4)将包封后的器件与载板分离，得到具有包封材料的重构圆片或方板；
5)在器件第一表面边缘及包封材料第一表面制作墙体结构并局部延伸至覆盖至少一焊盘，且在该焊盘处开口；
6)在墙体结构表面加盖板以在功能区形成空腔，且在焊盘处开口；
7)制作金属互连结构与焊盘电性连接。
优选的，步骤3)中，采用塑封、压膜或刷胶进行包封。
由上述对本发明的描述可知，与现有技术相比，本发明具有如下有益效果：
1、本发明采用包封材料将器件除第一表面外进行包封，并在器件和包封材料的第一表面设置墙体结构以支撑盖板，并形成大空腔，借助扇出的面积来制造墙体结构，使得墙体结构有足够的位置来加宽，提高整体结构可靠性，降低风险、降低成本。
2、本发明的结构和方法，通过重构圆片，使其属性不再脆弱，有利于提高产品的制程良率、易于加工、降低破片风险。
3、本发明的结构和方法，加大器件面积、减少无器件区面积，对于同样的一片原材料，增加器件数量，降低成本。
4、本发明的结构和方法，可采用晶圆级封装，适合大规模批量生产并降低生产成本，确保器件性能的一致性。
附图说明
图1为本发明的结构图；
图2为器件圆片结构图；
图3为划片示意图；
图4为图3俯视图；
图5为将芯片放入临时载板示意图；
图6为包封示意图；
图7为图6的俯视图；
图8为拆键合示意图；
图9为制作墙体结构示意图；
图10为图9的俯视图；
图11为制作盖板示意图；
图12为装置导电线路示意；
图13为图11的俯视图；
图14为本发明结构图(未划片)；
其中：10、器件，11、焊盘，12、功能区，13、空腔，20、包封材料，30、墙体结构，31、第一开口，40、盖板，41、第二开口，50、导电线路，60、钝化层，61、第三开口，70、信号端口，80、临时载板。
具体实施方式
以下通过具体实施方式对本发明作进一步的描述。
参照图1，一种键合墙体扇出器件的三维封装结构，包括器件10、包封材料20、墙体结构30、盖板40和金属互连结构等。该器件10的第一表面设有焊盘11和功能区12。该功能区12设有IDT，该焊盘11可为铝焊盘、铝镍金焊盘、铝镍钯金焊盘等。本发明器件的芯片类型为SAW滤波器、BAW滤波器或其它功能类似的滤波器件，器件10为铌酸锂、钽酸锂、玻璃、硅等圆片材料划片后的器件10。
该包封材料20将器件10除第一表面外进行包封，参见图1，包封材料20 将器件10的四个侧边和一个底边包封，器件的顶边作为第一表面且不包封。该包封材料20可通过塑封、压膜或刷胶实现，包封的厚度可根据需要设定。包封材料可以是聚合物、塑封料、环氧树脂或玻璃浆料等。
该墙体结构30设置于器件10第一表面边缘和包封材料20第一表面，该包封材料20的第一表面与器件10第一表面处于同一平面上，也即墙体结构30覆盖于器件10和包封材料20的第一表面交界面处，墙体结构30可完全覆盖或局部覆盖包封材料20第一表面。
墙体结构30还局部延伸至覆盖至少一焊盘11，且在该焊盘11处设有第一开口31，该第一开口31位于焊盘11上表面。该第一开口31的面积略小于焊盘 11面积。被墙体结构30覆盖的焊盘数量可以是一个、两个、三个甚至全部焊盘，在此不做限定。墙体结构30可为聚合物、玻璃、陶瓷或绝缘体等。
盖板40覆盖墙体结构30的表面，以在功能区12形成空腔13，且在焊盘 11处设有第二开口41。该空腔13的高度由墙体结构30厚度决定。该第二开口 41与第一开口31连通，第二开口41面积可略大于或等于第一开口31面积，优选为大于。该盖板40可为聚合物膜、玻璃、硅或陶瓷等材料。
金属互连结构布设于盖板40表面并延伸至第二开口41、第一开口31以与焊盘11电性连接。该金属互连结构包括导电线路50、钝化层60和信号端口70 等。该导电线路50与盖板40间绝缘，其布设于盖板40表面并延伸至第二开口 41、第一开口31以与焊盘11电性连接，该导电线路50采用金属材料。该钝化层60覆盖导电线路50和盖板40的外露表面，并在外连区域设有第三开口61。信号端口70位于第三开口61处以与导电线路50电性连接。
该钝化层60用于保护导电线路50，其可采用聚合物材料，提高产品的绝缘性能且对导电线路50起到防氧化的作用。该信号端口70为BGA焊球、镍钯金、镍金或钛铜焊盘。本发明的金属互连结构的实现方式不限于此，还可采用其它参见的金属外连结构实现。
本发明还提出一种键合墙体扇出器件的三维封装方法，用于制作上述的键合墙体扇出器件的三维封装结构，包括如下步骤：
1)参见图4,选择滤波器件圆片，将器件圆片进行划片得到单个器件10。该器件圆片为铌酸锂或碳酸锂等圆片，划片后的结构图参见图3、图4。
2)采用对位标记，通过拾取和放置，将器件10放置于临时载板80上，参见图5。
3)采用塑封、压膜或刷胶将器件10除第一表面进行包封，参见图6、图9，包封材料为聚合物、塑封料、环氧树脂或玻璃浆料等。
4)将包封后的器件与临时载板80分离，即移除临时载板80得到具有包封材料20的重构圆片或方板，参见图8。
5)在器件10第一表面边缘及包封材料20第一表面制作墙体结构30并局部延伸至覆盖至少一焊盘11，且在该焊盘11处开口形成第一开口31，该墙体结构30可为聚合物、玻璃、陶瓷或绝缘体，参见图9、图10。
6)在墙体结构30表面覆盖盖板40，从而在器件10的功能区12形成空腔 13，且在焊盘11处开口形成第二开口41。该盖板40可以是干膜、玻璃、硅或陶瓷等材料，可通过光刻或激光开孔，参见图11、图13。
7)制作金属互连结构与焊盘11电性连接。具体的，先在盖板40表面制作导电线路50，并延伸至第二开口41和第一开口31，与焊盘11电性连接，参见图12；再制作钝化层60覆盖导电线路50和盖板40的外露表面，并在外连区域进行光刻开口形成第三开口61。在外连区域的第三开口61处制作信号端口70，以与导电线路50电性连接。该信号端口70可以是BGA焊球、镍钯金、镍金或钛铜焊盘等常见的信号端口。
8)参见图14，对重构圆片或方板进行划片得到最终封装体。
对于芯片面积减小，带来的键合墙体变窄，而进一步影响器件可靠性，为了满足封装标准化的外形尺寸，本发明提出一种通过键合墙体扇出来解决芯片变小带来的具有密闭空腔晶圆级封装可靠性难题。本发明与标准扇出型封装将金属布线电信号扇出不同，先将器件划片，然后嵌入到另一种材料中，借助扇出的面积来制造墙体结构，使得墙体结构有足够的位置来加宽，实现大空腔、高可靠性、降低成本。
上述仅为本发明的具体实施方式，但本发明的设计构思并不局限于此，凡利用此构思对本发明进行非实质性的改动，均应属于侵犯本发明保护范围的行为。

Claims (9)

1.一种键合墙体扇出器件的三维封装结构，器件第一表面具有功能区和若干焊盘；其特征在于：器件除第一表面外具有包封材料；在器件第一表面制备有墙体结构并延展至包封材料第一表面，该墙体结构局部覆盖至少一焊盘且在焊盘处设有第一开口；设置有一盖板与墙体结构粘结，并在器件的功能区形成空腔结构，盖板上具有至少一个与第一开口相通的第二开口；盖板表面设置有金属互连结构通过第一开口、第二开口与焊盘电性连接。
2.如权利要求1所述的一种键合墙体扇出器件的三维封装结构，其特征在于：所述盖板为聚合物膜、玻璃、硅或陶瓷。
3.如权利要求1所述的一种键合墙体扇出器件的三维封装结构，其特征在于：所述墙体结构为聚合物、玻璃、陶瓷或绝缘体。
4.如权利要求1所述的一种键合墙体扇出器件的三维封装结构，其特征在于：所述器件的材质为铌酸锂、钽酸锂、玻璃或硅。
5.如权利要求1所述的一种键合墙体扇出器件的三维封装结构，其特征在于：所述包封材料为聚合物、塑封料、环氧树脂或玻璃浆料。
6.如权利要求1所述的一种键合墙体扇出器件的三维封装结构，其特征在于：所述金属互连结构包括导电线路、钝化层和信号端口；该导电线路与盖板间绝缘，该导电线路布设于盖板表面并延伸至第二开口、第一开口以与焊盘电性连接；该钝化层覆盖导电线路和盖板的外露表面，并设有第三开口；信号端口位于第三开口处以与导电线路电性连接。
7.如权利要求6所述的一种键合墙体扇出器件的三维封装结构，其特征在于：所述信号端口为BGA焊球、镍钯金、镍金或钛铜焊盘。
8.一种键合墙体扇出器件的三维封装方法，其特征在于：包括
1)将器件圆片进行划片；
2)通过拾取和放置，将器件放置于临时载板；
3)将器件进行包封；
4)将包封后的器件与载板分离，得到具有包封材料的重构圆片或方板；
5)在器件第一表面边缘及包封材料第一表面制作墙体结构并局部延伸至覆盖至少一焊盘，且在该焊盘处开口；
6)在墙体结构表面加盖板以在功能区形成空腔，且在焊盘处开口；
7)制作金属互连结构与焊盘电性连接。
9.如权利要求8所述一种键合墙体扇出器件的三维封装方法，其特征在于：步骤3)中，采用塑封、压膜或刷胶进行包封。
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