CN201663588U - Device realizing multi-phase clock fractional division - Google Patents
Device realizing multi-phase clock fractional division Download PDFInfo
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- CN201663588U CN201663588U CN2010201481792U CN201020148179U CN201663588U CN 201663588 U CN201663588 U CN 201663588U CN 2010201481792 U CN2010201481792 U CN 2010201481792U CN 201020148179 U CN201020148179 U CN 201020148179U CN 201663588 U CN201663588 U CN 201663588U
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Abstract
The utility model discloses a device realizing multi-phase clock fractional division, and relates to a frequency divider used in a digital-analog mixed chip. The device disclosed by the utility model comprises an accumulator, a trigger circuit and an edge detection unit, wherein the edge detection unit comprises N parallel edge detection circuits and an or gate; each edge detection circuit detects edges of two input clock signals according to enable signals generated by the accumulator, so as to generate control signals PROG; control signals PROG output by each edge detection circuit are converted into control signals PROG_OR after passing through the or gate; and the control signals PROG_OR are input to the accumulator as sequential control signals, and input to the trigger circuit as trigger signals. By adopting the technical scheme, the utility model can conduct fraction-frequency division with certain specific frequency dividing ratio on high-frequency clock signals, and can be realized more simply.
Description
Technical field
The utility model relates to the frequency divider in the digital-to-analogue hybrid chip, particularly a kind of device of realizing the multiphase clock fraction division.
Background technology
Integrated circuit of today (Integrated Circuit, IC) in, communication system class especially, integrated increasing subsystem.All need a clock signal (Clock) to come (Synchronization) synchronously between many subsystems.Because the difference of standard, the synchronised clock frequency that needs between different sub-systems is different, still, in order to save chip area and to reduce power consumption, people often tend on a chip, use a phase-locked loop (Phase-locked Loop, PLL).Therefore, needs will occur in chip design uses fraction division to produce the situation of a frequency clock.
In order to reduce the shake of consequent synchronised clock, wherein a kind of method of the most frequently used realization fraction division is to produce a series of frequency unanimities, the fixing clock signal of phase difference with phase-locked loop earlier, re-uses Digital Logical Circuits and produces final clock signal by the clock selecting that moves in circles.The circuit diagram that is a kind of multiphase clock frequency division in the prior art shown in Figure 1,110 is a multiplexer (Multiplexer) among the figure, and 120 is an accumulator (Accumulator), and 130 is a frequency divider (Divider).Wherein, the output of accumulator is as the selection signal of multiplexer, and the output of multiplexer is as the clock signal of accumulator and frequency divider.During operate as normal, multiplexer selects a clock as clock signal C 1 output, because the phase difference between CLK0～CLKn-1 is T in each period from CLK0～CLKn-1 according to the output signal SEL of accumulator
Ref/ n, therefore, if frequency code MOD is made as m, the frequency dividing ratio of frequency divider is made as M, and then the frequency of clock signal Cout is nf
Ref/ (mM), promptly be equivalent to input clock f
RefDone the fraction division operation, frequency dividing ratio is (mM)/n.But exist a problem to be in the circuit shown in Figure 1, as the reference clock frequency f of input multiplexer 110
RefHigher or the n value is bigger, i.e. phase difference between the clock in twos
Hour, the time Δ T between two rising edge clocks lacks (as shown in Figure 2), accumulator 120 can not be at this moment between in finish the operation that adds up, cause producing correct output frequency.In addition, also exist a problem to be in the circuit shown in Figure 1, clock C1 is that multiplexer 110 and accumulator 120 produce through frequency multiplication, therefore the frequency of clock C1 is higher, rate request for the frequency divider 130 of back is higher, thereby existing multiphase clock frequency splitting technology relatively is suitable for the application of low frequency.
In order to carry out frequency division to the clock signal of higher frequency, also has a kind of multiphase clock frequency dividing circuit shown in Figure 3 in the prior art, wherein 210 is a multiplexer (Multiplexer), 220 is an accumulator (Accumulator), 230 is a counter (Counter), and 240 is a trigger circuit (ToggleCircuit).Multiplexer 210 selects a clock as clock signal C 1 output in each period from CLK0～CLKn-1 according to the output signal SEL of accumulator 220, the C1 signal rising edge counting of 230 pairs of outputs of counter, when counting down to N, export a pulse signal C2, trigger accumulator and add up, change the selection signal SEL of multiplexer.Because the phase difference between CLK0～CLKn-1 is T
Ref/ n, therefore, if frequency code MOD is made as m, then every (N+m/n) T
RefTime C2 produces a pulse, and the frequency of output signal Cout is f
Ref/ [2 (N+m/n)], frequency dividing ratio is 2 (N+m/n).The shortcoming of this technology is, when the output of multiplexer is chosen in the shade period shown in Figure 4 when changing, the output of multiplexer will produce the rising edge (False Edge) of a mistake, thereby false triggering accumulator and trigger circuit cause producing wrong clock signal.Therefore, need to propose a kind of high-frequency multiphase clock frequency dividing circuit that is applicable to, to avoid occurring above-mentioned false triggering.
The utility model content
Technical problem to be solved by this invention is a kind of device of realizing the multiphase clock fraction division to be provided, thereby high frequency clock signal is carried out fraction division.
In order to address the above problem, the utility model discloses a kind of device of realizing the multiphase clock fraction division, comprise accumulator, trigger circuit and along detecting unit, wherein:
Described along detecting unit comprise n parallel along testing circuit and one or, each detects the edge of two clock signals of input according to the enable signal that described accumulator produces along testing circuit, produce control signal PROG, each control signal PROG along testing circuit output passes through described or produces control signal PROG_OR behind the door, described control signal PROG_OR is input to described accumulator as timing control signal, and described control signal PROG_OR is input to described trigger circuit as triggering signal simultaneously;
Wherein, described n the phase difference between each two clock signal importing along testing circuit is all equal along in the testing circuit, and described n is identical with the total number of the clock signal of input.
Further, in the said apparatus, describedly comprise control module and along trigger module along testing circuit, wherein: described control module, first rising edge of clock signal to input is counted, and when counting down to predetermined value, detect the trailing edge of first clock signal, and produce the enable signal that second clock signal rising edge detects according to testing result;
Described along trigger module, first rising edge in first clock signal comes then, with control signal PROG set, thereafter the enable signal that produces of the enable signal that detects of the second clock signal rising edge that produces according to described control module and described accumulator, detect the rising edge of second clock signal, when the rising edge of second clock signal arrived, PROG resetted with control signal.
Described predetermined value is N-1, and N is an integer, and wherein, N is smaller or equal to 1/2nd of the integer part of the frequency dividing ratio that will realize.
Preferably, when the integer part of the frequency dividing ratio that will realize is even number, N equal described frequency dividing ratio integer part 1/2nd.
Each is along the phase difference between two clock signals of testing circuit input
Wherein,
For the frequency dividing ratio that will realize deducts 1/2nd of remaining fractional part behind the 2N, T
RefBe cycle of clock signal of input.
Described control module comprises the D flip-flop that is used for the counter that first rising edge of clock signal is counted and is used to detect the trailing edge of first clock signal.
Described counter is a programmable counter.
Describedly comprise first D flip-flop that is used to detect first rising edge clock signal, second D flip-flop that is used to detect second clock signal rising edge, two and door, a NOR gate and a not gate along trigger module.
Described trigger circuit, being used for described control signal PROG_OR thixotroping along detecting unit output is produced duty ratio is 50% clock signal.
Described each the edge of two clock signals of input is sequentially detected according to the enable signal that described accumulator produces along testing circuit.
Described accumulator, the fixed code that is used to add up is to produce described enable signal.
Adopt technical solution of the present invention, can carry out the fraction division of some specific frequency dividing ratio to high frequency clock signal, and technical solution of the present invention implements fairly simple.
Description of drawings
Fig. 1 is the schematic diagram of a kind of multiphase clock frequency dividing circuit in the prior art;
The technological difficulties schematic diagram of Fig. 2 for occurring in the circuit shown in Figure 1;
Fig. 3 is the schematic diagram of another kind of multiphase clock frequency dividing circuit in the prior art;
The technological difficulties schematic diagram of Fig. 4 for occurring in the circuit shown in Figure 3;
Fig. 5 is the device schematic diagram of multiphase clock fraction division proposed by the invention;
Inside key signal when Fig. 6 is a device operate as normal shown in Figure 5 concerns schematic diagram;
Fig. 7 is along the internal structure schematic diagram of detecting unit in the device shown in Figure 5;
Fig. 8 be device shown in Figure 5 during along the detecting unit operate as normal internal signal concern schematic diagram.
Embodiment
Below in conjunction with drawings and the specific embodiments technical solution of the present invention is described in further details.
A kind of device of realizing the multiphase clock fraction division, its frequency dividing ratio that will realize is
As shown in Figure 5, comprise along detecting unit, accumulator (330) and trigger circuit (340) (Toggle Circuit).
Wherein, accumulator (Accumulator), the fixed code that is used to add up is to produce enable signal (ENABLE), and wherein accumulator carries out sequencing control according to the signal PROG_OR that is combined by the control signal along detecting unit output;
Trigger circuit (Toggle Circuit) is 50% clock signal (CLKout) according to signal PROG_OR triggering for generating duty ratio;
Along detecting unit, comprise parallel n curb testing circuit (310) and one or (320), the value of n equates with the total number of the clock signal of input, each enable signal (ENABLE) that (EdgeDetector) (Accumulator) produces according to accumulator (330) along testing circuit (310) sequentially detects the edge of clock signal in twos, and produce control signal PROG (as shown in Figure 5, first control signal that produces to n along testing circuit is respectively PROG_0～PROG_n-1), again by or the door (320) these control signals are combined into unified control signal PROG_OR, control signal PROG_OR is input to accumulator 330 as timing control signal, input to trigger circuit (340) as triggering signal, trigger circuit (340) is 50% clock signal according to this triggering signal generation duty ratio.
Since in the device shown in Figure 5 or door (320) each is combined into control signal PROG_OR along control signal PROG_0～PROG_n-1 that detecting unit produces, and accumulator is to be triggered by the trailing edge of PROG_OR, therefore (PROG_0～PROG_n-1) high level is nonoverlapping to this group control signal, along each is a sequential working along testing circuit in the detecting unit.The length of control signal PROG_0～PROG_n-1 high level (being the lasting duration of high level) is
Wherein, N is an integer, and N smaller or equal to the integer part of the frequency dividing ratio that will realize 1/2nd (wherein, when the integer part of the frequency dividing ratio that will realize is even number, the preferred value of N be equal frequency dividing ratio integer part 1/2nd, when the integer part of the frequency dividing ratio that will realize is odd number, the value of N be less than the integer part of frequency dividing ratio 1/2nd)
Be the frequency dividing ratio that will realize fractional part 1/2nd, all differ T between each high level
Ref, as shown in Figure 6, the PROG_OR signal is that one-period is
Signal, and be signal CLKout cycle of 50% to be by the duty ratio that the thixotroping of PROG_OR signal produces
Frequency is
Promptly realized
Fraction division doubly.
In the present embodiment, each further comprises control module (Control Module) (420) and edge triggering (Edge Trigger) module (410) along testing circuit as shown in Figure 7; Control module (420) comprises a counter (421) and a D flip-flop (422), comprise two D flip-flops (411) and (412), two and door (413) and (416), a NOR gate (414) and a not gate (415) along trigger module (410);
Along the operation principle of trigger module as shown in Figure 8, as the enable signal enable_module of control module when being high, this starts working along trigger module, counter (421) begins the rising edge counting to first clock signal (CLKa), and first rising edge of working as first clock signal (CLKa) comes then, the output set of D flip-flop (411), signal PROG becomes high level.When initial, signal cnt and enable_clkb are low level, and d type flip flop (412) is in reset mode.When counter (421) count down to predetermined value (N-1) (wherein, N be the frequency dividing ratio that will realize integer part value 1/2nd), signal cnt is changed to high level, d type flip flop (422) is after the next trailing edge of first clock signal (CLKa) is sampled to signal cnt, the enable signal (being signal enable_clkb) that the rising edge of second clock signal (CLKb) is detected is changed to high level, make d type flip flop (412) be in normal operating conditions, the next rising edge for the treatment of second clock signal (CLKb) comes temporarily the output set of d type flip flop (412).At this moment, because the output of d type flip flop (411) and (412) is high level, so signal clr resets, and then reset simultaneously d type flip flop (411) and (412) make signal PROG be reset to low level again.In the present embodiment since the fractional part of the frequency dividing ratio that will realize 1/2nd be
And the phase difference between the adjacent input clock signal just in time is
Therefore will adjacent clock signal input to respectively as first clock signal and second clock signal and get final product along testing circuit, like this, the length of signal PROG high level is
Final output clock frequency is
Frequency dividing ratio is
And in other scenes, if the frequency dividing ratio that will realize is
The time, then be with phase difference
Clock signal in twos input to respectively along in the detecting unit each along testing circuit,
Be and deduct 1/2nd of remaining fractional part behind the integer 2N in the frequency dividing ratio that will realize, for example CLK0 and CLKm are imported first along testing circuit, CLKm and CLK2m are imported second along testing circuit, the rest may be inferred, CLKn-m and CLK0 are imported n along testing circuit, so then can produce frequency and be
Clock signal, promptly realized frequency dividing ratio
From the foregoing description as can be seen, output reaches that stable to enable the next permission time along testing circuit be an input clock cycle T from the triggering signal of accumulator to accumulator
Ref, therefore allow higher input clock frequency (f
Ref) and bigger n value, promptly less input clock phase difference
Thereby can realize more fraction division ratio.In addition, technical solution of the present invention, directly do not adopt the different clock signal of multiplexer gating, and be to use the fixing between any two edge of different clocks signal to concern, produce the control signal that a series of relations are fixed, frequency is consistent earlier, again these control signals are combined, through trigger circuit, produce a duty ratio and be 50%, the cycle is the clock signal of input signal cycle branch several times, reach the function of fraction division, thereby therefore do not need extra control circuit to prevent some wrong signals along causing frequency division mistake to occur.When reality was used, counter also can use programmable counter, thereby can adjust the frequency dividing ratio of frequency dividing circuit of the present invention by the mode of configuration register.
The above is a preferred embodiments of the present utility model only, is not to be used to limit protection range of the present utility model.All within spirit of the present utility model and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within the protection range of the appended claim of the utility model.
Claims (11)
1. a device of realizing the multiphase clock fraction division comprises accumulator and trigger circuit, it is characterized in that, this device also comprises along detecting unit, wherein:
Described along detecting unit comprise n parallel along testing circuit and one or, each detects the edge of two clock signals of input according to the enable signal that described accumulator produces along testing circuit, produce control signal PROG, each control signal PROG along testing circuit output passes through described or produces control signal PROG_OR behind the door, described control signal PROG_OR is input to described accumulator as timing control signal, and described control signal PROG_OR is input to described trigger circuit as triggering signal simultaneously;
Wherein, described n the phase difference between each two clock signal importing along testing circuit is all equal along in the testing circuit, and described n is identical with the total number of the clock signal of input.
2. device as claimed in claim 1 is characterized in that, describedly comprises control module and along trigger module, wherein along testing circuit:
Described control module is counted first rising edge of clock signal of input, and when counting down to predetermined value, is detected the trailing edge of first clock signal, and produces the enable signal that second clock signal rising edge detects according to testing result;
Described along trigger module, first rising edge in first clock signal comes then, with control signal PROG set, thereafter the enable signal that produces of the enable signal that detects of the second clock signal rising edge that produces according to described control module and described accumulator, detect the rising edge of second clock signal, when the rising edge of second clock signal arrived, PROG resetted with control signal.
3. device as claimed in claim 2 is characterized in that,
Described predetermined value is N-1, and N is an integer, and wherein, N is smaller or equal to 1/2nd of the integer part of the frequency dividing ratio that will realize.
4. device as claimed in claim 3 is characterized in that,
When the integer part of the frequency dividing ratio that will realize is even number, N equal described frequency dividing ratio integer part 1/2nd.
5. as claim 3 or 4 described devices, it is characterized in that,
Each is along the phase difference between two clock signals of testing circuit input
Wherein,
For the frequency dividing ratio that will realize deducts 1/2nd of remaining fractional part behind the 2N, T
RefBe cycle of clock signal of input.
6. as claim 2 or 3 described devices, it is characterized in that,
Described control module comprises the D flip-flop that is used for the counter that first rising edge of clock signal is counted and is used to detect the trailing edge of first clock signal.
7. device as claimed in claim 6 is characterized in that, described counter is a programmable counter.
8. device as claimed in claim 7 is characterized in that,
Describedly comprise first D flip-flop that is used to detect first rising edge clock signal, second D flip-flop that is used to detect second clock signal rising edge, two and door, a NOR gate and a not gate along trigger module.
9. as claim 1,2 or 3 described devices, it is characterized in that,
Described trigger circuit, being used for described control signal PROG_OR thixotroping along detecting unit output is produced duty ratio is 50% clock signal.
10. as claim 1,2 or 3 described devices, it is characterized in that,
Described each the edge of two clock signals of input is sequentially detected according to the enable signal that described accumulator produces along testing circuit.
11. as claim 1,2 or 3 described devices, it is characterized in that,
Described accumulator, the fixed code that is used to add up is to produce described enable signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102323482A (en) * | 2011-08-05 | 2012-01-18 | 天津市德力电子仪器有限公司 | Method for measuring phase frequency characteristic by using digital intermediate-frequency spectrum analyzer during network analysis and measurement |
| CN103684445A (en) * | 2012-09-11 | 2014-03-26 | 成都锐成芯微科技有限责任公司 | Multiphase high-resolution phase locked loop |
| CN103854694A (en) * | 2012-11-29 | 2014-06-11 | 爱思开海力士有限公司 | Multi-phase clock generation circuit |
| CN105187052A (en) * | 2015-09-02 | 2015-12-23 | 深圳市同创国芯电子有限公司 | Programmable decimal frequency division circuit |
| WO2017121228A1 (en) * | 2016-01-15 | 2017-07-20 | 深圳市中兴微电子技术有限公司 | Method for keeping phases of frequency division clocks consistent and frequency division circuit |
| CN107425844A (en) * | 2017-07-17 | 2017-12-01 | 北京时代民芯科技有限公司 | A kind of configurable clock buffer suitable for SRAM type FPGA |
| CN108736882A (en) * | 2017-04-21 | 2018-11-02 | 展讯通信（上海）有限公司 | Fractional frequency divider circuit and rf terminal |
| CN113472345A (en) * | 2021-06-30 | 2021-10-01 | 北京时代民芯科技有限公司 | Configurable fractional frequency divider |
| CN114518781A (en) * | 2022-01-07 | 2022-05-20 | 西安电子科技大学 | Dual-mode adjustable high-precision baud rate clock generator and frequency division method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102323482B (en) * | 2011-08-05 | 2013-04-03 | 天津市德力电子仪器有限公司 | Method for measuring phase frequency characteristic by using digital intermediate-frequency spectrum analyzer during network analysis and measurement |
| CN102323482A (en) * | 2011-08-05 | 2012-01-18 | 天津市德力电子仪器有限公司 | Method for measuring phase frequency characteristic by using digital intermediate-frequency spectrum analyzer during network analysis and measurement |
| CN103684445A (en) * | 2012-09-11 | 2014-03-26 | 成都锐成芯微科技有限责任公司 | Multiphase high-resolution phase locked loop |
| CN103684445B (en) * | 2012-09-11 | 2016-08-17 | 成都锐成芯微科技有限责任公司 | Multiphase high-resolution phaselocked loop |
| CN103854694A (en) * | 2012-11-29 | 2014-06-11 | 爱思开海力士有限公司 | Multi-phase clock generation circuit |
| CN103854694B (en) * | 2012-11-29 | 2018-04-17 | 爱思开海力士有限公司 | Circuit occurs for multiphase clock |
| CN105187052A (en) * | 2015-09-02 | 2015-12-23 | 深圳市同创国芯电子有限公司 | Programmable decimal frequency division circuit |
| CN105187052B (en) * | 2015-09-02 | 2017-11-14 | 深圳市紫光同创电子有限公司 | A kind of programmable decimal frequency dividing circuit |
| WO2017121228A1 (en) * | 2016-01-15 | 2017-07-20 | 深圳市中兴微电子技术有限公司 | Method for keeping phases of frequency division clocks consistent and frequency division circuit |
| CN108736882B (en) * | 2017-04-21 | 2021-12-14 | 展讯通信（上海）有限公司 | Fractional frequency division circuit and radio frequency terminal |
| CN108736882A (en) * | 2017-04-21 | 2018-11-02 | 展讯通信（上海）有限公司 | Fractional frequency divider circuit and rf terminal |
| CN107425844A (en) * | 2017-07-17 | 2017-12-01 | 北京时代民芯科技有限公司 | A kind of configurable clock buffer suitable for SRAM type FPGA |
| CN107425844B (en) * | 2017-07-17 | 2020-09-11 | 北京时代民芯科技有限公司 | Configurable clock buffer suitable for SRAM type FPGA |
| CN113472345A (en) * | 2021-06-30 | 2021-10-01 | 北京时代民芯科技有限公司 | Configurable fractional frequency divider |
| CN113472345B (en) * | 2021-06-30 | 2023-10-03 | 北京时代民芯科技有限公司 | Configurable fractional frequency divider |
| CN114518781A (en) * | 2022-01-07 | 2022-05-20 | 西安电子科技大学 | Dual-mode adjustable high-precision baud rate clock generator and frequency division method |
| CN114518781B (en) * | 2022-01-07 | 2024-05-14 | 西安电子科技大学 | Dual-mode adjustable high-precision baud rate clock generator and frequency division method |
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Effective date of registration: 20151113 Address after: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Patentee after: ZTE Corporation Patentee after: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Patentee before: ZTE Corporation |
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