CN104396004A - 三维存储器阵列的多级接触及其制造方法 - Google Patents
三维存储器阵列的多级接触及其制造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 45
- 238000009413 insulation Methods 0.000 claims description 53
- 239000000463 material Substances 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 230000004888 barrier function Effects 0.000 claims description 29
- 238000003860 storage Methods 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 24
- 239000011810 insulating material Substances 0.000 claims description 19
- 230000002238 attenuated effect Effects 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000007800 oxidant agent Substances 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 8
- NOQGZXFMHARMLW-UHFFFAOYSA-N Daminozide Chemical group CN(C)NC(=O)CCC(O)=O NOQGZXFMHARMLW-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- -1 hafnium nitride Chemical class 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011370 conductive nanoparticle Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 239000011796 hollow space material Substances 0.000 description 1
- 210000001161 mammalian embryo Anatomy 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000005405 multipole Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 description 1
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Abstract
一种制造多级接触的方法。该方法包括提供工艺过程多级装置,该多级装置包括至少一个装置区域和至少一个接触区域。该接触区域包括构造为台阶图案的多个导电层。该方法还包括在该多个导电层上方形成共形的蚀刻终止层(122),在该蚀刻终止层(122)的上方形成第一电绝缘层(124),在该第一电绝缘层的上方形成共形的牺牲层(126)和在该牺牲层上方形成第二电绝缘层(128)。该方法还包括蚀刻多个接触开口(130A-E),穿过在该接触区域中的该蚀刻终止层、该第一电绝缘层、该牺牲层和该第二电绝缘层,到达该多个导电层。
Description
技术领域
本发明大体涉及半导体装置领域,特别涉及三维(3D)垂直NAND串和其它三维装置及其制造方法。
背景技术
T.Endoh等人的标题为“Novel Ultra High Density Memory With AStacked-Surrounding Gate Transistor(S-SGT)Structured Cell”,IEDM Proc.(2001)33-36的文章公开了三维垂直NAND串。然而,该NAND串只提供了每单元一位元。进一步地,NAND串的有源区域由相对困难和耗时的工艺形成,该工艺包括侧壁间隔件的重复形成和蚀刻衬底的一部分,这导致了大致圆锥形的有源区域形状。
发明内容
一个实施例涉及一种制造多级接触的方法。该方法包括提供工艺过程中的多级装置,包括至少一个装置区域和至少一个接触区域。该接触区域包括构造为台阶图案的多个导电层。该方法还包括在该多个导电层的上方形成共形的蚀刻终止层,在该蚀刻终止层的上方形成第一电绝缘层,在该第一电绝缘层的上方形成共形的牺牲层和在该牺牲层的上方形成第二电绝缘层。该方法还包括蚀刻多个接触开口,该多个接触开口穿过该接触区域的蚀刻终止层、第一电绝缘层、牺牲层和第二电绝缘层,到达该多个导电层。
另一个实施例涉及一种制造多级接触的方法。该方法包括提供工艺过程中的多级装置,包括至少一个装置区域和至少一个接触区域。该接触区域包括构造为台阶图案的多个导电层,位于该导电层上方的电绝缘层,位于该绝缘层的上方的具有多个开口的掩模,以及位于该掩模上方的减薄层。该方法还包括蚀刻该减薄层以减小其厚度和宽度,从而暴露在该掩模中的第一开口,蚀刻该电绝缘材料的暴露于该第一开口中的一部分以形成在电绝缘材料中的第一接触开口的一部分;进一步蚀刻该减薄层以减小其厚度和宽度,从而暴露在该掩模中的第二开口。
另一个实施例涉及包括至少一个装置区域和至少一个接触区域的多级装置。该接触区域具有多个堆叠导电层。该导电层形成在该接触区域中的台阶图案。该装置还包括在该导电层上方的共形的蚀刻终止层、在该蚀刻终止层上方的第一电绝缘层、在该第一电绝缘层上方的牺牲层和在该牺牲层上方的第二电绝缘层。该装置还包括多个接触开口,延伸穿过该接触区域的蚀刻终止层、第一电绝缘层、牺牲层和第二电绝缘层,到达该多个导电层。该装置还包括多个导电接触。多个电接触的相应的一个位于该多个接触开口的对应的一个中,并且每一个导电接触与该多个导电层的对应的一个电接触。
附图说明
图1A-1B分别是一个实施例中的NAND串的侧视横截面图和俯视横截面图。图1A是该装置沿着图1B中线Y-Y’的侧视横截面图,而图1B是该装置沿着图1A中线X-X’的侧视横截面图。
图2A和2B分别是另一个实施例中的NAND串的侧视横截面图和俯视横截面图。图2A是该装置沿着图2B中线Y-Y’的侧视横截面图,而图2B是该装置沿着图2A中线X-X’的侧视横截面图。
图3是常规的NAND串存储器装置的示意说明。
图4是示出了栅电极的接触的常规的NAND串存储器装置的横截面的扫描电子显微镜(SEM)图像。
图5是制造多级接触的常规方法的示意说明。
图6是根据一个实施例制造多级接触的方法的示意说明。
图7是提供图6的方法的附加细节的示意说明。
图8是示出了根据一个实施例的第一(下)介电层的损耗作为第二共形介电层的厚度的函数的图。
图9a是示出了在第二共形介电层的厚度为600nm时第一(下)介电层的损耗作为第三共形介电层的厚度的函数的图。
图9b是示出了在第二共形介电层的厚度为400nm时第一(下)介电层的损耗作为第三共形介电层的厚度的函数的图。
图10a-10b分别是根据一个实施例的在制造多级接触的方法中的一个步骤的侧视横截面图和俯视横截面图。
图10c-10d分别是图10a-10b的在制造多级接触的方法中的一个后续步骤的侧视横截面图和俯视横截面图。
图10e-10f分别是图10a-10b的在制造多级接触的方法中的一个后续步骤的侧视横截面图和俯视横截面图。
图10g-10h分别是图10a-10b的在制造多级接触的方法中的一个后续步骤的侧视横截面图和俯视横截面图。
具体实施方式
将参照附图如下描述本发明的实施例。应理解,以下实施例的意图为描述本发明示例的实施例,而不是限制本发明。
单片三维存储器阵列是多个存储器级形成在一个例如半导体晶片的单衬底之上,而没有***衬底。术语“单片”指阵列的每一级的层直接沉积在该阵列的每一个下层的级的层上。相反地,二维阵列可以被分别形成然后被封装在一起以形成非单片存储器装置。例如,如在Leedy的题为“ThreeDimensional Structure Memory”的美国专利号5915167中,已通过在分立的衬底上形成存储器级并将该存储器级相互粘附来构造非单片堆叠存储器。在键合前可以减薄衬底或者将其从存储器级中移除。但是由于该存储器级一开始形成在分立的衬底上,因此这样的存储器不是真正的单片三维存储器阵列。
本发明的实施例涉及制造例如单片3D阵列的多级存储器阵列的接触的方法。在一个实施例中,多级存储器装置包括至少一个装置区域和至少一个接触区域,存储器单元(例如垂直NAND串180)位于该至少一个装置区域,多级接触位于该至少一个接触区域。如图3和4所示以及以下更详细的讨论,多级垂直NAND存储器阵列的控制栅的远端以台阶式构造布置。以此方式,通过从存储器阵列的上表面向下至台阶120蚀刻在四周的介电层中的开口130的阵列以及在该开口130中沉积接触金属以接触该台阶120,可以实现到单独控制栅极的电接触。在制作多级存储器阵列的控制栅级的接触的常规方法中,在暴露最深的台阶之前,会严重地过蚀浅的台阶。
本发明的其它实施例提供了单片三维存储器装置阵列,例如垂直NAND串的阵列。该NAND串垂直取向,从而至少一个存储器单元位于另一个存储器单元的上方。该阵列允许NAND装置的垂直定标,以提供每单位面积的硅或者其它半导体材料的更高密度存储器单元。
在一些实施例中,如图1A、2A和3所示,单片三维NAND串180包括半导体沟道1,该半导体沟道1具有至少一个端部分,该端部分基本垂直于衬底100的主平面100a延伸。例如,如图1A和2A所示,该半导体沟道1可以具有柱形形状,并且整个柱形的半导体沟道基本垂直于衬底100的主平面100a延伸。在这些实施例中,如图1A和2A所示,该装置的源/漏电极可以包括提供在该半导体沟道1的下方的下电极102和形成在该半导体沟道1的上方的上电极202。或者,如图3所示,该半导体沟道1可以具有U型管道的形状。该U形管道形状的半导体沟道1的两个翼部分1a和1b可以基本垂直于该衬底100的主平面100a,并且该U形管道形状半导体沟道1的连接该两个翼部分1a和1b的连接部分1c基本平行于衬底100的主平面100a延伸。在这些实施例中,源极或者漏极区域之一区域2021从上方接触该半导体沟道1的第一翼部分,而源极或者漏极区域的另一个区域2022从上方接触该半导体沟道1的第二翼部分。可选的体接触电极(未示出)可以设置在衬底100中,以提供从下方接触该半导体沟道1的连接部分的体接触。该NAND串的选择栅极(SG)或者存取晶体管如图3所示。在如图3示出的实施例中,可以通过源线(SL)连接相邻NAND串的源区域2022,而可以通过位线(BL)连接相邻NAND串的漏区域2021。在该U型的实施例中,狭缝210分开该U形管道形状的两个翼部分1a和1b。可以用介电材料填充该狭缝210。
在一些实施例中,如图2A-2B所示,半导体沟道1可以是被填充的结构。在一些另外的实施例中,如图1A-1B所示,半导体沟道1可以是中空的,例如是填充有绝缘填充材料2的中空圆柱体。在这些实施例中,可以形成绝缘填充材料2以填充由该半导体沟道1围绕的中空部分。
衬底100可以是任何现有技术已知的半导体衬底,例如单晶硅、例如硅-锗或者硅-锗-碳的IV-IV族化合物、III-V族化合物、II-VI族化合物、在这类衬底上的外延层或者例如氧化硅、玻璃、塑料、金属或者陶瓷衬底的任何其它半导材料或者非半导材料。该衬底100可以包括制备在其上的集成电路,例如用于存储器装置的驱动电路。
任何合适的半导体材料可以用于半导体沟道1,例如硅、锗、锗化硅,或者例如III-V族,II-VI族的其它化合物半导体材料,或者导电或者半导电的氧化物等材料。半导体材料可以是非晶的、多晶的或者单晶的。该半导体沟道材料可以由任何合适的沉积方法形成。例如,在一个实施例中,该半导体沟道材料由低压化学气相沉积(LPCVD)形成。在一些其它的实施例中,该半导体沟道材料可以由通过再结晶初始沉积的非晶半导体材料形成的再结晶的多晶半导体材料形成。
绝缘填充材料2可以包括任何电绝缘材料,例如氧化硅、氮化硅、氮氧化硅或者其它高k绝缘材料。
如图1A至1B、2A至2B和3所示,该单片三维NAND串还包括多个控制栅极(CG)3。该控制栅电极3可以包括具有带状的部分,该部分基本平行于衬底100的主平面100a延伸。该多个控制栅电极3包括位于第一装置级(例如,装置级A)中的至少一个第一控制栅电极3a和位于第二装置级(例如装置级B)中的第二控制栅电极3b,该第二装置级位于该衬底100的主平面100a的上方和该装置级A的下方。该控制栅极的材料可以包括现有技术已知的任何一种或者多种合适的导电或者半导体控制栅极材料,例如掺杂多晶硅、钨、铜、铝、钽、钛、钴、氮化钛或者它们的合金。例如,在一些实施例中,优选多晶硅以便容易处理。
阻挡介电体7位于与控制栅极3相邻或者被其围绕。该阻挡介电体7可以包括位于与该多个控制栅电极3的相应的一个接触的多个阻挡介电部分,例如如图1A-1B和图2A-2B所示,位于装置级A中的第一介电体部分7a和位于装置级B中的第二介电体部分7b分别与控制电极3a和3b接触。或者,如图3所示,阻挡介电体7可以是连续的。
单片三维NAND串也可以包括多个分离的电荷储存部分9,每一个电荷储存部分9位于该阻挡介电体7和该沟道1之间。类似地,该多个分离电荷储存部分9包括位于装置级A中的至少一个第一分离电荷储存部分9a和位于装置级B中的第二分离电荷储存部分9b。或者,如图3所示,该电荷储存部分可以是连续的。也就是说,该电荷储存部分可以包括在连续电荷储存层的局部区域。
单片三维NAND串的隧道介电体11位于该多个分离电荷储存部分9的每一个和该半导体沟道1之间。该隧道介电体11可以包括多个阻挡介电部分11或者介电材料的连续层。
该阻挡介电体7和隧道介电体11可以独立地选自任何一个或者更相同或者不同的绝缘材料,例如氧化硅、氮化硅、氮氧化硅或者其它高k介电材料。
该电荷储存部分9可以包括分离或者连续的导体(例如,金属或者金属合金,例如钛、铂、钌、氮化钛、氮化铪、氮化钽、氮化锆或者金属硅化物,例如硅化钛、硅化镍、硅化钴,或者它们的组合)或者半导体(例如,多晶硅)浮置栅、导电纳米颗粒或者分离或者连续的电荷储存介电体(例如,氮化硅或者其它介电材料)结构。例如,在一些实施例中,分离电荷储存部分9是分离电荷储存介电结构,其每一个包括位于相应的蛤形阻挡介电部部分7中的氮化物结构,其中氧化硅阻挡介电部分7、氮化物结构9和氧化硅隧道介电体11形成该NAND串的氧化物-氮化物-氧化物的分离电荷储存结构。或者,可以使用多晶硅浮置栅极。
图4是示出常规垂直NAND存储器装置的横截面的扫描电子显微镜(SEM)的图像。如图4所示,接触132从接触区域134的顶表面延伸至控制栅极3的栅电极台阶120。如以下更详细的讨论,通过用例如铜或者铝或者它们的硅化物的导电材料填充形成在电绝缘(介电)材料124中的过孔,来制造接触132。为形成如图4所示的台阶图案,构造该控制栅电极3,从而第一导电层(例如在层的堆叠中的下层)包括横向延伸超过第二导电层(例如,在该堆叠中更高的层)的一部分。接触开口包括延伸至该第一导电层(例如,120a)的第一部分的第一接触开口(例如,图7中的130A)和延伸至该第二导电层(例如,120b)的上表面的第二接触开口(例如,图7中的130B)。例如,该第一导电层(例如,120a)可以是第一控制栅电极3的一部分,从装置区域延伸至接触区域134;并且该第二导电层(例如,120b)可以是第二控制栅电极3的一部分,从装置区域延伸至接触区域134。
图5示出了在使用制造上述图4讨论的多级接触的常规方法中的浅侧的问题。在常规方法中,控制栅台阶120覆盖有堆叠的介电(电绝缘)材料层。第一介电层是共形的蚀刻终止层122。该共形的蚀刻终止层122可以由例如氮化硅的任何合适的材料制成。该共形的蚀刻终止层122覆盖有由不同于层122的材料制成的第二介电层124。该第二介电材料可以由包括例如氧化硅(例如,SiO2)的氧化物的任何合适的材料制成。该第二介电层124不是共形的。也就是说,介电层124的厚度(h1,h2,h3,h4…hi)随着每一个台阶120而变化,从而该第二介电层124的上表面124a与衬底100的距离在所有台阶120中是相同的。第三介电层,即牺牲阻挡层126,沉积在该第二介电层124的上方。该牺牲阻挡层126可以由任何合适的材料制成,例如氮化硅(例如,优选与共形的蚀刻终止层122相同但与第二介电层124不相同的材料)。之后,第四介电层128沉积在该牺牲阻挡层126上。第四介电层128可以由包括例如氧化硅(例如,SiO2)的氧化物的任何合适的材料制成。
为制造控制栅极台阶120的接触,从该第四介电层128的顶表面128a,穿过该第四介电层128、该牺牲阻挡层126和该第二介电层124,蚀刻开口130A-130E。一般地,在第一蚀刻步骤中非选择性地蚀刻(即,用以基本相同的速率蚀刻所有材料的蚀刻剂蚀刻)该第四介电层128和该牺牲阻挡层126。然后选择性地蚀刻(即,用蚀刻一种材料(例如,第二介电材料124)基本比下层的材料(例如,蚀刻终止层122)更快(例如,2-10倍或者更快)的蚀刻剂蚀刻),从而开口在该蚀刻终止层122上停止。
然而,当蚀刻开口130A-130E时,常见的是较浅的开口(例如,130E、130D、130C)先于较深的开口(例如,130A)穿过蚀刻终止层122,到达该蚀刻终止层122。随着级(台阶)数目的增加,这尤其成为问题。不限制在例如多级NAND装置的多级存储器装置中的级的数目,其可以包括,例如2至256级,例如4至128级,例如8至64级,例如16至32级。通过将例如Cu、Al、它们的合金、或者硅化物(例如,Ti、Ni或者Co硅化物)的导电材料沉积在开口130A-130E中,完成接触。
图6和7是制造多级接触的第一实施例方法的示例说明。在该实施例中,控制栅台阶120覆盖有介电材料堆叠,包括:如上描述的蚀刻终止层122、第二介电层124、牺牲阻挡层126和第四介电层128。然而,与图5的常规的堆叠相反,该第二介电层124是共形的层。也就是说,该第二介电层124的厚度(h1,h2,h3,h4…hi)对于所有的台阶120基本相同(例如,h1≈h2≈h3≈h4≈hi),并且该第二介电层124的顶表面124a的形状跟随台阶120。此外,在该实施例中,牺牲阻挡层126也优选是共形的(例如,对于所有的台阶120,厚度相同)。优先地,层122和126由相同的第一材料制成,而层124和128由不同于该第一材料的相同的第二材料制成。在一个实施例中,该蚀刻终止层122和该牺牲阻挡层126由例如氮化硅的氮化物制成。也可以使用其它材料。该第二介电层124和该第四介电层128由例如氧化硅的氧化物制成。也可以使用其它介电材料。
在该实施例的第一步骤中,在第一蚀刻步骤701中,选择性地蚀刻(即,用蚀刻该第四介电层128的材料比蚀刻该牺牲阻挡层126的材料更快的蚀刻剂(具有第一蚀刻化学物))蚀刻该第四介电层128,穿过图7示出的在光致抗蚀剂或者其它掩模300,302中的孔。较深的开口(例如,130A,130B)停止在该牺牲阻挡层126上。较浅的开口(例如,130E,130D,130C)可以完全穿过该牺牲阻挡层126。然而,由于在该步骤中使用了选择性的蚀刻,当选择性的蚀刻剂到达该阻挡层126时,较浅的开口130E,130D,130C的蚀刻速率减慢,导致在该第一蚀刻步骤701中相对小的过蚀进第二介电层124。这样,第一蚀刻化学物可以用于使用该牺牲阻挡层126作为蚀刻终止,选择性地蚀刻多个接触开口130A至130E的第一部分,通过该第四介电层128。
在第二蚀刻步骤702中,选择性地蚀刻(即,用蚀刻该牺牲阻挡层126的材料比该第二介电层124的材料更快的蚀刻剂蚀刻)在较深开口130A,130B中的阻挡层126。当较深开口130A,130B到达该第二介电层124时,停止蚀刻。由于该第二蚀刻步骤702也使用了选择性的蚀刻,相对于将牺牲阻挡层126从较深的开口130A,130B的去除,在该第二介电层124中的浅开口130E,130D,130C的继续的蚀刻相对慢。优选地,所有的开口130A-130E停止在该第二介电层124中。这样,第二蚀刻化学物可以用于使用该第二介电层124作为蚀刻终止,选择性地蚀刻多个接触开口130A-130E的第二部分,穿过该牺牲阻挡层126。
在第三蚀刻步骤703中,选择性地蚀刻(例如,用蚀刻该第二介电层124的材料比该蚀刻终止层122的材料更快的蚀刻剂蚀刻)该第二介电层124。当该第二介电层124从较深开口130A,130B去除时(即,当到达该蚀刻终止层122时),停止蚀刻。作为使用共形的第二介电层124和共形的牺牲阻挡层126连同多个选择性蚀刻步骤的结果,最小化了最后蚀刻的深度的差别。可以形成较深的开口130A,130B,而不用穿过该蚀刻终止层122到达在浅开口130E,130D,130C中的控制栅极台阶120。这样,第三蚀刻化学物可以用于使用该共形的蚀刻终止层122为蚀刻终止,选择性地蚀刻接触开口130A-130E的第三部分,穿过该第二介电层124。当蚀刻完成到最深的台阶120e上方的蚀刻终止层时,在最浅的台阶120a上的蚀刻终止层122没有被穿透。
可以执行第四蚀刻步骤以去除在开口130A-130E中的该蚀刻终止层122,从而从第四介电层128的顶表面128a到控制栅极台阶120提供过孔。这样,第四蚀刻化学物可以用于选择性地蚀刻接触开口130A-130E的第四部分,穿过该共形的蚀刻终止层122,到达导电层120。
在一个实施例中,该第一蚀刻化学物和第三蚀刻化学物是相同的,该第二蚀刻化学物和第四蚀刻化学物是相同的,并且第一蚀刻化学物和第二蚀刻化学物不相同。用于氧化硅(例如,层124和128)的选择性蚀刻的选择率可以是用于氮化硅(例如,层122,126)的选择性蚀刻的选择率的13-15倍,而用于氮化硅的选择性蚀刻的选择率可以是用于氧化硅的选择性蚀刻的选择率的4-6倍。
在一个实施例中,该共形的蚀刻终止层122、该第二介电层124和该牺牲阻挡层126的每一个具有基本均匀的厚度,并且布置为在接触区域134中的该多个导电层120的上方的台阶图案。该第四介电层128具有可变的厚度和基本平面的上表面128a。该第四介电层128在该第一导电层的第一部分(例如,台阶128e)的上方比在该第二导电层(例如,台阶120d)的上方更厚。最浅的台阶120a位于在蚀刻方向中距离该第四介电层128的顶表面128a最短的距离。最深的台阶120e位于在该蚀刻方向中距离该第四介电层128的顶表面128a最长的距离。
如上讨论的,可以通过将例如Cu、Al、它们的合金或者硅化物(例如,Ti、Ni或者Co硅化物)的导电材料沉积在开口130A-130E中来形成接触132A-132E。例如,形成在第一接触开口130A中的第一导电接触132A和在第二接触开口130B中的第二导电接触132B(其中该第一导电接触132A比该第二导电接触132B延伸得更深)。可以形成多个导电接触132,其中该多个导电接触132的每一个位于该多个接触开口130的相应的一个中,并且每一个导电接触132与该多个导电层120的对应的一个电接触。
图8示出了根据一个实施例,该蚀刻终止层122的厚度损耗作为该共形的第二介电层124的厚度的函数。在这些模拟中,牺牲阻挡层126的厚度固定在150nm,并且孔130A和130E的深度分别为2480nm和780nm。图8示出了对于共形的第二介电层124的厚度范围约为275-630nm,在浅的开口中的蚀刻终止层122的损耗保持不变(小于30nm,例如25-29nm)。更厚的共形的第二介电层124的使用导致来自较深的开口的蚀刻终止层122的材料损耗的增加。然而,来自较深的开口的损耗总是小于来自浅开口的材料损耗(例如,损耗的差值小于20nm,例如小于12-19nm)。这样,牺牲阻挡层126可以至少为150nm厚,例如15-250nm厚。第二介电层124可以为275-630nm厚。
图9a和9b示出了对于(a)第二共形层的厚度为600nm以及对于(b)第二共形层的厚度为400nm,该蚀刻终止层122的厚度损耗作为该牺牲阻挡层126的厚度的函数。如图中所示,对于浅开口,蚀刻终止层122的厚度损耗随着牺牲阻挡层126的厚度增加而减小。此外,在深开口中的蚀刻终止层122的厚度损耗对牺牲阻挡层126的厚度不敏感。
图10a-10h示出了根据另一个实施例制造多级接触的方法。图10a、10c、10e和10g是示出该方法中步骤的侧视横截面图,而图10b、10d、10f和10h分别是与图10a、10c、10e和10g相对应的俯视横截面图。依次执行图10a-10h示出的步骤以制造图1和2示出的装置结构。也就是说,在工艺过程中装置上制造多极接触。
多级接触区域包括构造为台阶图案120的多个导电层。在该实施例中的多级接触区域还包括位于该导电层120上方的电绝缘层(例如,第二介电层124)。该多级接触区域还可以选择性地包括位于该导电层120和该电绝缘层124之间的蚀刻终止层122。在此实施例中,可以省略牺牲阻挡层126和第四介电层128。具有多个开口304A-304E的掩模300(例如,硬掩模,例如氧化硅、氮化硅、多晶硅等的一层或者多层)位于该电绝缘层124的上方。减薄层302(例如,光致抗蚀剂或者宽度和厚度可以由蚀刻或者灰化减薄的其它材料)位于该掩模300的上方。
在图10a和10b中示出的非限制性的实施例中,随着位于最深台阶120上方的最大直径的开口304A到位于最浅开口304E上方的最小直径的开口304e,开口304A-304E的直径逐渐减小。这是有利的,因为蚀刻在较大直径的开口中比在较小直径的开口中进行得更快。这样,可以通过使用不同直径的开口,实施对于该蚀刻工艺的附加控制。如示出的,多级接触区域包括五个级120。然而,如上所讨论的,没有限制在例如多级NAND装置的多级存储器装置中的级数目,并且其可以包括,例如2至256级,例如4至128级,例如8至64级,例如16至32级。
如图10a和10b所示,该方法包括蚀刻或者部分灰化减薄层302以降低其厚度和宽度,从而暴露在该掩模300中的第一开口304A。其它的开口304B至304E保持由厚度/宽度降低的减薄层302覆盖。如图10c-10d所示,可以蚀刻暴露在该第一开口304A中的电绝缘材料124,以形成在该电绝缘材料124中的第一接触开口130A的一部分。然后,如图10e和10f所示,可以蚀刻或者部分灰化减薄层302以降低其厚度和宽度,从而暴露在该掩模300中的第二开口304B。如图10g至10h所示,可以蚀刻暴露在该第一和第二开口304A,304B中的电绝缘材料124,以形成在该电绝缘材料124中的第二接触开口130B的一部分和进一步延伸接触开口130A。然后可以重复该蚀刻和减薄步骤直到形成对于每一个台阶120的在该电绝缘材料124(如果示出,还有层122)中的接触开口130A-130E。例如,还可以蚀刻或者灰化该减薄层302以减小其厚度和宽度,从而暴露在该掩模300中的第三开口并且蚀刻暴露在该第一和第二开口130A,130B中的电绝缘材料124的一部分,以形成在该电绝缘材料中的第二接触开口130A的第一部分和第一接触开口130A的第二部分。该第一接触开口130A比该第二接触开口130B更深。在形成所有的开口130A-130E之后,可以在该开口130A-130E中沉积例如Cu、Al、它们的合金或者硅化物的导电材料,以形成每个台阶的接触132。该方法可以包括连续蚀刻减薄层302直到暴露在该掩模中的所有的多个开口130A至130E,并且蚀刻多个接触开口的相应一个穿过在掩模300中的每一个开口,到达该多个导电层120a-120e。
在一个实施例中,在相同的蚀刻步骤中,可以使用相同的蚀刻化学物,同时蚀刻该电绝缘材料124和该减薄层302。在另一个实施例中,在不同的蚀刻步骤中,使用不同的蚀刻化学物,蚀刻该电绝缘材料124和该减薄层302。
尽管前述参考特定的优选的实施例进行了描述,但是应理解,本发明并不受限于此。本领域普通技术人员可以对公开的实施例进行各种修改,并且这些修改意图落在本发明的范围内。本文引用的所有的出版物、专利申请和专利的全部内容通过引用并入本文。
Claims (24)
1.一种制造多级接触的方法,包括:
提供工艺过程中多级装置,包括至少一个装置区域和至少一个接触区域,该接触区域包括构造为台阶图案的多个导电层;
在该多个导电层的上方形成共形的蚀刻终止层;
在该蚀刻终止层的上方形成第一电绝缘层;
在该第一电绝缘层的上方形成共形的牺牲层;
在该牺牲层的上方形成第二电绝缘层;以及
蚀刻多个接触开口,穿过在该接触区域中的该蚀刻终止层、该第一电绝缘层、该牺牲层和该第二电绝缘层,到达该多个导电层。
2.如权利要求1所述的方法,其中:
该多个导电层包括至少一个第一导电层和第二导电层,该至少一个第一导电层位于衬底上方的第一装置级中,该第二导电层位于该衬底上方比第一装置级更高的第二装置级中;
该第一导电层包括第一部分,该第一部分横向延伸通过该第二导电层,以形成该台阶图案的至少一部分;以及
该多个接触开口包括第一接触开口和第二接触开口,该第一接触开口延伸至该第一导电层的该第一部分,该第二接触开口延伸至该第二导电层的上表面。
3.如权利要求2所述的方法,还包括在该第一接触开口中形成第一导电接触和在该第二接触开口中形成第二导电接触,其中该第一导电接触比该第二导电接触延伸得更深。
4.如权利要求3所述的方法,其中该蚀刻的步骤包括:
使用第一蚀刻化学物,使用该牺牲层作为蚀刻终止,选择性地蚀刻该多个接触开口的第一部分,穿过该第二电绝缘层;
使用第二蚀刻化学物,使用该第一电绝缘层作为蚀刻终止,选择性地蚀刻该多个接触开口的第二部分,穿过该牺牲层;
使用第三蚀刻化学物,使用该共形的蚀刻终止层作为蚀刻终止,选择性地蚀刻该多个接触开口的第三部分,穿过该第一电绝缘层;
使用第四蚀刻化学物,选择性地蚀刻该多个接触开口的第四部分,穿过该共形的蚀刻终止层,到达该多个导电层。
5.如权利要求4所述的方法,其中:
该第一蚀刻化学物和该第三蚀刻化学物是相同的;
该第二蚀刻化学物和该第四蚀刻化学物是相同的;
该第一蚀刻化学物和该第二蚀刻化学物是不同的;
该共形的蚀刻终止层和该共形的牺牲层包括相同的材料;
该第一绝缘层和该第二电绝缘层包括相同的材料;以及
该共形的牺牲层包括与该第一电绝缘层不同的材料。
6.如权利要求5所述的方法,其中:
该共形的蚀刻终止层和该共形的牺牲层包括相同的氮化物材料;以及
该第一电绝缘层和该第二电绝缘层包括相同的氧化物材料。
7.如权利要求6所述的方法,其中该蚀刻终止层包括氮化硅,该第一电绝缘层包括氧化硅,该牺牲层包括氮化硅,并且该第二电绝缘层包括氧化硅。
8.如权利要求4所述的方法,其中:
该共形的蚀刻终止层、该第一电绝缘层和该牺牲层的每一个具有基本均匀的厚度,并且每一个布置为在该接触区域中的该多个导电层的上方的台阶图案;
该第二电绝缘层具有可变的厚度和基本平面的上表面;
该第二电绝缘层在该第一导电层的第一部分上方比在该第二导电层的上方更厚;
最浅的台阶位于在蚀刻方向中距离该第二电绝缘层的顶表面最短的距离处;
最深的台阶位于在蚀刻方向中距离该电绝缘层的顶表面最大的距离处;以及
当在该最深的台阶上方的蚀刻终止层的蚀刻完成时,在该最浅的台阶上的蚀刻终止层没有穿过。
9.如权利要求2所述的方法,其中:
该装置包括垂直的NAND装置;
该装置区域包括:
多个半导体沟道,其中该多个半导体沟道的每一个的至少一个端部分基本垂直于该衬底的主表面延伸;
多个电荷储存区域,每个电荷储存区域与该多个半导体沟道的相应一个相邻设置;以及
多个控制栅电极,具有带状,基本平行于该衬底的该主表面延伸,其中该多个控制栅电极包括至少一个在该第一装置级中的第一控制栅电极和在该第二装置级中的第二控制栅电极;
该第一导电层包括该第一控制栅极的一部分,从该装置区域延伸至该接触区域;以及
该第二导电层包括该第二控制栅电极的一部分,从该装置区域延伸至该接触区域。
10.一种制造多级接触的方法,包括:
提供工艺过程中的多级装置,该多级装置包括至少一个装置区域和至少一个接触区域,该接触区域包括:构造为台阶图案的多个导电层、位于该导电层上方的电绝缘层、位于该绝缘层上方的具有多个开口的掩模,和位于该掩模上方的减薄层;
蚀刻该减薄层以减小其厚度和宽度,从而暴露在该掩模中的第一开口;
蚀刻暴露在该第一开口中的电绝缘材料的一部分,以在该电绝缘材料中形成第一接触开口的一部分;
进一步蚀刻该减薄层以减小其厚度和宽度,从而暴露在该掩模中的第二开口。
11.如权利要求10所述的方法,其中蚀刻该电绝缘材料的一部分的步骤与进一步蚀刻该减薄层的步骤同时发生。
12.如权利要求11所述的方法,还包括继续蚀刻减薄层以减小其厚度和宽度,从而暴露在该掩模中的第三开口和蚀刻暴露在该第一开口和该第二开口中的电绝缘材料的一部分,以在该电绝缘材料中形成该第二接触开口的第一部分和该第一接触开口的第二部分,其中该第一接触开口比该第二接触开口更深。
13.如权利要求12所述的方法,还包括继续蚀刻该减薄层直到暴露在该掩模中的所有的该多个开口,并且蚀刻该多个接触开口的对应的一个,穿过在该掩模中的每一个开口,到达该多个导电层。
14.如权利要求13所述的方法,其中:
该多个导电层包括至少一个第一导电层和第二导电层,该至少一个第一导电层位于衬底上方的第一装置级中,该第二导电层位于该衬底上方比第一装置级更高的第二装置级中;
该第一导电层包括第一部分,横向延伸通过该第二导电层,以形成该台阶图案的至少一部分;以及
该多个接触开口包括第一接触开口和第二接触开口,该第一接触开口延伸至该第一导电层的该第一部分,该第二接触开口延伸至该第二导电层的上表面。
15.如权利要求14所述的方法,还包括在该第一接触开口中形成第一导电接触和在该第二接触开口中形成第二导电接触,其中该第一导电接触比该第二导电接触延伸得更深。
16.如权利要求15所述的方法,其中:
该装置包括垂直NAND装置;
该装置区域包括:
多个半导体沟道,其中多个半导体沟道的每一个的至少一个端部分基本垂直于该衬底的主表面延伸;
多个电荷储存区域,每个电荷储存区域与该多个半导体沟道的相应的一个相邻设置;以及
多个控制栅电极,具有带状,基本平行于该衬底的该主表面延伸,其中该多个控制栅电极包括在该第一装置级中的至少一个第一控制栅电极和在该第二装置级中的第二控制栅电极;
该第一导电层包括该第一控制栅电极的一部分,从该装置区域延伸至该接触区域;以及
该第二导电层包括该第二控制栅电极的一部分,从该装置区域延伸至该接触区域。
17.如权利要求10所述的方法,其中该减薄层包括光致抗蚀剂层并且该掩模包括硬掩模。
18.一种多级装置,包括:
至少一个装置区域和至少一个接触区域,该至少一个接触区域具有多个堆叠的导电层,其中该导电层形成在该接触区域中的台阶图案;
位于该导电层的上方的共形的蚀刻终止层;
位于该蚀刻终止层的上方的第一电绝缘层;
位于该第一电绝缘层的上方的共形的牺牲层;
位于该牺牲层的上方的第二电绝缘层;
多个接触开口,延伸穿过在该接触区域中的该蚀刻终止层、该第一电绝缘层、该牺牲层和该第二电绝缘层,到达该多个导电层;以及
多个导电接触,其中该多个导电接触的相应的每一个位于该多个接触开口的相应的一个中,以及每个导电接触与该多个导电层的相应的一层电接触。
19.如权利要求18所述的方法,其中:
该多个导电层包括至少一个第一导电层和第二导电层,该至少一个第一导电层在位于衬底上方的第一装置级中,该第二导电层位于该衬底上方比第一装置级更高的第二装置级中;
该第一导电层包括第一部分,横向延伸通过该第二导电层,以形成该台阶图案的至少一部分;
该多个接触开口包括第一接触开口和第二接触开口,该第一接触开口延伸至该第一导电层的该第一部分,该第二接触开口延伸至该第二导电层的上表面;
该多个导电接触的第一导电接触位于该第一接触开口中;
该多个导电接触的第二导电接触位于该第二接触开口中;以及
该第一导电接触比该第二导电接触延伸得更深。
20.如权利要求19所述的方法,其中:
该共形的蚀刻终止层和该共形的牺牲层包括相同的材料;
该第一电绝缘层和该第二电绝缘层包括相同的材料;以及
该共形的牺牲层包括不同于该第一电绝缘层的材料。
21.如权利要求20所述的方法,其中:
该共形的蚀刻终止层和该共形的牺牲层包括相同的氮化物材料;以及
该第一绝缘层和该第二电绝缘层包括相同的氧化物材料。
22.如权利要求21所述的方法,其中该蚀刻终止层包括氮化硅,该第一电绝缘层包括氧化硅,该牺牲层包括氮化硅,以及该第二电绝缘层包括氧化硅。
23.如权利要求19所述的方法,其中:
该装置包括垂直的NAND装置;
该装置区域包括:
多个半导体沟道,其中多个半导体沟道的每一个的至少一个端部分基本垂直于该衬底的主表面延伸;
多个电荷储存区域,每个电荷储存区域与该多个半导体沟道的相应的一个相邻设置;以及
多个控制栅电极,具有带状,基本平行于该衬底的该主表面延伸,其中该多个控制栅电极包括在该第一装置级中的至少一个第一控制栅电极和在该第二装置级中的第二控制栅电极;
该第一导电层包括该第一控制栅电极的一部分,从该装置区域延伸至该接触区域;以及
该第二导电层包括该第二控制栅电极的一部分,从该装置区域延伸至该接触区域。
24.如权利要求19所述的方法,其中:
该共形的蚀刻终止层、该第一电绝缘层和该牺牲层的每一个具有基本均匀的厚度,并且每一个布置为在该接触区域中的该多个导电层的上方的台阶图案;
该第二电绝缘层具有可变的厚度和基本平面的上表面;
该第二电绝缘层在该第一导电层的第一部分上方比在该第二导电层的上方更厚。
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CN112310108A (zh) * | 2019-08-02 | 2021-02-02 | 爱思开海力士有限公司 | 具有三维结构的半导体存储器装置及其制造方法 |
CN112614842A (zh) * | 2019-10-04 | 2021-04-06 | 爱思开海力士有限公司 | 存储器设备及其制造方法 |
CN112635540A (zh) * | 2019-10-08 | 2021-04-09 | 无锡华润上华科技有限公司 | Ldmos器件及其制备方法 |
CN113192967A (zh) * | 2020-06-11 | 2021-07-30 | 长江存储科技有限责任公司 | 半导体结构及其制备方法 |
CN113192967B (zh) * | 2020-06-11 | 2023-04-28 | 长江存储科技有限责任公司 | 半导体结构及其制备方法 |
WO2022016455A1 (en) * | 2020-07-23 | 2022-01-27 | Intel Corporation | Method and apparatus to mitigate word line staircase etch stop layer thickness variations in 3d nand devices |
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WO2013176960A2 (en) | 2013-11-28 |
US20130313627A1 (en) | 2013-11-28 |
US8828884B2 (en) | 2014-09-09 |
KR101941329B1 (ko) | 2019-01-22 |
KR20150079495A (ko) | 2015-07-08 |
CN104396004B (zh) | 2018-01-30 |
WO2013176960A3 (en) | 2014-02-20 |
US8994099B2 (en) | 2015-03-31 |
US9305935B2 (en) | 2016-04-05 |
US20140367759A1 (en) | 2014-12-18 |
US20150179663A1 (en) | 2015-06-25 |
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