CN103839943A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN103839943A
CN103839943A CN201310604699.8A CN201310604699A CN103839943A CN 103839943 A CN103839943 A CN 103839943A CN 201310604699 A CN201310604699 A CN 201310604699A CN 103839943 A CN103839943 A CN 103839943A
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region
diode
groove
layer
diode region
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CN103839943B (zh
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R.埃斯特夫
D.佩特斯
R.希米尼克
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本发明涉及半导体器件。一种半导体器件包括集成在半导体主体中的至少两个器件单元。每个器件单元包括：漂移区、源极区、布置在源极区和漂移区之间的漏极区、二极管区、二极管区和漂移区之间的pn结、和具有第一侧壁、与第一侧壁相对的第二侧壁以及底部的沟槽。主体区邻接第一侧壁，二极管区邻接第二侧壁，并且pn结邻接沟槽的底部。每个器件单元进一步包括栅电极，所述栅电极布置在沟槽中并通过栅极电介质与主体区、二极管区和漂移区介电绝缘。所述至少两个器件单元的二极管区在半导体主体的横向方向上远离。

Description

半导体器件
技术领域
本发明的实施例涉及半导体器件，特别涉及包括垂直晶体管器件和与该晶体管器件并联连接的二极管的半导体器件。
背景技术
功率晶体管，是具有多达几百伏特的电压阻断能力且具有高电流额定值的晶体管，可以被实施为垂直MOS沟槽晶体管。在这种情况下，晶体管的栅电极可以布置在沟槽中，该沟槽在半导体主体的垂直方向上延伸。栅电极与晶体管的源极区、主体区和漂移区介电绝缘并且在半导体主体的横向方向上邻近主体区。漏极区通常邻接漂移区，并且源电极连接到源极区。
在许多应用中，期望具有与晶体管的负载路径（漏极-源极路径）并联连接的二极管。出于这个目的可以使用晶体管的集成的体二极管。体二极管由主体区和漂移区之间的pn结形成。为了将体二极管与晶体管的负载路径并联连接，可以简单地将主体区电连接到源电极。然而，体二极管可以具有比在一些应用中所期望的更低的电流额定值。
可以利用传统半导体材料（诸如硅（Si）或碳化硅（SiC））来实施功率晶体管。归因于SiC的特定属性，对SiC的使用允许实施具有比Si更高的电压阻断能力（以给定的导通电阻）的功率晶体管。然而，高阻断电压导致半导体主体中、具体在主体区和漂移区之间的pn结处的高电场。通常存在接近该pn结布置的栅电极的区段和栅极电介质的区段。当栅极电介质的介电强度对于晶体管器件的期望电压阻断能力来说不足时，可能发生问题。在这种情况下，栅极电介质可能提早击穿。
存在下述需要：提供具有晶体管器件和二极管的半导体器件，其中保护晶体管的栅电极免于高电场，并且其中二极管具有高电流额定值和低损耗。
发明内容
根据实施例，一种半导体器件包括集成在半导体主体中的至少两个器件单元。每个器件单元包括：漂移区、源极区、布置在源极区和漂移区之间的漏极区、二极管区、二极管区和漂移区之间的pn结、和具有第一侧壁、与第一侧壁相对的第二侧壁以及底部的沟槽，其中主体区邻接第一侧壁，二极管区邻接第二侧壁，并且pn结邻接沟槽的底部。每个器件单元进一步包括栅电极，所述栅电极布置在沟槽中并且通过栅极电介质与主体区、二极管区和漂移区介电绝缘。所述至少两个器件单元的二极管区在半导体主体的横向方向上远离。
根据另一个实施例，描述了一种生产半导体器件的方法。所述方法包括：提供半导体主体，所述半导体主体具有漂移区层、邻接漂移区层的主体区层、和邻接主体区层且形成所述半导体主体的第一表面的源极区层；形成至少两个二极管区，使得每个二极管区从第一表面延伸通过源极区层和主体区层到漂移区层中，其中每个二极管区和漂移区层形成一个pn结；以及形成至少两个沟槽，每个沟槽具有第一侧壁、与第一侧壁相对的第二侧壁以及底部，使得每个沟槽在一个侧壁上邻接主体区层，在第二侧壁上邻接一个二极管区以及在底部上邻接一个pn结。所述方法进一步包括：在每个沟槽中形成栅电极和栅极电介质，所述栅极电介质将所述栅电极与所述半导体主体介电绝缘。
附图说明
下面参照附图来解释示例。附图用于图示基本原理，以便仅图示理解基本原理所必需的方面。附图不是按比例绘制的。在附图中，相同的附图标记表示类似的特征。
图1图示了根据第一实施例的半导体器件的垂直横截面视图。
图2图示了图1的半导体器件的一个实施例的水平横截面视图。
图3图示了在与图1中图示的截面不同的截面中图2的半导体器件的垂直横截面视图。
图4（包括图4A到4J）图示了根据一个实施例的用于生产半导体器件的方法。
图5（包括图5A和5B）图示了用于生产图4B中图示的半导体器件结构的方法的一个实施例。
具体实施方式
在下面的具体实施方式中，对附图进行了参照，附图形成具体实施方式的一部分，并且在附图中通过图示的方式示出了在其中可实践本发明的具体实施例。
图1图示了半导体器件、具体地垂直半导体器件、并且更具体地具有集成的二极管的垂直晶体管器件的垂直横截面视图。该半导体器件包括半导体主体100和集成在半导体主体100中的至少两个器件单元（晶体管单元）101、102。器件单元在下面还将被称为晶体管单元。在图1中，仅图示了两个器件单元101、102。然而，半导体器件可以包括集成在一个半导体主体100中的多于两个器件单元，诸如大约数十、数百、数千、数十万或甚至数百万器件单元。
在图1中，两个器件单元101、102用不同的附图标记来标记，而个体器件单元101、102的类似特征用类似的附图标记来标记。参照图1，每个晶体管单元101、102包括漂移区11、源极区12和主体区13。主体区13布置在源极区12和漂移区11之间。每个器件单元101、102进一步包括二极管区30和在二极管区30和漂移区11之间形成的pn结。在图1的实施例中，个体器件单元101、102共享漂移区11。也就是说，个体器件单元101、102-共同具有一个漂移区11。
参照图1，每个器件单元101、102进一步包括栅电极21，栅电极21布置在沟槽中并通过栅极电介质22与主体区13、二极管区30和漂移区11介电绝缘。每个器件单元101、102的具有栅电极21的沟槽具有第一侧壁1101、与第一侧壁1101相对的第二侧壁1102以及底部1103。每个器件单元101、102的主体区13邻接对应沟槽的第一侧壁1101，二极管区30邻接对应沟槽的第二侧壁1102，并且漂移区11和二极管区30之间的pn结邻接对应沟槽的底部1103。
参照图1，一个器件单元（诸如器件单元101）的个体二极管区30从与相邻器件单元（诸如器件单元102）的源极区12和主体区13邻近的半导体主体100的第一表面101延伸到形成pn结的漂移区11中。电绝缘层（绝缘层）51覆盖第一表面101和栅电极21。绝缘层51具有接触开口52，在接触开口52处绝缘层51露出个体器件单元101、102的第二二极管区32和源极区12。源电极41形成在绝缘层51上和接触开口52中。源电极41通过绝缘层51与栅电极21电绝缘并将个体二极管区30和个体源极区12电连接到源极端子S（在图1中仅示意性地图示）或形成源极端子S。可选地，源电极41包括电接触二极管区30和源极区12的第一源电极层411以及电连接第一源电极层411的第二源电极层412。第二源电极层412连接到源极端子S或形成半导体器件的源极端子S。第一源电极层411包括例如钛（Ti）、铂（Pt）、镍合金等。第二电极层412包括例如铝（Al）、铜（Cu）等。
参照图1，半导体器件进一步包括邻接漂移区11的漏极区14。可选地，与漂移区11相同掺杂类型但在漂移区11中更高掺杂的场截止区（未图示）布置在漂移区11和漏极区14之间。漏极区14电连接到漏极端子D（在图1中仅示意性地图示）。个体器件单元101、102共享一个漏极区14。也就是说，存在个体器件单元101、102所共有的一个漏极区14。
通过使个体源极区12经由源电极41连接到源极端子S，通过共享漏极区14并使漏极区14连接到漏极端子D，以及通过使个体栅电极21电连接到公共栅极端子G，来并联连接个体器件单元101、102。在图1中仅示意性地图示了栅电极21与栅极端子G的连接。本文中下面参照图2和3来解释一种将栅电极21连接到栅极端子G的可能方式。
图1的半导体器件是具有集成二极管的MOS晶体管器件。该晶体管器件可以被实施为n型器件或p型器件。在n型器件中，源极区和漂移区11是n掺杂的，而主体区13是p掺杂的。在p型器件中，源极区12和漂移区11是p掺杂的，而主体区13是n掺杂的。该晶体管器件可以被实施为增强（常断（normally-off））型器件或耗尽（常通（normally-on））型器件。在增强型器件中，个体器件单元101、102的主体区13邻接栅极电介质22。在耗尽型器件中，存在沿着栅极电介质22的、与源极区12和漂移区11相同掺杂类型的沟道区15（在图1中以虚线图示）。每个器件单元101、102的沟道区15沿栅极电介质22从对应的源极区12延伸到漂移区11，并在晶体管器件关断时耗尽电荷载流子。可替代地，栅极电介质22包括固定电荷，当栅极驱动电压（栅极-源极电压）为零时，该固定电荷使得在主体区13中沿栅极电介质22生成导电沟道。
另外，晶体管器件可以被实施为MOSFET或IGBT。在MOSFET中，漏极区14具有与源极区12和漂移区11相同的掺杂类型，而在IGBT中，漏极区14具有与源极区12和漂移区11的掺杂类型互补的掺杂类型。在IGBT中，漏极区14也被称为集电极区。
二极管区30具有与主体区13相同的掺杂类型，该掺杂类型是与漂移区11的掺杂类型互补的掺杂类型。因为一个器件单元（诸如图1中的器件单元101）的二极管区30邻接相邻器件单元（诸如图1中的器件单元102）的主体区13，所以每个器件单元的主体区13通过相邻器件单元的二极管区30电连接到源电极41。可选地，每个二极管区30包括两个不同掺杂的半导体区，即，邻接漂移区11且与漂移区11形成pn结的第一区31和将第一区31电连接到源电极41的第二二极管区32。第二二极管区32（其在下面还将被称为接触区）具有高于第一区31的掺杂浓度。在图1的实施例中，一个器件单元（诸如图1中的器件单元101）的接触区32邻接对应沟槽的第二侧壁1102并将相邻器件单元（诸如图1中的器件单元102）的主体区13电连接到源电极41。
每个器件单元101、102的二极管区30与漂移区11和漏极区14形成二极管。在图1中还图示了该二极管的电路符号（图1中图示的电路符号的极性与n型半导体器件相关；在p型器件中，该极性反转）。在个体器件单元101、102的二极管区30和漂移区11之间形成的二极管并联连接，并与MOS晶体管的负载路径（漏极-源极路径）并联连接。MOS晶体管的漏极-源极路径是漏极端子D和源极端子S之间的内部路径。当具有第一极性的电压施加在MOS晶体管的漏极和源极端子D、S之间时，个体二极管反向偏置（阻断），而当具有第二极性的电压施加在漏极和源极端子D、S之间时，个体二极管正向偏置（导通）。在n型半导体器件中，当正电压施加在漏极和源极端子D、S之间时，二极管反向偏置，而当负电压施加在漏极和源极端子D、S之间（其在源极和漏极端子S、D之间为正电压）时，二极管正向偏置。个体二极管与晶体管单元的体二极管并联。体二极管是由个体器件单元101、102的主体区13和漂移区11形成的二极管。然而，不同于体二极管，可以与MOS晶体管的属性无关地较宽地调整二极管区30和漂移区11之间的二极管的属性。具体地，可以通过实施二极管区30以使得二极管区30和漂移区11之间的pn结具有相对较大的面积，将二极管区30和漂移区11之间的二极管实施为具有高电流额定值。
可以通过在漏极和源极端子D、S之间施加负载电压和通过将驱动电势施加到栅电极G，像传统MOS晶体管那样操作图1的半导体器件。参考n型半导体器件来简要地解释该操作原理。然而，该操作原理也适用于p型器件，其中，在p型器件中，下面解释的电压的极性必须反转。当在漏极和源极端子D、S之间施加反向偏置体二极管和附加二极管（个体器件单元101、102的二极管区30和漂移区11之间的二极管）的负载电压时，半导体器件处于正向操作模式中。在n型器件中，该电压是正电压。在正向操作模式中，可以通过对栅极端子G施加的驱动电势来接通和关断MOS晶体管。当对栅极端子G施加的驱动电势在源极区12和漂移区11之间的主体区13中生成导电沟道时，MOS晶体管接通（处于接通状态中），而当主体区13中的导电沟道被中断时，MOS晶体管关断（处于关断状态中）。接通或关断晶体管器件的驱动电势的绝对值依赖于晶体管器件的具体类型（增强型器件或耗尽型器件）。
当在漏极和源极端子D、S之间施加正向偏置体二极管和附加二极管的电压时，半导体器件处于反向操作模式中。在该操作模式中，仅可以通过负载电压的极性来控制半导体器件，而不可以通过对栅极端子G施加的驱动电势来控制半导体器件。
当半导体器件处于正向操作模式中时并且当半导体器件被关断时，二极管区30和漂移区11之间的pn结以及主体区13和漂移区11之间的pn结反向偏置，使得耗尽区在漂移区11中扩充。当负载电压增加时，耗尽区在漏极区14的方向上更深地扩充到漂移区11中。当负载电压增加并且耗尽区更深地扩充到漂移区11中时，pn结处的电场强度也增加。因为主体区13和第一漂移区11之间的pn结接近于栅极电介质22，所以当施加高负载电压时，即当出现高场强时，栅极电介质22可能被损坏。然而，在图1的半导体器件中，两个相邻器件单元101、102的二极管区30与漂移区11一起充当JFET（结型场效应晶体管）。该JFET在两个相邻二极管区30之间具有沟道区111。随着负载电压增加并且随着漂移区11的电势增加，JFET夹断沟道区111并防止在负载电压进一步增加时主体区13和漂移区11之间的pn结处的电场的场强进一步增加。在其处夹断JFET的沟道111的负载电压例如依赖于两个相邻二极管区30在半导体主体100的横向方向上的距离。半导体主体100的“横向方向”垂直于垂直方向并基本上平行于第一表面101，在该垂直方向上，漏极区14与主体区13和二极管区30分隔开。两个相邻二极管区30之间的该横向距离例如在0.5μm（微米）和2μm（微米）之间或在容纳栅电极21的沟槽的宽度的0.25倍和1.5倍之间。沟槽的“宽度”是第一和第二侧壁1101、1102之间的距离。在沟槽逐渐变细（tapered）的情况下，如图1的实施例中图示的那样，该宽度是第一和第二侧壁之间的最大距离。
每个器件单元101、102包括沟道区，该沟道区是主体区13沿栅极电介质22的区或者是可选的沟道区15（在图1中以虚线图示）。当晶体管器件处于接通状态中时，沿栅极电介质22的沟道区使电荷载流子能够从源极区12流动到漂移区11。每个器件单元101、102的二极管区30不与沟道区重叠。即，二极管区30和漂移区11之间的pn结邻接个体栅极沟槽的底部并且在沟道区的方向上不延伸超过栅极沟槽。因此，二极管区30不约束从沟道区到漏极区14的电荷载流子流动。
除了其它以外，半导体器件的电压阻断能力还依赖于二极管区30和漏极区14之间的距离。可以在制造过程中根据期望的电压阻断能力来调整该距离。作为经验法则，在SiC半导体主体100中，依照100V电压阻断能力，漏极区14和二极管区30之间的距离在0.8微米和1.0微米之间。
半导体主体100可以包括传统半导体材料，特别地，宽带隙半导体材料，诸如碳化硅（SiC）等。图1中图示的器件拓扑特别适合于利用SiC技术实施的半导体器件。当例如半导体主体100包括SiC时，栅极电介质22可以被实施为硅氧化物（SiO2）。SiO2的栅极电介质22在被暴露到可能在高电压器件中出现的高场强时可能遭受退化。在这样的器件中，当半导体器件被关断并且在漏极和源极端子D、S之间施加高负载电压时，由二极管区30和漂移区11形成的JFET高效地保护栅极电介质22。在反向操作模式中，直接连接到源电极41的附加二极管是与MOS晶体管的负载路径并联连接的具有低损耗的非常高效的二极管。
漂移区11的掺杂浓度例如在1E14cm-3和1E17cm-3之间。主体区13的掺杂浓度例如在5E16cm-3和5E17cm-3之间。源极区和漏极区12、14的掺杂浓度例如比1E19cm-3高。二极管区30的掺杂浓度例如在1E18cm-3和1E19cm-3之间。
参照图1，每个器件单元101、102的主体区13在第一侧壁1101处邻接对应的栅极沟槽。尤其当栅极沟槽具有逐渐变细的侧壁时，第一和第二侧壁1101、1102可以对应于半导体主体100的晶格的不同晶面。根据一个实施例，半导体主体100包括六边形SiC晶体，并且栅极沟槽具有逐渐变细的侧壁，使得第一侧壁1101对应于SiC晶体中的11-20平面。在这种情况下，个体沟道区以相对较低的电阻为特征。在该实施例中，第一侧壁1101与SiC半导体主体100的晶体的c轴对齐。c轴（六边形主轴）垂直于SiC晶体的生长面（0001平面）。在图1中未图示该生长面。沟槽的底部1103基本上平行于第一表面101。
沟槽110的第一侧壁1101和第一表面101之间的角度α（阿尔法）依赖于第一表面相对于生长面（0001平面）的定向。根据一个实施例，第一表面101相对于生长面倾斜，其中第一表面101和生长面之间的角度可以在1°和10°之间，特别地在2°和8°之间。在这种情况下，α在80°（90°- 10°）和89°（90°- 1°）之间，并且特别地在82°（90°- 8°）和88°（90°- 2°）之间。根据一个特定实施例，第一表面101和生长面之间的角度是4°，使得沟槽110的第一表面101和第一侧壁1101之间的角度α是86°。在SiC晶体中沿11-20平面存在高电荷载流子迁移率，使得第一侧壁1101与c轴的对齐导致主体区13中沿栅极电介质22的沟道区中的低电阻。
栅极沟槽可以是细长的沟槽，其中栅电极21可以连接到处于图1的垂直横截面视图中的视野之外的位置处的栅极端子电极。图2示出了包括细长栅极沟槽的、图1的半导体器件的一个实施例的水平横截面视图。图2图示了半导体主体100的三个不同水平层中的半导体器件的特征。在图2中，以点线图示了栅电极21和栅极电介质22。如可以从图2中看出的那样，具有栅电极21和栅极电介质22的栅极沟槽是细长的沟槽。具有可选接触区32的二极管区30和源极区12平行于栅极沟槽伸展。图2进一步图示了（以虚线）绝缘层51的接触开口52、53。参照图2，在源极区12和二极管区30（具体地，二极管区30的接触区32）上方存在第一接触开口52，并且在栅电极21上方存在第二接触开口53。第二开口53在半导体主体100的第一横向方向x上与第一开口52分隔开。在本实施例中，个体栅极沟槽和个体二极管区30在垂直于第一横向方向x的第二横向方向y上分隔。参照图1和2，源电极41在第一接触开口52所位于的那些区中覆盖绝缘层51，并在第一接触开口52中电连接到接触区32和源极区12。
栅极连接电极（栅极伸展部）42在第一横向方向x上与源电极41分隔开，并在布置了第二接触开口53的那些区中覆盖绝缘层51。栅极连接电极42在第二接触开口53中电连接到栅电极21。参照图2，源电极41和栅极连接电极42可以基本上平行。
图1中图示的垂直横截面视图对应于图2中图示的截面A-A中的垂直横截面视图。图3图示了图2中图示的截面B-B中的垂直横截面视图，其中截面B-B切割穿过栅极连接电极42和第二接触开口53。参照图3，绝缘层51将二极管区30和源极区12与栅极连接电极42分离，并且栅极连接电极42通过第二接触开口53电连接到栅电极21。
根据一个实施例，半导体器件包括连接到源极端子S的一个源电极41和连接到栅极端子G的一个栅极连接电极42。根据另一实施例（未图示），半导体器件包括各自连接到栅极端子G的若干栅极连接电极42和各自连接到源极端子S的若干源电极41，其中栅极连接电极42和源电极41基本上平行并在第一横向方向x上交替地布置。
下面参照图4A到4J来解释用于生产如本文中前面解释的半导体器件的方法的一个实施例。这些附图中的每一个示出了在该方法的各个方法步骤期间半导体主体100的垂直横截面视图。
参照图4A，该方法包括提供具有漂移区层111、邻接漂移区层111的主体区层113和邻接主体区层113的源极区层112的半导体主体100。源极区层112形成半导体主体100的第一表面101。半导体主体100进一步包括与主体区层113相对的、邻接漂移区层111的漏极区层114。可选地，与漂移区层111相同掺杂类型但比漂移区层111更高掺杂的场截止区层（未图示）布置在漏极层区114和漂移区层111之间。漂移区层111形成漂移区11，主体区层113形成主体区13，源极区层112形成源极区12，并且漏极区层114形成完成的半导体器件的漏极区14。个体半导体层111-114的掺杂类型和掺杂浓度对应于由这些个体半导体层形成的器件区的掺杂类型和掺杂浓度。本文中前面已解释了个体器件区的这些掺杂类型和掺杂浓度。
可以使用用于生产具有若干不同掺杂的半导体层的半导体主体100的传统技术来生产图4A的半导体主体100。根据一个实施例，生产半导体主体100包括：提供形成漏极区层114的半导体衬底；在漏极区层114上生长作为第一外延层的漂移区层111；在漂移区层111上生长作为第二外延层的主体区层113；以及在主体区层113上生长作为第三外延层的源极区层112。在各个外延过程期间，可以原位掺杂各个外延层。
根据第二实施例，提供了具有与漂移区层111的掺杂浓度相对应的掺杂浓度的半导体衬底。通过注入过程，将掺杂原子通过第一表面101注入到该衬底中，以便形成主体区层113和源极区层112。此外，将掺杂原子通过与第一表面101相对的第二表面102注入到衬底中，以便形成漏极区层114。
根据第三实施例，提供了形成漏极区层114的半导体衬底。在漏极区层114上生长外延层，其中外延层具有与漂移区层111的掺杂浓度相对应的掺杂浓度。该外延层形成半导体主体100的第一表面101。最后，将掺杂原子通过第一表面101注入到外延层中，以便形成主体区层113和源极区层112。
参照图4B，形成在半导体主体100的第二横向方向y上分隔的二极管区30。形成二极管区30可以包括：在漂移区层111中形成第一二极管区31；以及形成第二二极管区（接触区）32，其中接触区32从第一表面101延伸通过源极区层112和主体区层113到第一二极管区31中。形成第一和第二二极管区31、32可以包括传统的注入过程。本文中下面进一步参照图5A和5B来解释用于生产二极管区30的方法的实施例。
参照图4C，该方法进一步包括在半导体主体100的第一表面101中产生沟槽。沟槽各自包括第一侧壁1101、与第一侧壁1101相对的第二侧壁1102、以及底部1103。沟槽将主体区层113和源极区层112细分成若干区段，其中在形成二极管区30之前具有主体区层113的掺杂浓度的那些区形成主体区13，并且在形成二极管区30之前具有源极区层112的掺杂浓度的那些区形成半导体器件的源极区12。参照图4C，沟槽110被形成为使得每个沟槽110的第一侧壁1101邻接一个源极区12和一个主体区13并且每个沟槽110的第二侧壁1102邻接一个二极管区30，具体地，二极管区30的接触区32。在这种情况下，在二极管区30和漂移区11之间形成的pn结邻接每个沟槽110的底部1103。形成沟槽110可以包括使用蚀刻掩模210的传统蚀刻过程。
可选地，存在沟槽110的后处理，在该后处理中，个体沟槽的侧壁1101、1102与底部1103之间的拐角被圆化（round）。在图4D中图示了这种圆化过程的结果。圆化过程可以包括在包含氢气的大气中的热处理。根据一个实施例，利用作为在接下来的过程步骤中形成的栅极电介质22的厚度的至少两倍或其厚度的至少四倍的半径来形成侧壁1101、1102与底部1103之间的拐角。根据一个实施例，拐角的半径是至少300纳米（nm）。
根据一个实施例，利用逐渐变细的侧壁来形成沟槽110。根据一个实施例，半导体主体100包括SiC，并且利用逐渐变细的侧壁来形成沟槽110以使得第一侧壁1101与SiC半导体晶体的c轴对齐。
在图4I中图示的接下来的过程步骤中，在沟槽110的侧壁1101、1102和底部1103上形成栅极电介质22。可选地，还在半导体主体100的第一表面101上形成栅极电介质22。根据一个实施例，半导体主体100包括SiC，并且栅极电介质22包括二氧化硅（SiO2）。形成栅极电介质22可以包括氧化过程或者沉积过程和氧化过程的组合。
参照图4F，在沟槽110中以及在半导体主体100的第一表面101上方形成电极层21’。电极层21’的位于沟槽110中的那些区段形成个体器件单元的栅电极21。例如，电极层21’包括高掺杂多晶半导体材料（诸如多晶硅）或硅化物。
参照图4G，电极层21’从第一表面101被去除但保持处于沟槽110中，在沟槽110中电极层21’形成栅电极21。去除第一表面101上方的电极层21’可以包括蚀刻过程，诸如干法蚀刻过程。
参照图4H，在第一表面101和栅电极21上方形成绝缘层51。绝缘层51可以是传统的电绝缘层，诸如氧化物。形成绝缘层51可以包括化学气相沉积（CVD）。
参照图4I，在绝缘层51中形成接触开口52。形成接触开口可以包括使用蚀刻掩模的传统蚀刻过程。图4I图示了在二极管区30和源极区12上方形成第一接触开口52。等效地，在图4I的垂直横截面中的视野之外的区中栅电极21上方形成第二接触开口53。
最后，形成源电极41。源电极41在第一接触开口52中电接触二极管区30和源极区12。可选地，源电极41包括前面解释的两个子层411、412。形成源电极41可以包括金属沉积过程，诸如 CVD过程、蒸发过程、流电过程和溅射过程。源电极41包括导电材料，诸如金属或硅化物。等效地，栅极连接电极42被形成在图4J中的视野之外的区中并在第二接触开口53中接触栅电极21。
图5A和5B图示了用于生产二极管区30的方法的一个实施例。在图5A和5B的方法中，利用第一二极管区31和第二二极管区32来形成二极管区30。参照图5A，形成第一二极管区31可以包括使用注入掩模210的注入过程。对注入过程的注入能量进行调整以使得掺杂原子被注入到漂移区层111中。
参照图5B，形成第二二极管区（接触区）32包括使用另外注入掩模的另外注入过程。可以通过沿第一注入掩模210的开口的侧壁形成分隔部220来获得该另外注入掩模。形成接触区32可以包括具有不同注入能量的若干随后注入过程。另外，每个注入过程，还有前面参照图4A到4J解释的注入过程，包括用于激活所注入的掺杂原子的热处理。
虽然已公开了本发明的各种示例性实施例，但是对于本领域技术人员来说将显而易见的是，在不脱离本发明的精神和范围的情况下，可以做出将实现本发明的一些优点的各种改变和修改。对于本领域技术人员来说将显而易见的是，执行相同功能的其它部件可以被合适地替代。应当提到的是，参照特定附图解释的特征可以与其它附图的特征组合，即使在没有明确提到这一点的那些情况下。另外，可以在使用适当处理器指令的全软件实施方式中或者在利用硬件逻辑和软件逻辑的组合以实现相同结果的混合实施方式中实现本发明的方法。意图由所附权利要求覆盖对本发明构思的这种修改。
 为了便于描述，使用诸如“在……下方”、“在……之下”、“下”、“在……上方”、“上”等的空间相对术语来解释一个元件相对于第二元件的定位。这些术语意图包含除了与在附图中描绘的那些定向不同的定向之外器件的不同定向。另外，还使用诸如“第一”、“第二”等的术语来描述各种元件、区、区段等，并且这些术语也不意图进行限制。贯穿该描述，类似的术语指代类似的元件。
如本文中使用的那样，术语“具有”、“包含”、“包括”、“含有”等是开放式术语，其指示所声明的元件或特征的存在，但不排除附加元件或特征。冠词“一”、“一个”和“该”意图包括复数以及单数，除非上下文以其它方式清楚地指示。
应当理解的是，本文中描述的各种实施例的特征可以彼此组合，除非以其它方式具体注明。

Claims (16)

1.一种半导体器件，包括半导体主体和集成在所述半导体主体中的至少两个器件单元，每个器件单元包括：
漂移区、源极区、以及布置在所述源极区和所述漂移区之间的主体区；
二极管区、以及所述二极管区和所述漂移区之间的pn结；
沟槽，具有第一侧壁、与第一侧壁相对的第二侧壁、以及底部，其中所述主体区邻接所述第一侧壁，所述二极管区邻接所述第二侧壁，并且所述pn结邻接所述沟槽的底部；
栅电极，布置在所述沟槽中并通过栅极电介质与所述主体区、所述二极管区和所述漂移区介电绝缘；
其中所述至少两个器件单元的二极管区在所述半导体主体的横向方向上远离。
2.根据权利要求1的半导体器件，进一步包括：源电极，电连接到每个器件的源极区和二极管区。
3.根据权利要求2的半导体器件，其中每个二极管区包括：
第一二极管区，与所述漂移区形成pn结；
第二二极管区，比所述第一二极管区更高地掺杂并连接到所述源电极。
4.根据权利要求3的半导体器件，其中所述第二二极管区邻接所述沟槽的第二侧壁。
5.根据权利要求1的半导体器件，其中所述至少两个器件单元共享所述漂移区。
6.根据权利要求1的半导体器件，其中每个器件单元进一步包括漏极区，所述漏极区在所述半导体主体的垂直方向上邻近所述漂移区并远离所述二极管区。
7.根据权利要求1的半导体器件，其中所述至少两个器件单元共享所述漏极区。
8.根据权利要求1的半导体器件，
其中所述至少两个器件单元是邻近的，并且
其中一个器件单元的二极管区邻接另一个器件单元的主体区。
9.根据权利要求1的半导体器件，
其中所述半导体主体包括SiC晶体，以及
其中所述沟槽的第一侧壁与所述SiC晶体的c轴对齐。
10.根据权利要求9的半导体器件，其中所述半导体主体的第一表面和第一表面之间的角度在80°和89°之间。
11.一种生产半导体器件的方法，所述方法包括：
提供半导体主体，所述半导体主体包括漂移区层、邻接漂移区层的主体区层、和邻接主体区层且形成所述半导体主体的第一表面的源极区层；
形成至少两个二极管区，使得每个二极管区从所述第一表面延伸通过所述源极区层和所述主体区层到所述漂移区层中，其中每个二极管区和所述漂移区层形成一个pn结；
形成至少两个沟槽，每个沟槽具有第一侧壁、与第一侧壁相对的第二侧壁、以及底部，使得每个沟槽在一个侧壁上邻接所述主体区层，在所述第二侧壁上邻接一个二极管区以及在所述底部上邻接一个pn结；
在每个沟槽中形成栅电极和栅极电介质，所述栅极电介质将所述栅电极与所述半导体主体介电绝缘；
其中在形成所述二极管区之后保持的所述源极区层的区段形成源极区，并且其中在形成所述二极管区之后保持的所述主体区层的区段形成主体区。
12.根据权利要求11的方法，进一步包括：
在所述第一表面上形成绝缘层；
在每个二极管区和每个源极区上方所述绝缘层中形成第一接触开口；以及
形成源电极，所述源电极在每个第一接触开口中电连接到所述源极区和所述二极管区。
13.根据权利要求12的方法，进一步包括：
在每个栅电极上方所述绝缘层中形成第二接触开口；以及
形成栅极连接电极，所述栅极连接电极在每个第二接触开口中电连接到所述栅电极。
14.根据权利要求11的方法，其中所述沟槽是细长的沟槽。
15.根据权利要求11的方法，
其中所述半导体主体包括SiC晶体，以及
其中所述沟槽被形成为使得所述沟槽的第一侧壁与所述SiC晶体的c轴对齐。
16.根据权利要求15的方法，其中所述第一沟槽被形成为使得所述半导体主体的第一表面和第一表面之间的角度在80°和89°之间。
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