CN103620774A - 倒装芯片、正面和背面线键合相组合的封装 - Google Patents

倒装芯片、正面和背面线键合相组合的封装 Download PDF

Info

Publication number
CN103620774A
CN103620774A CN201280030799.8A CN201280030799A CN103620774A CN 103620774 A CN103620774 A CN 103620774A CN 201280030799 A CN201280030799 A CN 201280030799A CN 103620774 A CN103620774 A CN 103620774A
Authority
CN
China
Prior art keywords
microelectronic element
substrate
front surface
microelectronic
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201280030799.8A
Other languages
English (en)
Other versions
CN103620774B (zh
Inventor
贝尔加桑·哈巴
理查德·德威特·克里斯普
韦勒·佐尼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera LLC filed Critical Tessera LLC
Publication of CN103620774A publication Critical patent/CN103620774A/zh
Application granted granted Critical
Publication of CN103620774B publication Critical patent/CN103620774B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种微电子组件10可以包括具有在其第一表面34和第二表面32之间延伸的孔39、在第一表面处的衬底触点41和在第二表面处的端子36的衬底30。微电子组件10可以包括：具有面对第一表面34的前表面16的第一微电子元件12，具有面对第一微电子元件的前表面22的第二微电子元件14，以及将第二微电子元件的触点26与端子36电连接的引线50。第二微电子元件14的触点26可以暴露在前表面22处且暴露于第一微电子元件12的边缘29之外。第一微电子元件12可以用于再生在端子36处被微电子组件10接收的至少一些信号并且将所述信号传输到第二微电子元件14。

Description

倒装芯片、正面和背面线键合相组合的封装
相关申请的交叉引用
本申请要求2011年4月21日申请的美国临时专利申请61／477,883以及2011年11月29日申请的美国专利申请13／306,182的权益，其公开内容通过引用并入本文。以下的共同所有的申请通过引用并入本文，包括：均在2011年4月21日申请的美国临时专利申请61／477,820、61／477／877以及61／477,967。
技术领域
本发明涉及堆叠微电子组件，制造这种组件的方法，以及用于这种组件的部件。
背景技术
半导体芯片通常设为单独的预封装单元。标准芯片具有带有大的前面的扁平矩形体，该前面具有连接到芯片的内部电路的触点。每个单独的芯片典型地安装在封装中，封装再安装在电路板例如印制电路板上，封装将芯片的触点连接到电路板的导体。在很多常规的设计中，芯片封装在电路板中占用的面积比芯片本身的面积大很多。如参考具有前面的扁平芯片的本公开中所使用的“芯片的面积”应被理解为指的是所述前面的面积。在“倒装芯片”设计中，芯片的前面面对封装衬底的面，即，通过焊球或其他连接元件将芯片载体与芯片上的触点直接键合到芯片载体的触点。通过覆盖芯片的前面的端子又可以将芯片载体键合到电路板。“倒装芯片”设计提供相对紧凑的布置；每个芯片占用的电路板的面积等于或稍大于芯片的前面的面积，例如在共同转让的美国专利5,148,265、5,148,266和5,679,977中的某些实施例中所公开的，其全部公开内容通过引用并入本文。
某些创新的安装技术提供的紧密度接近或等于常规倒装芯片键合的紧密度。可以在等于或稍大于芯片本身的面积的电路板的面积中容置单个芯片的封装通常被称为“芯片级封装”。
除了最小化被微电子组件占用的电路板的平面面积，还需要生产一种垂直于电路板平面的整体高度或尺寸较小的芯片封装。这种薄的微电子封装允许将其中安装有封装的电路板紧挨着相邻结构放置，由此产生包含电路板的产品的整体尺寸。已经提出用于在单个封装或模块中设置多个芯片的各种提议。在常规的“多芯片模块”中，芯片并排地安装在单个封装衬底上，然后可以将该封装衬底安装至电路板。这种方法只是提供芯片所占用的电路板的总面积的有限减小。总面积仍然大于模块中各个芯片的总表面积。
还已经提出将多个芯片封装在“堆叠”布置(即多个芯片放置成一个在另一个之上的布置)中。在堆叠布置中，可以将多个芯片安装在比芯片的总面积小的电路板的面积中。例如，在上述的美国专利5,679,977、5,148,265以及5,347,159的某些实施例中公布了一些堆叠芯片布置，其全部公开内容通过引用并入本文。也通过引用并入本文的美国专利4,941,033公开一种布置，其中芯片一个在另一个之上地堆叠，且通过与芯片相关联的所谓的“布线膜”上的导体彼此互连。
除了现有技术的这些努力，需要对用于具有基本位于芯片的中心区域的触点的芯片的多芯片封装的情况进一步改进。某些半导体芯片，例如一些存储芯片，通常具有基本沿芯片的中心轴设置的一行或两行触点。
发明内容
根据本发明的方面，一种微电子组件可以包括具有相对地面对的第一表面和第二表面以及在所述第一表面和第二表面之间延伸的至少一个孔的衬底，所述衬底具有在所述第一表面处的衬底触点和在所述第二表面处的端子。所述微电子组件还可以包括具有面对所述第一表面的前表面的第一微电子元件，具有面对所述第一微电子元件的前表面的第二微电子元件，以及将所述第二微电子元件的所述触点与所述端子电连接的引线。所述第一微电子元件可以具有远离所述前表面的后表面以及在所述前表面和所述后表面之间延伸的边缘。所述第一微电子元件可以具有在所述前表面处的面对相应的所述衬底触点且与所述相应的衬底触点相联接的多个触点。所述第二微电子元件可以具有暴露在其所述前表面处且暴露在所述第一微电子元件的边缘之外的多个触点。所述第二微电子元件可以配备有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。所述引线具有与所述至少一个孔对齐的部分。所述第一微电子元件可用于再生在所述端子处被所述微电子组件接收的至少一些信号和用于将所述信号传输至所述第二微电子元件。
在示例性实施例中，所述第一微电子元件可用于控制所述微电子组件外部的部件与所述第二微电子元件之间的数据传递。在一个实施例中，所述第一微电子元件可用于提供所述外部部件和所述第二微电子元件之间的信号缓冲。在特定实施例中，所述第一微电子元件可用于主要执行逻辑功能。
在一个实施例中，所述组件还可包括至少部分地覆盖所述第二微电子元件的第三微电子元件。所述第三微电子元件可具有暴露在其所述前表面处并暴露在所述第二微电子元件的边缘之外的多个触点，所述多个触点电连接到至少一些所述衬底触点。所述组件还可包括将所述第三微电子元件的所述触点与所述端子电连接的第二引线，所述第二引线具有与至少一个孔对齐的部分。在一个实施例中，所述第二微电子元件和所述第三微电子元件分别包括非易失性闪存。在特定实施例中，所述第一微电子元件可以具有除提供存储器存储阵列之外的主要功能。在特定实施例中，所述第二微电子元件的所述触点位于邻近所述第二微电子元件的边缘的位置，所述第三微电子元件的所述触点位于邻近所述第三微电子元件的边缘的位置。
在特定实施例中，所述第二微电子元件的所述触点可以设置在其所述前表面的中心区域内。所述中心区域可以与所述第二微电子元件的相对的第一边缘和第二边缘间隔开。在一个实施例中，衬底可以包括具有限定所述第一衬底表面和所述第二衬底表面的第一表面和第二表面的介质元件。沿所述介质元件的所述第一表面或所述第二表面的至少一个延伸并延伸至所述至少一个孔的边缘之外的引线可以与所述第二微电子元件的所述触点键合。在示例性实施例中，所述衬底可以具有低于百万分之七／℃的热膨胀系数。在特定实施例中，所述引线可以包括延伸穿过所述至少一个孔至所述衬底的所述第二表面处的键合触点的线键合。
在一个实施例中，所述组件还可包括从所述衬底或所述第一微电子元件的至少一个延伸的基本刚性的导电接线柱。在一个实施例中，所述组件还可包括所述第二微电子元件的所述前表面和衬底的所述第一表面之间的间隔元件。在示例性实施例中，所述组件还可包括具有前表面和远离所述前表面的后表面的第三微电子元件，所述后表面面对所述第一微电子元件的所述后表面。所述第三微电子元件可以具有暴露在其所述前表面处的多个触点以及将所述第三微电子元件的所述触点与至少一些所述衬底触点电连接的多条引线。
在示例性实施例中，可以将所述第三微电子元件的所述触点连接到至少一些所述衬底触点的所述引线包括线键合。在特定实施例中，将所述第三微电子元件的所述触点连接到至少一些所述衬底触点的所述引线可以包括延伸至所述第三微电子元件的边缘之外的引线键合。所述第三微电子元件的所述边缘可以在所述第三微电子元件的所述前表面和后表面之间延伸。在一个实施例中，所述组件还可以包括具有面对所述介质元件的前表面以及远离所述前表面的后表面的第四微电子元件。所述第四微电子元件可以具有暴露在其所述前表面处并且电连接到至少一些所述第一导电元件的多个触点。所述第二微电子元件可以至少部分地覆盖所述第四微电子元件。
在特定实施例中，所述组件还可包括具有面对所述衬底的前表面和远离所述前表面的后表面的第三微电子元件。所述第三微电子元件可以具有暴露在其所述前表面处并且电连接到至少一些所述衬底触点的多个触点。所述第二微电子元件可至少部分地覆盖所述第三微电子元件。在示例性实施例中，所述第三微电子元件可以包括用于主要执行逻辑功能的芯片。
根据本发明的另一方面，微电子组件可包括具有相对地面对的第一表面和第二表面以及在所述第一表面和第二表面之间延伸的第一孔的衬底，所述衬底进一步具有在其上的多个导电元件。所述组件还可包括具有面对所述衬底的表面的第一微电子元件，具有面对所述第一微电子元件的前表面的第二微电子元件，连接至所述第二微电子元件并延伸穿过所述第一孔至所述衬底上的至少一些所述导电元件的信号引线，以及其中具有设置在所述衬底的所述第一表面和所述第二微电子元件的所述前表面之间的有源电路元件的至少一个功率调节部件。所述第一微电子元件可具有远离所述前表面的另一表面以及在其所述表面之间延伸的边缘。所述第二微电子元件可具有暴露在其所述前表面处的多个触点。所述第二微电子元件可突出于所述第一微电子元件的所述边缘之外。
在一个示例中，所述衬底可包括在所述第一表面和所述第二表面之间延伸的第二孔。所述微电子组件可进一步包括将所述第一微电子元件与所述衬底上的所述导电元件电连接的额外的信号引线。所述额外的信号引线可具有与所述第二孔对齐的部分。在特定实施例中，所述至少一个功率调节部件包括开／关切换的开关。本发明的另一方面可提供将根据本发明的上述方面的微电子组件与其连接至的其他电子部件相结合的***。例如，所述***可设置在单个壳体中和／或安装至单个壳体，所述壳体可以为便携式壳体。根据本发明的这个方面中的优选实施例的***可以比可比较的常规***更紧凑。
附图说明
现在将参考附图描述本发明的各个实施例。需要理解的是，这些附图仅描述本发明的一些实施例，因此不应作为对本发明范围的限制。
图1是根据本发明的实施例的堆叠微电子组件的示意性截面正视图；
图2是图1所示的微电子组件的俯视图；
图3A是示出图1所示的堆叠微电子组件的一部分的剖视图；
图3B是示出图3A的一部分的局部剖视图；
图4A是示出根据图1所示的实施例的变型的堆叠微电子组件的一部分的剖视图；
图4B是示出图4A的一部分的剖视图；
图5是根据本发明的实施例的堆叠微电子组件的示意性截面正视图；
与6是根据本发明的另一个实施例的堆叠微电子组件的示意性截面正视图；
图7是根据本发明的另一个实施例的堆叠微电子组件的示意性截面正视图；以及
图8是根据本发明的一个实施例的***的示意图。
具体实施方式
参考图1和图2，根据本发明的实施例的堆叠微电子组件10包括背面或倒装芯片放置的第一微电子元件12和背面放置的第二微电子元件14。在一些实施例中，第一微电子元件12和第二微电子元件14可为半导体芯片，或包括半导体芯片的元件，该半导体芯片具有在其前表面16处的触点。该半导体芯片可为半导体材料(例如硅或砷化镓)的薄片，并且可被设置为单独的预封装单元。半导体芯片可配备有有源电路元件(例如，晶体管、二极管等)，或无源电路元件(例如电阻、电容或电感等)，或有源和无源电路元件的组合。在“有源”半导体芯片中，每个微电子元件中的有源电路元件典型地在一个或多个“集成电路”中电连接在一起。第一微电子元件和第二微电子元件都可如下文中讨论的电连接至衬底30。在一个实施例中，衬底30可再电连接至电路板，例如印刷电路板。在特定实施例中，微电子组件10可为具有用于与电路板(例如印刷电路板等)的面上的相应触点电连接的端子的微电子“封装”。
在特定实施例中，衬底可为各种结构的介质元件，例如聚合材料或无机材料(例如陶瓷或玻璃)的介质元件，衬底具有在其上的导电元件，例如端子以及与端子电连接的导电元件(例如迹线、衬底触点或其他导电元件)。在另一示例中，衬底可基本由半导体材料(例如硅)组成，或者可选地包括半导体材料层及其一个或多个介质层。这种衬底可具有低于百万分之七每摄氏度(“7ppm／℃”)的热膨胀系数。在又一个实施例中，衬底可为具有引脚的引线框架，其中端子可以为引脚的部分，例如引脚的端部。
第一微电子元件12可包括主要用于执行逻辑功能的半导体芯片，例如微处理器、特定用途集成电路(“ASIC”)、现场可编程门阵列(“FPGA”)或其他逻辑芯片等。在其他示例中，第一微电子元件12可以包括或者为存储芯片(例如，闪存(“或非”或“与非”)芯片、动态随机存取存储(DRAM)芯片或静态随机存取存储(SRAM)芯片)，或者主要用于执行一些其他功能。在一个示例中，第一微电子元件12可以配备有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。第一微电子元件12具有前表面16、远离前表面16的后表面18、以及在前表面和后表面之间延伸的第一边缘27和第二边缘29。
在特定实施例中，第一微电子元件12可以具有除提供存储器存储阵列之外的主要功能。在一个示例中，第一微电子元件12可用于控制微电子组件的外部部件与第二微电子元件之间的数据传递。在示例性实施例中，第一微电子元件12可用于提供外部部件和堆叠微电子组件10中的其他微电子元件(例如，第二微电子元件14或多个第二微电子元件(例如，图7所示的第二微电子元件714))之间的信号缓存。在一个示例中，第一微电子元件12可用于再生在端子36处被微电子组件10接收的至少一些信号并将所述信号传输至第二微电子元件14。这种第一微电子元件12可用于帮助提供第二微电子元件14关于微电子组件10的外部部件的阻抗隔离。
在另一示例中，微电子组件10可配置为用作固态存储器驱动。在这种示例中，第一微电子元件12可包括主要用于执行逻辑功能的半导体芯片，例如固态驱动控制器，第二微电子元件14可包括存储器存储元件，例如非易失性闪存。第一微电子元件12可包括用于将***(例如图8的***1100)的中央处理单元从管理至和从包括在第二微电子元件14中的存储器存储元件的数据传递中解脱出来的专用处理器。这种包括固态驱动控制器的第一微电子元件12可以提供至和从***例如***1100的主板(例如图8所示的电路板1102)上的数据总线的直接存储访问。
电触点20暴露在第一微电子元件12的前表面16处。如在本发明所使用的，导电元件“暴露在”结构的表面处的描述表示导电元件可用于与在与介质结构的表面垂直的方向上从介质结构的外部朝介质结构的表面移动的理论点接触。因此，暴露在结构的表面处的端子或其他导电元件可从这样的表面突出；可与这样的表面平齐；或者可相对于这样的表面凹入并通过介质结构中的孔或凹入部暴露。电触点20可包括键合焊盘或其他导电结构(例如凸点、接线柱等)。键合焊盘可以包括一种或多种金属(例如铜、镍、金或铝)，并且可以为大约0.5μm厚。键合焊盘的大小可随着装置类型的改变而改变，但其一侧将典型地为几十微米到几百微米。
第二微电子元件14具有前表面22、远离前表面22的后表面24、在前表面和后表面之间延伸的第一边缘35和第二边缘37、以及暴露在前表面22处的触点26。如图1所示，第一微电子元件12和第二微电子元件14相互堆叠，以便第二微电子元件14的至少一部分覆盖第一微电子元件12的至少一部分，以及第二微电子元件14的触点26设置在第一微电子元件12的第二边缘29之外。
在特定实施例中，如图1所示，第二微电子元件14的前表面22包括第一端区域21和第二端区域23以及在第一端区域21和第二端区域23之间延伸的中心区域19。第一端区域21在中心区域19和第一边缘35之间延伸，第二端区域23在中心区域19和第二边缘37之间延伸。中心区域可延伸第二微电子元件14的第一边缘35和第二边缘37之间的距离的三分之一，第一端区域和第二端区域可分别延伸边缘35和边缘37之间的距离的三分之一。电触点26暴露在第二微电子元件14的前表面22处。例如，触点26可布置成邻近前表面22的中心的一行或平行的两行。第二微电子元件14可包括或者可为DRAM芯片。在一个示例中，第二微电子元件14可配备有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。第二微电子元件14的中心区域19的至少一部分突出于第一微电子元件12的第二边缘29之外，以便第二微电子元件14的触点26暴露于第一微电子元件12的第二边缘29之外。
如上所讨论的，在一个实施例中，衬底30可包括具有相对地面对的第一表面34和第二表面32的介质元件。一个或多个导电元件或端子36暴露在介质元件30的第二表面32处。在特定实施例中，一些或全部端子36可以关于第一微电子元件12和／或第二微电子元件14是可移动的。
衬底进一步包括在其相对的第一表面和第二表面之间(例如，在介质元件30的相对的第一表面和第二表面之间)延伸的一个或多个孔。在如图1所示的实施例中，衬底包括孔39和与介质元件的孔39对齐的至少一些触点26。多条引线将第二微电子元件的触点26与微电子组件的端子36电连接。引线具有与孔39对齐的部分。例如，引线可包括键合至衬底触点的线键合50，衬底触点再通过引线的其他部分(例如，沿半导体元件或介质元件30延伸的金属迹线)连接至端子36，或者如果衬底包括引线框架，引线可包括其引脚的部分。
如图1所示，衬底30可延伸至第一微电子元件12的第一边缘27以及第二微电子元件14的第二边缘35之外。在示例中，包括介质材料的衬底可称作“介质元件”30，不论是部分地还是全部地由任何适当的介质材料制成。介质元件30可为，例如，介质元件30可包括柔性材料层，例如聚亚酰胺层、BT树脂层或通常用于制造带式自动键合(TAB)带的其他介质材料层。可选地，介质元件30可包括相对刚性的板状材料，例如纤维增强环氧树脂的厚层，例如，Fr-4板或Fr-5板。不论使用何种材料，介质元件30可包括单层的或多层的介质材料。
介质元件30的第一表面34可与第一微电子元件12的前表面16并列。如图1和图2所示，介质元件30还可包括暴露在第二表面32上的导电元件40以及导电迹线25。导电迹线25将导电元件40电联接至端子36。可使用共同转让的美国申请公布2005／0181544中描述的方法产生迹线和导电元件40，其全部公开内容通过引用并入本文。介质元件30可进一步包括暴露在第一表面34上的导电元件48。
返回图1，间隔元件或支撑元件31可放置在第二微电子元件14的第一端区域21和介质元件30的一部分之间。间隔元件31可帮助将第二微电子元件支撑在衬底30的上方。这种间隔元件31可以由例如介质材料(例如硅二极管或其他材料)、半导体材料(例如硅)、或一层或多层的粘合剂或其他聚合材料制成。在特定实施例中，间隔元件可以包括金属或由金属制成。如果间隔元件包括粘合剂，粘合剂可以将第二微电子元件14连接至衬底30。在一个实施例中，间隔元件31在基本垂直于衬底的第一表面34的竖直方向可具有与第一微电子元件12的前表面16和后表面18之间的第一微电子元件12的厚度基本相等的厚度。如图1所示，如果间隔元件31包括粘合剂，该粘合剂可将第二微电子元件14连接至介质元件30。如图1所示，第二微电子元件14的第二端区域23可通过键合材料60(例如可热传导的粘合剂60)键合至第一微电子元件12的第二端区域17。同样地，粘合剂(可选地，热传导的粘合剂)可将第二微电子元件的第一端区域与间隔元件31键合。类似地，间隔元件61可包括用于将第二微电子元件14与间隔元件31键合的粘合剂。在特定实施例中，键合材料60、61或两者均可部分地或全部地由晶元粘贴粘合剂制成，在特定示例中，可由低弹性模量材料(例如硅弹性体)制成。然而，如果微电子元件12和14为由相同材料形成的常规半导体芯片，键合材料60、61或两者均可全部地或部分地由高弹性模量粘合剂或焊料制成，这是因为，响应于温度变化，微电子元件将趋于一致地扩张或收缩。无论使用何种材料，间隔元件31和60的每个可包括单个层或多个层。
参考图1，微电子组件可包括将第二微电子元件12的触点26电连接至衬底的端子36的键合线50。在一个实施例中，引线可包括延伸穿过孔39并键合至微电子元件的触点26、40和衬底的键合元件(例如，线键合)。键合元件50至少部分地与介质元件30的孔39对齐。键合线50可包括将第二微电子元件14的一些触点与导电元件40电连接的多线键合52、54。线键合52、54延伸穿过孔39。线键合52和54的每个将触点26电联接至介质元件30的相应导电元件40。键合线50可包括如2010年10月19日申请的、发明名称为“Enhanced Stacked Microelectronic Assemblies with Central Contacts and Improved ThermalCharacteristics”的美国专利申请12／907,522中描述的多线键合结构，其全部公开内容通过引用并入本文。如图1所示，可选地或额外地，引线(例如引线键合49)可沿如图所示的介质元件30的第一表面34延伸或沿第二表面延伸并进入孔39以与触点26电连接。引线键合49不必延伸穿过介质元件30的孔39但至少部分与孔对齐。
微电子组件10可进一步包括至少覆盖第一微电子元件12和第二微电子元件14的包胶模(overmold)或密封剂11。如图1所示，包胶模11还可覆盖延伸于第一微电子元件12的第一边缘27和第二微电子元件14的第一边缘35之外的介质元件30的部分。因此，包胶模11可至少接触第一微电子元件12的第一边缘27、第二微电子元件14的第一边缘35以及介质元件30的第一表面34。包胶模11可由任何适当的材料制成，包括环氧树脂等。
如2010年10月19日申请的、发明名称为“Enhanced Stacked Microelectronic Assemblieswith Central Contacts and Improved Thermal Characteristics”的美国专利申请12／907,522所描述的，微电子组件10可额外地包括附接至一个或多个第一微电子元件12或第二微电子元件14的后表面的散热片或散热板，其全部公开内容通过引用并入本文。在一些实施例中，微电子组件10包括与第一微电子元件12和／或第二微电子元件14热耦合的散热片，但不包括包胶模11。
此外，微电子组件10可进一步包括附接至介质元件30的第二表面32上的端子36的接合单元81。接合单元81可以为焊球或其他键合块和金属(例如锡、铟或其组合)块，并且适于将微电子组件10接合和电联接至电路板(例如印刷电路板)。
参考图2和图3A，介质元件30还包括导电元件41，例如触点焊盘和介质元件30的第一表面34上的导电迹线25。导电元件41可在介质元件30的内部延伸。因此，如本发明中所使用的，第一特征放置在第二特征“上”的描述不应被理解为要求第一特征位于第二特征的表面上。
继续参考图3A，倒装芯片互连43将第一微电子元件12的前表面16上的电触点20电连接至介质元件30的第一表面34上的导电元件41。在示例性实施例中，第一微电子元件12的前表面16处的多个电触点20可以面对介质元件30的相应的导电元件41并与其接合。倒装芯片互连是用于将半导体芯片上的键合焊盘导电连接至衬底上的触点焊盘的常用方案。在倒装芯片互连中，金属凸点典型地位于每个键合焊盘上。然后，反转微电子元件，以便金属凸点提供微电子元件的触点(例如键合焊盘)与介质元件之间的电通路以及微电子元件至介质元件的机械附接。倒装芯片工艺有很多变型，但是一种常用的配置是使用焊料作为金属凸点以及使用焊料的熔融作为将其固定至键合焊盘和衬底的方法。当焊料熔化时，它可流动以形成截球体。
倒装芯片互连为第一微电子元件12提供比通过线键合连接至介质元件的其他微电子元件多的I/O(输入／输出)。此外，倒装芯片互连将第二微电子元件14和介质元件30之间的线键合路径最小化，从而减少线键合的阻抗。
在图2所述的实施例中，倒装芯片互连43可包括设置在第一微电子元件10和介质元件30之间的多个实心金属凸点45，例如焊球。每个实心金属凸点45可设置在第一微电子元件12的电触点20和介质元件30的导电元件41之间(并与它们接触)，从而提供电触点20和导电元件41之间的电连接。金属凸点45可(并与它们接触)由接合金属或任何其他适当的材料组成。
底充胶47可围绕实心金属凸点45以将第一微电子元件12粘合至介质材料30。底充胶47可特别地设置在第一微电子元件12的前表面16和介质元件30的第一表面34之间以将第一微电子元件12联接至介质元件30。任何适当的粘合剂可用作底充胶47。例如，底充胶47可完全地或部分地由聚合粘合剂(例如环氧树脂)制成。但是，在一些实施例中，底充胶47被完全省略。
参考图4A和图4B，在根据本发明的实施例的变型中，倒装芯片互连43′可包括将第一微电子元件12和介质元件30相连接的多个基本刚性的导电柱106，如2008年9月26日申请的美国专利申请公开2009／0146303所描述的，其全部公开内容通过引用并入本文。导电柱106包括从介质元件30的第一表面34朝第一微电子元件12突出的导电凸点或接线柱108。每个接线柱108基本与从第一微电子元件12的前表面朝介质元件30突出的导电凸点或接线柱110对齐。通过增加微电子元件12和介质元件30之间的间隙或垂直距离，导电柱106为衬底上芯片封装提供增加的高度，但是同时允许减小导电柱106之间的中心水平距离或间距P。增加介质元件30和微电子元件12之间的距离的能力可帮助降低导电圆柱处的压力，可便于底充胶47的应用，并允许使用更多种的底充胶。在一个具体实施例中，柱106延伸微电子元件12的前表面与介质元件30的第一表面34之间的分隔距离的至少40％。这个40％的分隔距离的设置可帮助降低导电柱106处的压力，可便于底充胶47的使用，并允许使用更多种的底充胶。
实心金属凸点或导电接线柱108从介质元件30的第一表面34延伸以形成导电柱106的第一部分。导电接线柱108具有顶表面116和以与介质材料30的顶表面成大角度延伸的边缘表面113，从而当边缘表面113触点介质元件30的第一表面34时生成明显的角度。例如，在所示的实施例中，在介质元件30的第一表面34和导电接线柱108的边缘表面113之间生成大于90度的角度。该角度基于导电接线柱108的形状而不同。例如，圆柱体接线柱可以在介质元件30的第一表面34和导电接线柱108之间具有90度的角度。发明名称为“Chip Capacitor Embedded PWB”的美国专利申请公布2010／0071944、发明名称为“Multilayer Substrate with Interconnection Vias and Method of Manufacturing the Same”的美国专利申请公布2009／0071707、发明名称为“Interconnection Element with Posts Formed byPlating”的美国专利申请公布2009／0145645中描述了示例性工艺和接线柱，其全部公开内容通过引用并入本文。例如，导电接线柱108可由如本文更详细描述的刻蚀工艺形成。可选地，导电接线柱108可通过电镀形成，其中通过介质层(例如，光刻胶层)中图案化的孔将金属镀到基底金属层上而形成接线柱108。
导电接线柱108的尺寸可在显著的范围内变化，但是最典型地，从介质元件30的第一表面34延伸的每个导电接线柱108的高度H1至少为50微米并且可延伸至多达300微米。这些导电接线柱108可具有比它的直径或宽度W1大的高度H1。但是，高度H1也可比宽度W1小，例如为宽度W1的大小的至少一半。
导电接线柱108可由任何导电材料制成，例如铜、铜合金、金及其组合。导电接线柱108至少可包括可被焊料润湿的暴露金属层。例如，接线柱可由铜组成，并且在接线柱的表面具有金层。额外地，导电接线柱108可包括至少一层的熔化温度比将接合至的焊料的熔化温度高的金属层。例如，这种导电接线柱108可包括铜层或完全由铜形成。
导电接线柱108还可具有各种形状，包括截头锥形。每个导电接线柱108的基底114和顶表面116可基本为圆形或具有不同的形状，例如长方形。导电接线柱108的基底114的直径典型地为大约50μm至300μm，而顶表面116的直径典型地为大约25μm至200μm。每个导电接线柱108可具有邻近介质衬底30的基底114和远离介质元件的顶表面116。可选地，从介质元件30的第一表面34开始的导电接线柱的高度H1(排除任何焊接掩模118)典型地从小至30μm到多达200μm。如图3B所示，焊接掩模118可设置在介质元件30上并邻近导电接线柱108。焊接掩模118帮助防止焊料外溢以及防止在回流阶段期间发生邻近柱106之间的桥接。
如上所讨论的，倒装芯片互连43′还可包括从第一微电子元件12的前表面13延伸的导电接线柱110。能够从微电子元件等延伸的示例性导电接线柱和制造导电接线柱的方法在转让给Advanpak的美国专利6,681,982、6,592,109和6,578,754中进行了描述，其全部公开内容通过引用并入本文。例如，导电接线柱110可由刻蚀工艺形成。可选地，导电接线柱110可由电镀形成，其中通过介质层(例如，光刻胶层)中图案化的孔将金属镀到基底金属层上而形成接线柱108。与从介质元件30延伸的导电接线柱108类似，从微电子元件12延伸的接线柱110可具有顶表面128和以与微电子元件的前表面16成大角度延伸的边缘表面117，从而在微电子元件和导电接线柱之间生成明显的角度。
为了提供导电接线柱110和微电子元件12之间的金属触点，在微电子元件12的前表面16上可提供凸块下金属化层120。凸块下金属化层120典型地由金属(包括钛、钛钨、铬)组成。凸块下金属化层120用作导电柱106的导电金属触点。还可使用本领域已知的方法在微电子元件12的前表面16上、微电子元件12和凸块下金属化层120之间提供钝化层119。。
从微电子元件12延伸的导电接线柱110的尺寸也可在显著的范围内变化，但是最典型地，每个导电接线柱110的高度H2不小于50微米。导电接线柱110可具有比它的宽度W2大的高度H2。但是，高度也可比宽度W2小，例如为宽度的大小的至少一半。
导电接线柱110可由铜或铜合金制成，但也包括其他导电材料，例如金或金与铜的组合物。额外地，导电接线柱110可包括至少一层熔化温度比将接合至的焊料的熔化温度高的金属。例如，导电接线柱将包括铜层或完全由铜形成。
在特定实施例中，导电接线柱110可为圆柱形的，以便接线柱的基底126的直径和接线柱的顶表面128的直径相等。在一个实施例中，导电接线柱的基底126和顶表面128的直径可以为大约30μm至150μm。每个导电接线柱110具有邻近微电子元件12的基底126以及远离微电子元件12的顶表面128。可选地，导电接线柱110可具有各种形状，例如截头锥形、矩形或棒形。
焊料的涂层或帽(cap)(未示出)可附接至导电接线柱110的顶表面128或未附接至微电子元件12的导电接线柱的部分。焊料的帽可具有与导电接线柱110相同的直径或宽度W2，以便它成为导电接线柱110的延伸。在一个示例中，焊料的帽可具有大约25μm至80μm范围内的高度H3。
应理解的是，从微电子元件12的前表面16延伸的导电接线柱110的高度H2可以与从介质元件30的第一表面34延伸的导电接线柱108的高度H1相等。然而，高度可选地可以是不同的，从而导电接线柱110的高度H2可以小于或大于导电接线柱108的高度H1。在特定说明性示例中，从微电子元件12延伸的导电接线柱110可具有50μm长的高度，而从介质元件30延伸的导电接线柱108可具有55μm的高度H1。
为了将微电子元件12与介质元件30导电连接在一起，微电子元件12上的导电接线柱110必须连接至介质元件30上的导电接线柱108。微电子元件12被反转，以便微电子元件12的导电接线柱110和介质元件30的导电接线柱108彼此对齐并且紧密邻近。回流微电子元件12上的焊料的帽以允许焊料浸湿微电子元件12上的导电接线柱110的表面以及介质元件30上的导电接线柱108的表面。焊料将浸湿导电接线柱的暴露表面并且产生从微电子元件12延伸至介质元件30的导电柱106。与焊料接合的微电子元件12和介质元件30上的导电柱108、110的增加的表面积可帮助减小焊料接口的电流密度。这种电流密度的减小可帮助减少电迁移并提供更佳的耐久性。
导电柱106包括与导电接线柱导电互连的焊料。在一个示例中，在从微电子元件延伸的导电接线柱的基底和从衬底延伸的基底的暴露部分之间延伸的导电柱的间隙或高度H的范围为80μm至100μm。
导电柱106的壁132可为凸面的或桶形的，其中导电柱的中点区域M1(即微电子元件的导电接线柱110和介质元件30的导电接线柱108之间)具有比分别邻近介质元件30的第一表面34和微电子元件12的前表面16的导电柱106的部分的宽度W1、W2大的宽度W。
进一步地如图4A所示，远离介质元件30延伸的较低接线柱108以及较低触点焊盘117可由单独的刻蚀步骤形成，例如2008年6月28日公布的国际专利PCT No.WO2008／076428所公布的，其全部公开内容通过引用并入本文。例如，可使用具有顶部金属层和底部金属层123以及中间刻蚀停止层或内部金属层121的三层金属衬底以产生导电接线柱108和触点焊盘41。在一个这种工艺中，根据光刻图案化的光刻胶层刻蚀三层或多层金属结构的暴露金属层以形成导电接线柱108，刻蚀工艺停止在该结构的内部金属层121上。内部金属层121包括与顶部金属层和底部金属层123的金属不同的一个或多个金属，这种组成的内部金属层不与用于刻蚀顶部金属层123的刻蚀剂附接。例如，从其刻蚀导电接线柱108的顶部金属层123基本由铜组成，底部金属层123也可基本由铜组成，内部金属层121基本由镍组成。镍相对于铜提供良好的分离性以避免镍层与被刻蚀以形成导电接线柱108的金属层附接。为了形成触点焊盘41，可根据另一光刻图案化的光刻胶层进行另一刻蚀步骤。接线柱108可进一步与其他导电特征(例如通孔115)互连，通孔115进一步地再与其他导电特征(未示出)互连。
微电子组件10可以可选地包括其他类型的倒装芯片互连。其他类型的倒装芯片互连在2008年9月26日申请的美国专利申请公布2009／0146303以及2010年7月8日申请的、发明名称为“Microelectronic Packages with Dual or Multiple-etched Flip Connectors”的美国专利申请12／832,376中进行了描述，其全部公开内容通过引用并入本文。
图5描述图1所示的微电子组件的变型。如图5所示的微电子组件10′与图1所示的微电子组件10类似。在这个变型中，在第二微电子元件14的第一端区域21和介质元件30的部分之间设置第三微电子元件62，代替图1所示的间隔元件31。第三微电子元件62延伸至第二微电子元件14的第二边缘35之外并且可为具有逻辑功能的芯片，例如微处理器或存储器芯片(例如闪存(或非或与非)芯片、DRAM阵列或SRAM阵列)。而且，第三微电子元件62具有前表面66、远离前表面66的后表面68、以及在前表面和后表面之间延伸的第一边缘67和第二边缘69。电触点63暴露在第三微电子元件62的前表面66处。上述的倒装芯片互连的任一个，例如互连43，将第三微电子元件62的前表面66上的电触点63电连接至介质元件的第一表面34上的导电元件41。
键合材料61(例如上述(图1)的键合材料)可设置在第二微电子元件14和第三微电子元件62的后表面68之间。
微电子组件10′可以可选地或额外地包括正面放置在第一微电子元件12上的另一微电子元件72。这个微电子元件72可以为主要用于执行逻辑功能的芯片，例如微处理器、协处理器、图形处理器或信号处理器、特殊用途集成电路芯片(ASIC)或现场可编程门阵列(FPGA)芯片，以及其他示例。可选地，这个微电子元件72可以为存储器芯片，例如，闪存(或非或与非)阵列、DRAM阵列或SRAM阵列、以及其他很多可能的类型。微电子元件72具有后表面76、远离后表面76的前表面78、以及在前表面和后表面之间延伸的第一边缘87和第二边缘79。第四微电子元件72的前表面78可包括第一端区域75和第二端区域77以及位于第一端区域75和第二端区域77之间的中心区域73。第一端区域75在中心区域73和第一边缘87之间延伸，第二端区域77在中心区域73和第二边缘79之间延伸。电触点80，例如键合焊盘，暴露在微电子元件72的前表面78处。电触点80可设置在前表面78的第一端区域75、第二端区域77和／或中心区域73内。在所示的实施例中，电触点80设置在前表面78的第一端区域75内。微电子元件72的第一边缘87可以与第一微电子元件12的第一边缘27对齐。
第一微电子元件14的前表面可以通过粘合剂60附接至第二微电子元件12的后表面。微电子元件72的后表面也可以通过粘合剂附接至微电子元件12的后表面。粘合剂层放置在第二微电子元件14的第二端区域23和第一微电子元件12的第二端区域17之间以及第一微电子元件12的第一端区域15和第四微电子元件72之间。因此，间隔元件60延伸于第二微电子元件14的第一边缘37之外并在第四微电子元件72的第一边缘87处结束。如果间隔元件60包括粘合剂，粘合剂可将第一微电子元件12连接至第四微电子元件72。
一个或多个电连接或引线90将第四微电子元件72的后表面78上的触点80电连接至介质元件30的第一表面34上的一些导线元件41。电连接90可包括将第四微电子元件72的一些触点与介质元件30的第一表面34上的导电元件41电连接的一个或多个线键合92。可选地或额外地，电连接90可以包括引线键合。线键合92可以绕第四微电子元件72的第一边缘87和第一微电子元件12的第二边缘27延伸。每个线键合92将触点80电连接至暴露在介质元件30的第一表面34处的相应导电元件48。电连接90可包括如2010年10月169日申请的、发明名称为“Enhanced Stacked Microelectronic Assemblies with CentralContacts and Improved Thermal Characteristics”的美国专利申请12／907,522中描述的多线键合结构，其全部公开内容通过引用并入本文。
如图5所示，本文描述的微电子组件10′或任何其他微电子组件可通过接合单元81连接至电路板300，例如印刷电路板。
微电子组件10"可进一步包括设置在第二微电子元件14的第一端区域21和介质元件30"的部分之间的一个或多个功率调节部件和／或微机电***(MEMS)200，功率调节部件和／或微机电***(MEMS)200可额外地用于将微电子元件14的前表面在结构的表面34″上方间隔开期望的距离。功率调节部件具有有源电路元件并且能够增强微电子组件10"的性能，特别是在功率敏感的应用(例如移动装置)中，并且可以为一个或多个开／关切换的开关(例如，晶体管、或适于调节来自电源的功率的其他部件)。例如，在一些实施例中，功率调节部件200可以为能够控制对第一微电子元件12"或第二微电子元件14供给功率的功率管理集成电路芯片或微控制器。例如，功率调节部件200可以允许持续地为第一微电子元件12"供给功率，但是仅在使用高功率应用时接通第二微电子元件14"。在这种实施例中，当使用低功率应用时，可以仅将功率供应给第一微电子元件12"。
图1所示的微电子组件10的间隔元件31可由一个或多个功率调节部件和／或MEMS200替代。类似地，图4所示的微电子组件10的第三微电子元件62可由一个或多个功率调节部件和／或MEMS200替代。MEMS200可包括一个或多个压力传感器和／或加速度传感器。
图7示出具有可选结构的图1的微电子组件10的变型。除了微电子组件710包括第二微电子元件714覆盖第一微电子元件712的堆叠之外，图7所示的微电子组件710与上述微电子组件10相同。
与图1所示的实施例类似，第一微电子元件712可以为通过倒装芯片互连743键合至介质元件730的倒转芯片，倒装芯片互连743将第一微电子元件712的前表面716上的电触点720电连接至介质元件的第一表面734上的导电元件741。
在所示的示例中，第二微电子元件714a的第一边缘735可以延伸于第一微电子元件712的第二边缘729之外，以便暴露在第二微电子元件714a的前表面722处的一个或多个导电触点726设置在第一微电子元件的第二边缘729之外。类似地，第二微电子元件714b、714c和714d的每一个的第一边缘735可以延伸于邻近其前表面设置的第二微电子元件的第一边缘之外，以便暴露在第二微电子元件714b、714c和714d的每一个的前表面722处的一个或多个导电触点726设置在邻近其前表面设置的第二微电子元件的第一边缘之外。
多条引线可以将每个第二微电子元件的触点726与微电子组件710的端子736电连接。引线可以具有与延伸穿过介质元件730的至少一个孔739对齐的部分。例如，引线可以包括在每个第二微电子元件的触点726之间延伸至暴露在介质元件730的第二表面732处的导电触点740的线键合750，然后线键合750可以通过引线的其他部分(例如，沿介质元件730延伸的金属迹线)连接至端子736。
虽然微电子组件710在图7中示为具有延伸穿过介质元件730的至少一个孔739，但是，在可选示例中，介质元件可以不设有孔739。在这种实施例中，介质元件730可包括单个区域730a，区域730b可被省略。在这个示例中，在第二微电子元件714的触点726与介质元件730的触点740之间延伸的引线的部分(例如，线键合750)可绕介质元件的边缘730c延伸。如果省略区域730b，介质元件的边缘730c可以为介质元件的***边缘。
微电子组件710可以包括附接至暴露在介质元件730的第二表面732处的端子736的接合单元781(例如，焊球)。这种接合单元781可适于将微电子组件710接合并电联接至外部部件，例如电路板(例如，印刷电路板)。
在示例性实施例中，微电子组件710可配置为用作固态存储驱动。在这种示例中，第一微电子元件712可包括主要用于执行逻辑功能的半导体芯片，例如固态驱动控制器，每个第二微电子元件714可包括存储器存储元件，例如非易失性闪存。第一微电子元件712可包括用于将***(例如图8的***1100)的中央处理单元从将数据传递至包括在第二微电子元件714的存储器存储元件和传递来自包括在第二微电子元件714中的存储器存储元件的数据中解脱出来的专用处理器。这种包括固态驱动控制器的第一微电子元件712可以提供至和从***(例如***1100)的母板(例如，图8所示的电路板1102)上的数据总线的直接存储访问。
在特定实施例中，第一微电子元件712可具有缓冲功能。这种第一微电子元件712可用于提供每个第二微电子元件714关于微电子组件710的外部部件的阻抗隔离。
如图8所示，上述的微电子组件可以用于构建不同的电子***。例如，根据本发明的进一步实施例的***1100包括与其他电子部件1108和1110结合的上述微电子组件1106。在示出的示例中，部件1108为半导体芯片，而部件1110为显示屏，但是可以是任何其他能够使用的部件。当然，尽管为了说明的清楚性，在图8中仅示出了两个额外的部件，***可以包括任何数量的这种部件。微电子组件1106可以为上述的组件的任一个。在进一步的变型中，可以使用任何数量的这种微电子组件。微电子组件1106和部件1108及1110安装在共用的壳体1101(以虚线示意地示出)中，并在必要时彼此电互连以形成期望的电路。在示出的示例性***中，***包括电路板1102(例如柔性印刷电路板)，电路板包括将部件彼此互连的很多个导体1104，在图8中仅示出其中一个导体。然而，这只是示例性的；可以使用用于制造电连接的任何适当的结构。壳体1101被示为在例如移动电话或个人数字助理中可用的类型的便携式壳体，屏幕1110暴露在壳体的表面处。在结构1106包括感光元件(例如成像芯片)的情况下，还可以设置透镜1111或其他光学装置用于将光导向到该结构。此外，图8所示的简化的***只是示例性的；可以使用上述的结构制造其他***，包括通常被认为是固定结构的***，例如台式电脑、路由器等。
尽管已经参考特定实施例对本发明进行了描述，应该理解的是这些实施例仅仅是对本发明的原理和应用的说明。因此，应理解的是，在不脱离通过所附权利要求限定的本发明的精神和范围的情况下，可以对上述说明性实施例进行各种修改以及可以设计其他布置。
应理解的是，各个从属权利要求及其中列举的特征可以以不同的方式与原始权利要求中的特征相结合。还应理解的是，结合各个实施例描述的特征可与所述实施例的其他特征共享。

Claims (27)

1.一种微电子组件，包括：
衬底，所述衬底具有相对地面对的第一表面和第二表面以及在所述第一表面和第二表面之间延伸的至少一个孔，所述衬底具有在所述第一表面处的衬底触点和在所述第二表面处的端子；
第一微电子元件，所述第一微电子元件具有面对所述第一表面的前表面，远离所述前表面的后表面，以及在所述前表面和所述后表面之间延伸的边缘，所述第一微电子元件具有在所述前表面处的面对相应的所述衬底触点且与所述相应的衬底触点相联接的多个触点；
第二微电子元件，所述第二微电子元件具有面对所述第一微电子元件的前表面，所述第二微电子元件具有暴露在其前表面处且暴露在所述第一微电子元件的边缘之外的多个触点，所述第二微电子元件配备有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能；以及
引线，所述引线将所述第二微电子元件的所述触点与所述端子电连接，所述引线具有与所述至少一个孔对齐的部分，
其中所述第一微电子元件用于再生在所述端子处被所述微电子组件接收的至少一些信号，并且将所述信号传输至所述第二微电子元件。
2.根据权利要求1所述的微电子组件，其中所述第一微电子元件用于控制所述微电子组件的外部部件与所述第二微电子元件之间的数据传递。
3.根据权利要求2所述的微电子组件，其中所述第一微电子元件用于提供所述外部部件与所述第二微电子元件之间的信号缓冲。
4.根据权利要求1所述的微电子组件，其中所述第一微电子元件用于主要执行逻辑功能。
5.根据权利要求1所述的微电子组件，进一步包括：
第三微电子元件，所述第三微电子元件至少部分地覆盖所述第二微电子元件，所述第三微电子元件具有暴露在其前表面处且暴露在所述第二微电子元件的边缘之外的多个触点，所述多个触点与至少一些所述衬底触点电连接；以及
第二引线，所述第二引线将所述第三微电子元件的触点与所述端子电连接，所述第二引线具有与所述至少一个孔对齐的部分。
6.根据权利要求5所述的微电子组件，其中所述第二微电子元件和所述第三微电子元件分别包括非易失性闪存。
7.根据权利要求5所述的微电子组件，其中所述第一微电子元件具有除了提供存储器存储阵列之外的主要功能。
8.根据权利要求5所述的微电子组件，其中所述第二微电子元件的所述触点位于邻近所述第二微电子元件的所述边缘的位置，所述第三微电子元件的所述触点位于邻近所述第三微电子元件的边缘的位置。
9.根据权利要求1所述的微电子组件，其中所述第二微电子元件的所述触点设置在其所述前表面的中心区域内，所述中心区域与所述第二微电子元件的相对的第一边缘和第二边缘间隔开。
10.根据权利要求1所述的微电子组件，其中所述衬底包括具有限定所述第一衬底表面和所述第二衬底表面的第一表面和第二表面的介质元件，其中沿所述介质元件的第一表面或第二表面的至少一个延伸并且延伸至所述至少一个孔的边缘之外的引线与所述第二微电子元件的所述触点键合。
11.根据权利要求1所述的微电子组件，其中所述衬底具有低于百万分之七／℃的热膨胀系数。
12.根据权利要求1所述的微电子组件，其中所述引线包括延伸穿过所述至少一个孔至所述衬底的所述第二表面处的键合触点的线键合。
13.根据权利要求1所述的微电子组件，进一步包括从所述衬底或所述第一微电子元件的至少一个延伸的基本刚性的导电接线柱。
14.根据权利要求1所述的微电子组件，进一步包括所述第二微电子元件的所述前表面和所述衬底的所述第一表面之间的间隔元件。
15.根据权利要求1所述的微电子组件，进一步包括：第三微电子元件，所述第三微电子元件具有前表面和远离所述前表面的后表面，所述后表面面对所述第一微电子元件的所述后表面，所述第三微电子元件具有暴露在其所述前表面处的多个触点；以及与所述第三微电子元件的所述触点和至少一些所述衬底触点电连接的多条引线。
16.根据权利要求15所述的微电子组件，其中将所述第三微电子元件的触点连接至至少一些所述衬底触点的所述引线包括线键合。
17.根据权利要求15所述的微电子组件，其中将所述第三微电子元件的所述触点连接至至少一些所述衬底触点的所述引线包括延伸至所述第三微电子元件的边缘之外的引线键合，所述第三微电子元件的边缘在所述第三微电子元件的所述前表面和后表面之间延伸。
18.根据权利要求15所述的微电子组件，进一步包括第四微电子元件，所述第四微电子元件具有面对所述介质元件的前表面和远离所述前表面的后表面，所述第四微电子元件具有暴露在其所述前表面处并且电连接到至少一些所述第一导电元件的多个触点，所述第二微电子元件至少部分地覆盖所述第四微电子元件。
19.根据权利要求1所述的微电子组件，进一步包括第三微电子元件，所述第三微电子元件具有面对所述衬底的前表面和远离所述前表面的后表面，所述第三微电子元件具有暴露在其所述前表面并且电连接到至少一些所述衬底触点的多个触点，所述第二微电子元件至少部分地覆盖所述第三微电子元件。
20.根据权利要求19所述的微电子组件，其中所述第三微电子元件包括用于主要执行逻辑功能的芯片。
21.一种***，包括根据权利要求1所述的组件以及与所述组件电连接的一个或多个其他电子部件。
22.根据权利要求21所述的***，进一步包括壳体，所述组件和所述其他电子部件安装至所述壳体。
23.一种微电子组件，包括：
衬底，所述衬底具有相对地面对的第一表面和第二表面以及在所述第一表面和所述第二表面之间延伸的第一孔，所述衬底进一步具有在其上的多个导电元件；
第一微电子元件，所述第一微电子元件具有面对所述衬底的所述第一表面的表面和远离所述表面的另一表面以及在其所述表面之间延伸的边缘；
第二微电子元件，所述第二微电子元件具有面对所述第一微电子元件的前表面，所述第二微电子元件具有暴露在其所述前表面处的多个触点，所述第二微电子元件突出于所述第一微电子元件的边缘之外；
信号引线，所述信号引线连接至所述第二微电子元件并且延伸穿过所述第一孔至所述衬底上的至少一些所述导电元件；以及
至少一个功率调节部件，所述功率调节部件具有设置在所述衬底的所述第一表面和所述第二微电子元件的所述前表面之间的有源电路元件。
24.根据权利要求23所述的微电子组件，其中所述衬底包括在所述第一表面和所述第二表面之间延伸的第二孔，所述微电子组件进一步包括将所述第一微电子元件与所述衬底上的导电元件电连接的额外的信号引线，所述额外的信号引线具有与所述第二孔对齐的部分。
25.根据权利要求23所述的微电子组件，其中所述至少一个功率调节部件包括开／关切换的开关。
26.一种***，包括根据权利要求23所述的组件以及与所述组件电连接的一个或多个其他电子部件。
27.根据权利要求26所述的***，进一步包括壳体，所述组件与所述其他电子部件安装至所述壳体。
CN201280030799.8A 2011-04-21 2012-03-21 倒装芯片、正面和背面线键合相组合的封装 Expired - Fee Related CN103620774B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161477883P 2011-04-21 2011-04-21
US61/477,883 2011-04-21
US13/306,182 2011-11-29
US13/306,182 US8304881B1 (en) 2011-04-21 2011-11-29 Flip-chip, face-up and face-down wirebond combination package
PCT/US2012/029873 WO2012145114A1 (en) 2011-04-21 2012-03-21 Flip-chip, face-up and face-down wirebond combination package

Publications (2)

Publication Number Publication Date
CN103620774A true CN103620774A (zh) 2014-03-05
CN103620774B CN103620774B (zh) 2016-10-05

Family

ID=47020673

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280030799.8A Expired - Fee Related CN103620774B (zh) 2011-04-21 2012-03-21 倒装芯片、正面和背面线键合相组合的封装

Country Status (7)

Country Link
US (3) US8304881B1 (zh)
EP (1) EP2700097A1 (zh)
JP (1) JP2014514766A (zh)
KR (1) KR20140028015A (zh)
CN (1) CN103620774B (zh)
TW (1) TWI523174B (zh)
WO (1) WO2012145114A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107845628A (zh) * 2016-09-19 2018-03-27 通用电气公司 集成电路器件及其组装方法

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5667381B2 (ja) * 2010-06-01 2015-02-12 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
US8836101B2 (en) * 2010-09-24 2014-09-16 Infineon Technologies Ag Multi-chip semiconductor packages and assembly thereof
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8304881B1 (en) * 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8569884B2 (en) 2011-08-15 2013-10-29 Tessera, Inc. Multiple die in a face down package
KR20140069343A (ko) * 2011-10-03 2014-06-09 인벤사스 코포레이션 패키지의 중심으로부터 옵셋된 단자 그리드를 구비하는 스터드 최소화
JP5887415B2 (ja) 2011-10-03 2016-03-16 インヴェンサス・コーポレイション 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化
WO2013052080A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Stub minimization for multi-die wirebond assemblies with orthogonal windows
US8659142B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8659140B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US8525327B2 (en) 2011-10-03 2013-09-03 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8513813B2 (en) 2011-10-03 2013-08-20 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
TWI508238B (zh) * 2012-12-17 2015-11-11 Princo Corp 晶片散熱系統
US8907500B2 (en) * 2013-02-04 2014-12-09 Invensas Corporation Multi-die wirebond packages with elongated windows
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
JP2015216263A (ja) * 2014-05-12 2015-12-03 マイクロン テクノロジー， インク． 半導体装置
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
KR101953089B1 (ko) * 2014-11-06 2019-05-23 로베르트 보쉬 게엠베하 Mems 트랜스듀서 패키지들의 제조시 사용된 리드 프레임 기반 칩 캐리어
US9799628B2 (en) 2015-03-31 2017-10-24 Qualcomm Incorporated Stacked package configurations and methods of making the same
US10367284B2 (en) 2015-07-27 2019-07-30 Hewlett Packard Enterprise Development Lp Socket to support boards in a spaced relation
WO2017023257A1 (en) * 2015-07-31 2017-02-09 Hewlett Packard Enterprise Development Lp Multi-chip module
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US10121766B2 (en) * 2016-06-30 2018-11-06 Micron Technology, Inc. Package-on-package semiconductor device assemblies including one or more windows and related methods and packages
US9953904B1 (en) 2016-10-25 2018-04-24 Nxp Usa, Inc. Electronic component package with heatsink and multiple electronic components
KR102592640B1 (ko) 2016-11-04 2023-10-23 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US10741525B2 (en) 2017-06-02 2020-08-11 Ultramemory Inc. Semiconductor module
TWI642158B (zh) * 2017-07-21 2018-11-21 致伸科技股份有限公司 指紋感測晶片封裝結構
TWI710075B (zh) * 2019-08-14 2020-11-11 力成科技股份有限公司 半導體封裝結構及其製造方法
US11527480B2 (en) * 2020-04-30 2022-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
JP2022010482A (ja) * 2020-06-29 2022-01-17 キオクシア株式会社 メモリシステム

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010035451A1 (en) * 1999-08-19 2001-11-01 Michael Bettinger Apparatuses for forming wire bonds from circuitry on a substrate to a semiconductor chip, and methods of forming semiconductor chip assemblies
US6385049B1 (en) * 2001-07-05 2002-05-07 Walsin Advanced Electronics Ltd Multi-board BGA package
CN101000903A (zh) * 2006-01-11 2007-07-18 三星Techwin株式会社 印刷电路板以及利用其制造半导体封装的方法
US20080093725A1 (en) * 2006-10-18 2008-04-24 Samsung Electronics Co., Ltd. Semiconductor package preventing warping and wire severing defects, and method of manufacturing the semiconductor package

Family Cites Families (166)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62107391A (ja) 1985-11-06 1987-05-18 Nippon Texas Instr Kk 情報記憶媒体
JPH02174255A (ja) 1988-12-27 1990-07-05 Mitsubishi Electric Corp 半導体集積回路装置
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5369552A (en) 1992-07-14 1994-11-29 Ncr Corporation Multi-chip module with multiple compartments
US5998864A (en) 1995-05-26 1999-12-07 Formfactor, Inc. Stacking semiconductor devices, particularly memory chips
US5861666A (en) 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US5892660A (en) 1996-08-29 1999-04-06 Micron Technology, Inc. Single in line memory module adapter
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6742098B1 (en) 2000-10-03 2004-05-25 Intel Corporation Dual-port buffer-to-memory interface
US6021048A (en) 1998-02-17 2000-02-01 Smith; Gary W. High speed memory module
US6150724A (en) 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US7525813B2 (en) 1998-07-06 2009-04-28 Renesas Technology Corp. Semiconductor device
US6353539B1 (en) 1998-07-21 2002-03-05 Intel Corporation Method and apparatus for matched length routing of back-to-back package placement
US6121576A (en) 1998-09-02 2000-09-19 Micron Technology, Inc. Method and process of contact to a heat softened solder ball array
US6201695B1 (en) 1998-10-26 2001-03-13 Micron Technology, Inc. Heat sink for chip stacking applications
US6815251B1 (en) 1999-02-01 2004-11-09 Micron Technology, Inc. High density modularity for IC's
SE519108C2 (sv) 1999-05-06 2003-01-14 Sandvik Ab Belagt skärverktyg för bearbetning av grått gjutjärn
TW409377B (en) 1999-05-21 2000-10-21 Siliconware Precision Industries Co Ltd Small scale ball grid array package
KR100393095B1 (ko) 1999-06-12 2003-07-31 앰코 테크놀로지 코리아 주식회사 반도체패키지와 그 제조방법
JP3360655B2 (ja) 1999-07-08 2002-12-24 日本電気株式会社 半導体装置
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6369448B1 (en) 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6414396B1 (en) 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
JP3768761B2 (ja) 2000-01-31 2006-04-19 株式会社日立製作所 半導体装置およびその製造方法
JP2001223324A (ja) 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6731009B1 (en) 2000-03-20 2004-05-04 Cypress Semiconductor Corporation Multi-die assembly
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6592109B2 (en) 2000-07-31 2003-07-15 Toyo Tire & Rubber Co., Ltd. Liquid sealing type body mount
JP2002076252A (ja) 2000-08-31 2002-03-15 Nec Kyushu Ltd 半導体装置
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
JP3462166B2 (ja) 2000-09-08 2003-11-05 富士通カンタムデバイス株式会社 化合物半導体装置
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
SG95637A1 (en) 2001-03-15 2003-04-23 Micron Technology Inc Semiconductor/printed circuit board assembly, and computer system
SG106054A1 (en) 2001-04-17 2004-09-30 Micron Technology Inc Method and apparatus for package reduction in stacked chip and board assemblies
JP2002353398A (ja) 2001-05-25 2002-12-06 Nec Kyushu Ltd 半導体装置
US6472741B1 (en) 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same
JP2003101207A (ja) 2001-09-27 2003-04-04 Nec Kyushu Ltd 半田ボールおよびそれを用いた部品接続構造
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
SG118103A1 (en) 2001-12-12 2006-01-27 Micron Technology Inc BOC BGA package for die with I-shaped bond pad layout
KR100480909B1 (ko) 2001-12-29 2005-04-07 주식회사 하이닉스반도체 적층 칩 패키지의 제조 방법
TW523890B (en) 2002-02-07 2003-03-11 Macronix Int Co Ltd Stacked semiconductor packaging device
US7196415B2 (en) 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
DE10215654A1 (de) 2002-04-09 2003-11-06 Infineon Technologies Ag Elektronisches Bauteil mit mindestens einem Halbleiterchip und Flip-Chip-Kontakten sowie Verfahren zu seiner Herstellung
JP4149438B2 (ja) 2002-06-05 2008-09-10 株式会社ルネサステクノロジ 半導体装置
JP2004063767A (ja) * 2002-07-29 2004-02-26 Renesas Technology Corp 半導体装置
US6762942B1 (en) 2002-09-05 2004-07-13 Gary W. Smith Break away, high speed, folded, jumperless electronic assembly
TW557556B (en) 2002-09-10 2003-10-11 Siliconware Precision Industries Co Ltd Window-type multi-chip semiconductor package
AU2003301632A1 (en) 2002-10-22 2004-05-13 Unitive International Limited Stacked electronic structures including offset substrates
US7268425B2 (en) 2003-03-05 2007-09-11 Intel Corporation Thermally enhanced electronic flip-chip packaging with external-connector-side die and method
TW200419752A (en) 2003-03-18 2004-10-01 United Test Ct Inc Semiconductor package with heat sink
US7528421B2 (en) 2003-05-05 2009-05-05 Lamina Lighting, Inc. Surface mountable light emitting diode assemblies packaged for high temperature operation
KR20050001159A (ko) 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
SG148877A1 (en) 2003-07-22 2009-01-29 Micron Technology Inc Semiconductor substrates including input/output redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7061121B2 (en) 2003-11-12 2006-06-13 Tessera, Inc. Stacked microelectronic assemblies with central contacts
US7095104B2 (en) 2003-11-21 2006-08-22 International Business Machines Corporation Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
US7176043B2 (en) 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
JP2005251957A (ja) 2004-03-04 2005-09-15 Renesas Technology Corp 半導体装置
US7489517B2 (en) 2004-04-05 2009-02-10 Thomas Joel Massingill Die down semiconductor package
US7078808B2 (en) 2004-05-20 2006-07-18 Texas Instruments Incorporated Double density method for wirebond interconnect
US7525189B2 (en) 2004-05-21 2009-04-28 Nec Corporation Semiconductor device, wiring board, and manufacturing method thereof
KR20050119414A (ko) 2004-06-16 2005-12-21 삼성전자주식회사 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법
KR20060004298A (ko) 2004-07-09 2006-01-12 삼성테크윈 주식회사 무선 전자 라벨
US7381593B2 (en) 2004-08-05 2008-06-03 St Assembly Test Services Ltd. Method and apparatus for stacked die packaging
JP4445351B2 (ja) 2004-08-31 2010-04-07 株式会社東芝 半導体モジュール
JP4601365B2 (ja) * 2004-09-21 2010-12-22 ルネサスエレクトロニクス株式会社 半導体装置
US20060097400A1 (en) 2004-11-03 2006-05-11 Texas Instruments Incorporated Substrate via pad structure providing reliable connectivity in array package devices
US7786567B2 (en) 2004-11-10 2010-08-31 Chung-Cheng Wang Substrate for electrical device and methods for making the same
US7217994B2 (en) 2004-12-01 2007-05-15 Kyocera Wireless Corp. Stack package for high density integrated circuits
TWI256092B (en) 2004-12-02 2006-06-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
JP2006172122A (ja) 2004-12-15 2006-06-29 Toshiba Corp カード状記憶装置
US7755179B2 (en) 2004-12-20 2010-07-13 Semiconductor Components Industries, Llc Semiconductor package structure having enhanced thermal dissipation characteristics
JP4086068B2 (ja) 2004-12-27 2008-05-14 日本電気株式会社 半導体装置
KR20060080424A (ko) 2005-01-05 2006-07-10 삼성전자주식회사 멀티 칩 패키지를 장착하는 메모리 카드
US7205656B2 (en) * 2005-02-22 2007-04-17 Micron Technology, Inc. Stacked device package for peripheral and center device pad layout device
US7196427B2 (en) 2005-04-18 2007-03-27 Freescale Semiconductor, Inc. Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element
US7250675B2 (en) 2005-05-05 2007-07-31 International Business Machines Corporation Method and apparatus for forming stacked die and substrate structures for increased packing density
KR101070913B1 (ko) 2005-05-19 2011-10-06 삼성테크윈 주식회사 반도체 칩 적층 패키지
US7402911B2 (en) 2005-06-28 2008-07-22 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
SG130066A1 (en) * 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP4108701B2 (ja) 2005-09-12 2008-06-25 株式会社ルネサステクノロジ Ｉｃカードの製造方法
US7602054B2 (en) 2005-10-05 2009-10-13 Semiconductor Components Industries, L.L.C. Method of forming a molded array package device having an exposed tab and structure
US20070152310A1 (en) 2005-12-29 2007-07-05 Tessera, Inc. Electrical ground method for ball stack package
JP2007188916A (ja) 2006-01-11 2007-07-26 Renesas Technology Corp 半導体装置
KR100690247B1 (ko) 2006-01-16 2007-03-12 삼성전자주식회사 이중 봉합된 반도체 패키지 및 그의 제조 방법
US20070176297A1 (en) 2006-01-31 2007-08-02 Tessera, Inc. Reworkable stacked chip assembly
WO2007088757A1 (ja) 2006-02-02 2007-08-09 Matsushita Electric Industrial Co., Ltd. メモリカードおよびメモリカードの製造方法
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
KR20070088177A (ko) 2006-02-24 2007-08-29 삼성테크윈 주식회사 반도체 패키지 및 그 제조 방법
US20080029879A1 (en) 2006-03-01 2008-02-07 Tessera, Inc. Structure and method of making lidded chips
US7514780B2 (en) 2006-03-15 2009-04-07 Hitachi, Ltd. Power semiconductor device
US7368319B2 (en) 2006-03-17 2008-05-06 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7768075B2 (en) 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
CN100511588C (zh) 2006-04-14 2009-07-08 泰特科技股份有限公司 导线架型芯片级封装方法
SG136822A1 (en) * 2006-04-19 2007-11-29 Micron Technology Inc Integrated circuit devices with stacked package interposers
TW200743190A (en) 2006-05-10 2007-11-16 Chung-Cheng Wang A heat spreader for electrical device
JP5026736B2 (ja) 2006-05-15 2012-09-19 パナソニックヘルスケア株式会社 冷凍装置
WO2008007257A2 (en) 2006-06-20 2008-01-17 Nxp B.V. Integrated circuit and assembly therewith
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
TWI306658B (en) 2006-08-07 2009-02-21 Chipmos Technologies Inc Leadframe on offset stacked chips package
US7638868B2 (en) 2006-08-16 2009-12-29 Tessera, Inc. Microelectronic package
US7906844B2 (en) 2006-09-26 2011-03-15 Compass Technology Co. Ltd. Multiple integrated circuit die package with thermal performance
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
JP4389228B2 (ja) * 2006-11-29 2009-12-24 エルピーダメモリ株式会社 メモリモジュール
US7772683B2 (en) 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
WO2008076790A2 (en) * 2006-12-14 2008-06-26 Rambus Inc. Multi-die memory device
US20100071944A1 (en) 2006-12-19 2010-03-25 Tessera Interconnect Materials, Inc. Chip capacitor embedded pwb
JP2008177241A (ja) 2007-01-16 2008-07-31 Toshiba Corp 半導体パッケージ
WO2008093414A1 (ja) 2007-01-31 2008-08-07 Fujitsu Microelectronics Limited 半導体装置及びその製造方法
JP5285224B2 (ja) * 2007-01-31 2013-09-11 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 回路装置
JP2008198841A (ja) 2007-02-14 2008-08-28 Elpida Memory Inc 半導体装置
JP2008235576A (ja) 2007-03-20 2008-10-02 Fujitsu Ltd 電子部品の放熱構造及び半導体装置
US7872356B2 (en) 2007-05-16 2011-01-18 Qualcomm Incorporated Die stacking system and method
US20080296717A1 (en) 2007-06-01 2008-12-04 Tessera, Inc. Packages and assemblies including lidded chips
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
US7619901B2 (en) 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR101341566B1 (ko) 2007-07-10 2013-12-16 삼성전자주식회사 소켓, 검사 장치, 그리고 적층형 반도체 소자 제조 방법
US20090071707A1 (en) 2007-08-15 2009-03-19 Tessera, Inc. Multilayer substrate with interconnection vias and method of manufacturing the same
US20090148594A1 (en) 2007-08-15 2009-06-11 Tessera, Inc. Interconnection element with plated posts formed on mandrel
US8299626B2 (en) 2007-08-16 2012-10-30 Tessera, Inc. Microelectronic package
US7442045B1 (en) 2007-08-17 2008-10-28 Centipede Systems, Inc. Miniature electrical ball and tube socket with self-capturing multiple-contact-point coupling
US20090051043A1 (en) 2007-08-21 2009-02-26 Spansion Llc Die stacking in multi-die stacks using die support mechanisms
US7872340B2 (en) 2007-08-31 2011-01-18 Stats Chippac Ltd. Integrated circuit package system employing an offset stacked configuration
WO2009045371A2 (en) 2007-09-28 2009-04-09 Tessera, Inc. Flip chip interconnection with double post
US7880310B2 (en) * 2007-09-28 2011-02-01 Intel Corporation Direct device attachment on dual-mode wirebond die
US7851267B2 (en) 2007-10-18 2010-12-14 Infineon Technologies Ag Power semiconductor module method
US8345431B2 (en) 2008-01-02 2013-01-01 Microelectronics Assembly Technologies, Inc. Thin multi-chip flex module
JP5207868B2 (ja) 2008-02-08 2013-06-12 ルネサスエレクトロニクス株式会社 半導体装置
US8138610B2 (en) 2008-02-08 2012-03-20 Qimonda Ag Multi-chip package with interconnected stacked chips
US8354742B2 (en) 2008-03-31 2013-01-15 Stats Chippac, Ltd. Method and apparatus for a package having multiple stacked die
US8159052B2 (en) 2008-04-10 2012-04-17 Semtech Corporation Apparatus and method for a chip assembly including a frequency extending device
US7928562B2 (en) 2008-07-22 2011-04-19 International Business Machines Corporation Segmentation of a die stack for 3D packaging thermal management
US8253231B2 (en) * 2008-09-23 2012-08-28 Marvell International Ltd. Stacked integrated circuit package using a window substrate
KR101479461B1 (ko) 2008-10-14 2015-01-06 삼성전자주식회사 적층 패키지 및 이의 제조 방법
JP5056718B2 (ja) 2008-10-16 2012-10-24 株式会社デンソー 電子装置の製造方法
US8049339B2 (en) 2008-11-24 2011-11-01 Powertech Technology Inc. Semiconductor package having isolated inner lead
US7951643B2 (en) 2008-11-29 2011-05-31 Stats Chippac Ltd. Integrated circuit packaging system with lead frame and method of manufacture thereof
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US20100193930A1 (en) 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
KR101566407B1 (ko) * 2009-03-25 2015-11-05 삼성전자주식회사 적층 메모리 소자
TWI401785B (zh) 2009-03-27 2013-07-11 Chipmos Technologies Inc 多晶片堆疊封裝
US8039316B2 (en) 2009-04-14 2011-10-18 Stats Chippac Ltd. Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof
KR101601847B1 (ko) 2009-05-21 2016-03-09 삼성전자주식회사 반도체 패키지
KR20100134354A (ko) 2009-06-15 2010-12-23 삼성전자주식회사 반도체 패키지, 스택 모듈, 카드 및 전자 시스템
TWM370767U (en) 2009-06-19 2009-12-11 fu-zhi Huang Modulized computer
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US20110085304A1 (en) 2009-10-14 2011-04-14 Irvine Sensors Corporation Thermal management device comprising thermally conductive heat spreader with electrically isolated through-hole vias
US10128206B2 (en) 2010-10-14 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8378478B2 (en) 2010-11-24 2013-02-19 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts
KR101061531B1 (ko) 2010-12-17 2011-09-01 테세라 리써치 엘엘씨 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체
US8304881B1 (en) * 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US8338963B2 (en) 2011-04-21 2012-12-25 Tessera, Inc. Multiple die face-down stacking for two or more die
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8436457B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8723327B2 (en) 2011-10-20 2014-05-13 Invensas Corporation Microelectronic package with stacked microelectronic units and method for manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010035451A1 (en) * 1999-08-19 2001-11-01 Michael Bettinger Apparatuses for forming wire bonds from circuitry on a substrate to a semiconductor chip, and methods of forming semiconductor chip assemblies
US6385049B1 (en) * 2001-07-05 2002-05-07 Walsin Advanced Electronics Ltd Multi-board BGA package
CN101000903A (zh) * 2006-01-11 2007-07-18 三星Techwin株式会社 印刷电路板以及利用其制造半导体封装的方法
US20080093725A1 (en) * 2006-10-18 2008-04-24 Samsung Electronics Co., Ltd. Semiconductor package preventing warping and wire severing defects, and method of manufacturing the semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107845628A (zh) * 2016-09-19 2018-03-27 通用电气公司 集成电路器件及其组装方法
CN107845628B (zh) * 2016-09-19 2020-09-25 通用电气公司 集成电路器件及其组装方法

Also Published As

Publication number Publication date
TW201248809A (en) 2012-12-01
US20130056870A1 (en) 2013-03-07
WO2012145114A1 (en) 2012-10-26
KR20140028015A (ko) 2014-03-07
US20140042644A1 (en) 2014-02-13
CN103620774B (zh) 2016-10-05
US9093291B2 (en) 2015-07-28
US8436458B2 (en) 2013-05-07
US8304881B1 (en) 2012-11-06
JP2014514766A (ja) 2014-06-19
TWI523174B (zh) 2016-02-21
US20120267797A1 (en) 2012-10-25
EP2700097A1 (en) 2014-02-26

Similar Documents

Publication Publication Date Title
CN103620774A (zh) 倒装芯片、正面和背面线键合相组合的封装
TWI479630B (zh) 具中心接觸件之增強堆疊微電子總成以及其之系統、模組及配置
US9515053B2 (en) Microelectronic packaging without wirebonds to package substrate having terminals with signal assignments that mirror each other with respect to a central axis
US8980693B2 (en) Stackable microelectronic package structures
US9312239B2 (en) Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
CN103620778B (zh) 倒装芯片、正面和背面中心键合存储线键合组件
US20170263540A1 (en) Stacked chip-on-board module with edge connector
EP2764513B1 (en) Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
CN104885217A (zh) 两个或多个晶元的多晶元堆叠
US11929337B2 (en) 3D-interconnect
CN112614830A (zh) 一种封装模组及电子设备
KR101811738B1 (ko) 중앙 콘택을 구비한 적층형 마이크로전자 조립체
TWI395319B (zh) 避免封裝堆疊接點斷裂之半導體組合構造

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20161005

Termination date: 20180321

CF01 Termination of patent right due to non-payment of annual fee