CN1034826A - 在半导体片表面具有金属导线迹的半导体器件的制造方法 - Google Patents
在半导体片表面具有金属导线迹的半导体器件的制造方法 Download PDFInfo
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Abstract
一种制造半导体器件的方法,该器件的半导体片
具有由半导体区和其周围的氧化区所构成的表面,在
表面上制备金属层,以这层金属层形成导线迹,然后,
把氧化硅绝缘层淀积在表面上的导线迹上。根据本
发明,在把氧化硅层制备在导线迹上之前,这种导线
迹上制备有防氧化材料的顶层。由于制备了顶层,避
免了氧化硅复盖的导线迹产生高电阻甚至电学断路
的可能。
Description
本发明涉及一种半导体器件的制造方法,该器件的半导体片具有由半导体区与其周围的氧化区构成的表面,在此表面上有用金属层形成的导线迹(conductor track),然后在该表面的半导体部份上淀积一层氧化硅绝缘层。
能够这样来制备导线迹使它既在半导体区上方又在氧化区上方伸展,并与半导体区连接,所以,例如,导线迹就与位于半导体区内的场效应晶体管的源区或漏区相连接。然后导线可以进一步通过淀积复盖在导线上的氧化硅绝缘层上的联接窗口而与金属层相连接,该金属层制备于氧化硅绝缘层之上。该导线也可进一步地连接到也制备于半导体的表面上的多晶硅的导线迹上。于是这两种导线迹可以用一层氧化硅的绝缘层复盖。因此,例如,一个制备于半导体区内的场效应晶体管的漏区或源区可以连接到另一个制备于半导体片上的场效应管的栅极上。然而,导线迹也可以这样布置,以使它仅在氧化区上方或仅在半导体区上方延伸。在这些情况下,可以用它来形成不同的内部连线。
欧洲专利申请No.190070在开始一段公开了一种与上述类似的一种方法。在该专利中用钛、钒、铬、锆、铌、钼、铪、钽或钨层形成导线迹。氧化硅绝缘层可以用已知的淀积氧化硅的各种方法淀积在半导体片表面的导线迹上。
实际上,已经发现,利用现有的方法可能会引起一些问题。例如,被氧化硅复盖的导线迹会具有比根据其性质所预料的金属线迹大得多的电阻。在某些情况,人们也已发现,导线迹甚至被完全断开。如果采用获得优良阶梯复盖的淀积工艺来制备氧化硅层的话,这个问题尤其明显。然而,在制造具有电路元件的半导体器件(例如具有亚微米尺度的场效应管)时,这种淀积工艺是非常必要的。
因为本发明的目的特别是改进开头一段所提及的方法,从而,能够借助于一种淀积工艺将氧化硅层淀积在半导体片表面的金属导线迹上,既能获得优良的阶梯复盖,而导线迹又不会产生不良的电学性能。
为此目的,本发明的方法其特征在于:在导线迹表面上制备氧化硅层之前,先在导线迹上制备一层防氧化材料的顶层。
本发明基于对以下事实的认识:即在采用能获得优良阶梯复盖性的淀积工艺淀积氧化硅的过程中,钛、钒、铬、锆、铌、钼、铪、钽或钨的导线迹很容易被氧化。在这种工艺中,半导体片被加热到650℃以上,同时含硅的混合气体通过半导体片,实际上该混合气体总是含有氧化性组分,例如在含有二氯甲硅烷的混合气体中,要么含有含氧的杂质,要么含有氧的化合物,在这种条件下该金属容易被氧化。当温度低于450℃时,这类情况实际上不会发生。但是在此温度时也不能淀积具有优良阶梯复盖性的氧化硅层。由于所说的氧化作用,导线迹的电阻会变得很高,甚至完全断开,从而被破坏。
依据本发明提供的措施,在氧化硅绝缘层沉积过程中,导线迹的此种氧化作用可以被阻止。
可以利用氮化硅或氧化硅来制造防氧化的顶层。然而,由于上述原因此种防氧化顶层应在低温下沉积,比如,通过等离电体淀积工艺而制备。但是这种淀积层的阶梯复盖性差。
本发明的一种优化实施例其特征在于:导线迹上有一层非晶硅的防氧化顶层。这种非晶硅层可利用溅射淀积工艺很容易在较低的温度下淀积而成并具有良好的阶梯复盖,或者利用另一种淀积工艺,在此工艺中非晶硅由含甲硅烷的蒸汽淀积而成。在后一种工艺中,金属表面对甲硅烷的分解反应起催化作用,所以这种反应可以在低于450℃的温度下发生。事实上,是在上述金属不被氧化的条件下实施这些工艺的。进一步还发现,在氧化硅在导线迹上淀积的过程中,非晶硅本身基本上没有氧化。还发现,此顶层非常致密以致于实际上观察不到下面金属的氧化。
根据本发明,最好在导线迹上制备厚度至少为3毫微米的非晶硅顶层。已发现,具有该最小厚度的非晶硅层充分地保护了下面金属不被氧化。
根据本发明,以非常适用的手段制备具有顶层的导线迹的一种方法,其特征在于:导线迹以具有顶层的形式来制备,其中先将防氧化材料制备于表面上的金属层上,然后将并列的两层蚀刻成与导线迹相同的图形。金属层和防氧化层都可以利用溅射工艺淀积得到。这两层都可以在一次工艺步骤中在同一设备中得到。
更进一步,最好首先将防氧化层蚀刻成图形,随后把防氧化材料层的图形盖住,同时进行蚀刻,在下面的金属层中就得到相同的图形。这样顶层形成厚度例如为5毫微米的很薄的掩模。结果,底下的金属层可以被通过掩模开口的液态蚀刻剂很好地浸湿。结果,例如能够形成相当窄的导线迹,导线迹的间距可小于1微米。举例来讲,与非晶硅的顶层相比,这些金属层可以在过氧化氢溶液中非常有选择性地被蚀刻掉。
最好是更进一步地用添加钛和氮的钨层形成导线迹。由于钨和钛的混合物中添加了氮,在氧化硅层淀积过程中,金属层的侧向氧化大大减弱。与添加氮的导线迹相比,没有加氮的导线迹其未被顶层复盖的侧边的氧化要激烈的多。结果,导线迹具有不规则的边缘,添加氮则可以避免这一点。
利用实例,参考附图,下面将对本发明作更完整的描述。图中:
图1至8表示了用本发明的方法所获得的半导体器件的几个连续的制造步骤。开始的材料是半导体片1,它具有表面2,表面2与P型硅构成的半导体区3以及围绕着3的氧化区4邻接。氧化区4可以用通常的方法将硅局部氧化获得。它也可以用氧化硅填充半导体片中刻出的沟槽来制备。如本例所示,表面2可以位于半导体区3和氧化区4以上的同一平面上,然而,它也可以位于比半导体区3高一点的氧化区4之上。在所说的第一种情况下,有时使用“埋区氧化”这个词。
在附图中,只表示了单个的半导体区3被氧化区4所包围。然而,实际上一块半导体片可包含极大量的这类半导体区。例如,每一个半导体区都可以包含一个电路元件,比如一个场效应管。在此处所给的例子中,将场效应管位于半导体区3中。
在通常情况下,在表面2上用一栅氧化层5将多晶硅与半导体区3相绝缘而制成栅极6。图中还示出了一个多晶硅导线迹7,它置于氧化区4上面。例如,这个导线迹7构成了位于邻近的半导体区中的场效应管的栅极。在栅极6和导线迹7形成之后,用通常的方法注入BF2离子形成半导体区8和9。离子的注入能量约为55Kev,剂量约为2.1015离子/厘米2。用栅极6和氧化区4作为一个注 入掩模。半导体区8和9现在可作为场效应管的源区和漏区。在半导体区8和9形成后,在整块半导体片上沉积氧化硅层,在栅极6和导线迹7的边缘形成绝缘层10,然后对此氧化硅层进行各向异性的蚀刻处理,掌握蚀刻的时间只让边缘的绝缘层10保留下来。
为了使具有低电阻率的半导体区8和9能被连接,最好使8和9带有金属硅化物的顶层12。用能与硅形成硅化物的金属层11复盖整个半导体表面来实现这一点,此例中用约40毫微米厚的钛作复盖层,然后,基片1在氮化气氛中加热至650℃保持10秒钟。在金属层11与硅接触的区域内形成硅化钛,而在金属层11位于氧化硅上的区域内则形成氮化钛。随后,用氨和过氧化氢的水溶液中除去所形成的氮化钛。然后将基片1在850℃的氮气中再加热10秒钟。这样就制成了带有稳定的硅化钛顶层12的半导体区8和9、栅极6和多晶硅的导线迹7,硅化钛12的方块电阻约2.5到3.5欧姆。栅极6和导线迹7的边界绝缘层10以及氧化区4上没有硅化钛。
在硅化钛的顶层12形成后,在半导体片的表面2上制备金属导线17和18,在半导体区3和氧化区4内形成的半导体区8和9与导线17及18邻接,本例中已经在3和4上制备了栅极6和多晶硅导线7。制备一绝缘氧化硅层19将表面2上的导线17、18复盖。在图17和18中,示出了两个金属导线17和18。导线迹17在半导体区8和氧化区4以及多晶导体7的上方延伸,并将半导体区8和导体7连接起来。导线迹18在半导体9和氧化区4上延伸并通过在氧化硅层19内的窗口20及在窗口20内形成的金属插头21连接到制备在氧化硅层19上的更远的导线22。
将金属层13淀积在表面2上,然后将它蚀刻成与导线迹17、 18相应的图形,从而在表面2上形成导线迹17、18。根据本发明,在导线迹17、18上复盖氧化硅层19之前,将防氧化材料顶层16制备在17、18上。
氧化硅的绝缘层19必须用具有非常好的阶梯复盖性的淀积工艺来制备。在此工艺过程中将半导体基片1加热到650℃以上的温度,同时将含硅混合气体比如四乙氧基硅烷Si(OC2H5)4或者二氯甲硅烷SiH2Cl2与氧的混合物通过半导体块。这样,由钛、钒、铬、锆、铌、钼、铪、钽或钨或合金做成的导线迹17、18在这种条件下很容易氧化。即使在第一个实例子中,最后的气体混合物也含有足够多的氧。因为这些金属导线迹能承受高温,适合制备于氧化硅层的底下,然而它们会具有相当高的电阻,甚至可能发生电学断路。在比450℃低得多的温度下,所说的金属实际上即使在氧化气体混合物中也不会氧化,但是在这样的低温下,无法制备具有良好阶梯复盖性的氧化硅层。由于有了防氧化层16,能够做到将具有良好阶梯复盖性的氧化硅层淀积在导线迹上。
根据本发明,最好将非晶硅顶层16作为防氧化顶层置于导线迹17、18上。利用通常的溅射沉积工艺或利用从含有甲硅烷(SiH4)的蒸汽中淀积非晶硅的工艺很容易在450℃以下的温度淀积出这样的顶层。在第二种情况下,金属表面对于甲硅烷SiH4的分解反应起催化作用。因此这种反应可以在低于450℃的温度下发生。在这些工艺中,所述的金属不会氧化。已经发现,在利用上述有良好阶梯复盖性的工艺之一使氧化硅淀积的过程中,实际上非晶硅的顶层本身不氧化。人们还发现,这样的顶层是很致密的,以致于实际上观察不到下面金属的氧化。
非晶硅的防氧化顶层最好至少具有3毫微米的厚度。具有此厚度的顶层充分地保护了下面金属不被氧化。
用通常的工艺,比如溅射淀积工艺,将钛、钒、铬、锆、铌、钼、铪、钽或钨或它们的混合物做成的金属层13淀积在半导体片1的表面2上来制备带有防氧化层16的导线迹17和18,然后用一层防氧化层材料14将金属层13复盖。随后将这两层金属用常用方法制备的光刻掩模15将其掩蔽蚀刻成与导线迹17相应的图形。最好防氧化材料层14首先被蚀刻成此图形。在清除光刻掩模15后,把保留下来的防氧化材料层16作为将下面金属层13蚀刻为相同图形时的掩模。这样就形成了带有防氧化顶层16的导线迹17。防氧化层14,在本例中是非晶硅层,能在含四氟化碳(CF4)和氧气的混合气体所形成的等离子体中相对于层13被有选择性地蚀刻。金属层13,本例中是含氮的钛钨合金,能在过氧化氢溶液中相对于非晶硅和金属13下面的金属硅化物和氧化硅有选择性地被蚀刻掉。因为层14为厚度在3-50毫微米之间的极薄的掩模,金属层13的未复盖部分能很好地被浸湿。这样,可以得到间距非常小的导线迹(小于1微米)。
举例来说,含氮的钛钨混合物组成的金属层13,其厚度为100毫微米,其中钛钨之比为1∶4,氮的含量为10-30%(原子比),而非晶硅层14厚度大于3毫微米。淀积这层金属是通过,例如在温度为150℃条件下,压强为毫乇的含氩气和氮气的气氛中,其中含氮体积比最多为25%,将钛钨比为1比4的靶溅射。这样,最多有30%原子比的氮结合入金属层中。由于层13中添加了氮,在随后的向整个基片上淀积氧化硅层19的过程中,金属层的 侧向氧化大大地减少了。如果不含氮的钛钨合金层的侧向氧化是300毫微米的话,则厚度相同的含氮合金层的侧向氧化只有140毫微米。
在四乙氧基硅烷的气氛中将基片1加热到大约700℃,在基片1上制备成氧化硅层19。接着,用通常方法将这层平整化。最后,在氧化硅层19上制备接触窗20。窗口20完全处于导线迹18之上,这有其他好处,即在蚀刻步骤中,因为导线迹18能作为阻蚀器,所以下面的氧化区4不会被损坏。
以通常的方法用金属21,例如钨,填充接触窗20,先有选择性地将这种金属淀积在导线迹18上或用厚的金属层完全复盖基片1,然后把它再次蚀刻掉直至氧化硅层,接触窗保持恰好充满的状态。在氧化硅层上,制备另一层金属22例如铝,于是它通过接触窗口20内的金属21与金属导线18和带有半导体区9的金属硅化物层12电连接。
最好在半导体区8、9和在多晶硅栅极6、多晶硅导线迹7上制备了金属硅化物顶层12之后再制备金属层13,以此形成导线17和18。顺序也可以不同,例如,金属层13可以首先在生成金属硅化物的金属层11上形成,然后进行硅化处理。那么,这种处理应该使下金属层11与底下的硅形成金属硅化物,而上金属层13则保持不变。接着,导线迹可以用上金属层形成,然后,底下那层未转变为金属硅化锏慕鹗舨?1的未复盖部分被消除。然而,与以上描述的方法相比,此法的缺点是在硅化处理过程中,半导体带8和9中的硅通过已生成的硅化物扩散,并与未反应的金属形成硅化物。在该方法中,金属硅化物还可能在氧化硅上形成,例如,在栅极6的侧边绝缘 层10上形成,结果,形成了所不希望的短路。本发明的方法避免了这种金属硅化物的过度生长。如上所述,金属硅化物在氮气氛中很短时间内形成。金属层11在其下面无硅的区域,转变为金属氮化物。此金属构成良好的硅扩散位垒,所以,大大抑制了上述的金属硅化物的过度生长。金属硅化物最好在含氮气氛中,温度为600到700℃之间,保温5-20秒钟生成。
人们将了解到本发明并不局限于此处描述的实施例,而且在本发明的范围内可能出现许多进一步的变动。例如,我们描述了在半导体区3内制备场效应管,当然这儿同样可以制造另一种电路元件,比如制造一个双极型晶体管。
Claims (9)
1、一种制造半导体器件的方法,这种半导体器件的半导体片具有由半导体区与其周围的氧化区构成的表面,在此表面上制备一层金属层,以这层金属层形成导线迹,然后在该表面的半导体部分上淀积一层氧化硅绝缘层,该半导体器件的制造方法其特征在于:在导线迹上制备氧化硅层之前,先在导线迹上制备一个防氧化材料的顶层。
2、按照权利要求1所述的方法,其特征在于:导线迹上的防氧化层为非晶硅顶层。
3、按照权利要求2所述的方法,其特征在于:导线迹的非晶硅顶顶层厚度至少为3毫微米。
4、按照以上任何一条权利要求所述的方法,其特征在于:导线迹的制备是通过先在表面层上的金属层上淀积一层防氧化材料的顶层,然后将并列的两层蚀刻成与导线迹相同的图形。
5、按照权利要求4所述的方法,其特征在于首先把防氧化材料层蚀刻成所说的图形,随后利用对防氧化材料层中图形实行掩蔽的同时把底下的金属层蚀刻成相同的图形。
6、按照权利要求5所述的方法,其特征在于:导线迹以添加氮的钨钛混合物层制成。
7、按照权利要求6所述的方法,其特征在于:把10-30%的氮(原子比)添加到含钨和钛的混合物中,其中钨钛之比为1∶4。
8、按照以上权利要求中的任何一条的方法,其特征在于:在制备生成导线迹的金属层之前,至少要把金属硅化物顶层局部地制备在半导体区上。
9、按照权利要求8所述的方法,其特征在于:用热处理的方法,在含氮气氛中,加热到600-700℃之间,保持5-20秒钟,来制备金属硅化物顶层。
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NL8800220A NL8800220A (nl) | 1988-01-29 | 1988-01-29 | Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij een metalen geleiderspoor op een oppervlak van een halfgeleiderlichaam wordt gebracht. |
NL8800220 | 1988-01-29 |
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US (1) | US5366928A (zh) |
EP (1) | EP0326218A1 (zh) |
JP (1) | JP2664757B2 (zh) |
KR (1) | KR0158441B1 (zh) |
CN (1) | CN1016297B (zh) |
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US5418179A (en) * | 1988-05-31 | 1995-05-23 | Yamaha Corporation | Process of fabricating complementary inverter circuit having multi-level interconnection |
JPH0758701B2 (ja) * | 1989-06-08 | 1995-06-21 | 株式会社東芝 | 半導体装置の製造方法 |
US5500557A (en) * | 1992-04-30 | 1996-03-19 | Sgs-Thomson Microelectronics, Inc. | Structure and method for fabricating integrated circuits |
US5444302A (en) * | 1992-12-25 | 1995-08-22 | Hitachi, Ltd. | Semiconductor device including multi-layer conductive thin film of polycrystalline material |
US5589417A (en) * | 1993-01-12 | 1996-12-31 | Texas Instruments, Incorporated | TiSi2 /TiN clad interconnect technology |
US5635426A (en) * | 1993-08-26 | 1997-06-03 | Fujitsu Limited | Method of making a semiconductor device having a silicide local interconnect |
EP0748517A1 (en) * | 1994-02-28 | 1996-12-18 | National Semiconductor Corporation | Providing a low resistance to integrated circuit devices |
US5496750A (en) * | 1994-09-19 | 1996-03-05 | Texas Instruments Incorporated | Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition |
JP2692617B2 (ja) * | 1994-12-06 | 1997-12-17 | 日本電気株式会社 | 半導体装置の製造方法 |
US5607879A (en) * | 1995-06-28 | 1997-03-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for forming buried plug contacts on semiconductor integrated circuits |
JP2001036080A (ja) * | 1999-07-26 | 2001-02-09 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
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US3806361A (en) * | 1972-01-24 | 1974-04-23 | Motorola Inc | Method of making electrical contacts for and passivating a semiconductor device |
US3859127A (en) * | 1972-01-24 | 1975-01-07 | Motorola Inc | Method and material for passivating the junctions of mesa type semiconductor devices |
US4106051A (en) * | 1972-11-08 | 1978-08-08 | Ferranti Limited | Semiconductor devices |
JPS5232270A (en) * | 1975-09-05 | 1977-03-11 | Hitachi Ltd | Passivation film formaion by sputtering |
FR2335951A1 (fr) * | 1975-12-19 | 1977-07-15 | Radiotechnique Compelec | Dispositif semiconducteur a surface passivee et procede d'obtention de la structure de passivation |
JPS5410668A (en) * | 1977-06-25 | 1979-01-26 | Fujitsu Ltd | Production of semiconductor device |
JPS5650533A (en) * | 1979-10-01 | 1981-05-07 | Hitachi Ltd | Semiconductor device |
US4267012A (en) * | 1979-04-30 | 1981-05-12 | Fairchild Camera & Instrument Corp. | Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer |
US4622735A (en) * | 1980-12-12 | 1986-11-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing a semiconductor device utilizing self-aligned silicide regions |
JPS5846644A (ja) * | 1981-09-14 | 1983-03-18 | Oki Electric Ind Co Ltd | 半導体素子 |
JPS5877098A (ja) * | 1981-10-28 | 1983-05-10 | Toshiba Corp | プログラマブル・リ−ド・オンリ・メモリ素子 |
JPS58119669A (ja) * | 1982-01-08 | 1983-07-16 | Seiko Epson Corp | 薄膜半導体装置の製造方法 |
US4491860A (en) * | 1982-04-23 | 1985-01-01 | Signetics Corporation | TiW2 N Fusible links in semiconductor integrated circuits |
US4558507A (en) * | 1982-11-12 | 1985-12-17 | Nec Corporation | Method of manufacturing semiconductor device |
JPS59111152A (ja) * | 1982-12-16 | 1984-06-27 | Sharp Corp | 電子写真用感光体 |
US4570328A (en) * | 1983-03-07 | 1986-02-18 | Motorola, Inc. | Method of producing titanium nitride MOS device gate electrode |
JPS59198734A (ja) * | 1983-04-25 | 1984-11-10 | Mitsubishi Electric Corp | 多層配線構造 |
US4567058A (en) * | 1984-07-27 | 1986-01-28 | Fairchild Camera & Instrument Corporation | Method for controlling lateral diffusion of silicon in a self-aligned TiSi2 process |
JPH0682839B2 (ja) * | 1984-08-21 | 1994-10-19 | セイコー電子工業株式会社 | 表示用パネルの製造方法 |
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US4761386A (en) * | 1984-10-22 | 1988-08-02 | National Semiconductor Corporation | Method of fabricating conductive non-metallic self-passivating non-corrodable IC bonding pads |
DE3686490T2 (de) * | 1985-01-22 | 1993-03-18 | Fairchild Semiconductor | Halbleiterstruktur. |
US4965218A (en) * | 1985-10-21 | 1990-10-23 | Itt Corporation | Self-aligned gate realignment employing planarizing overetch |
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- 1989-01-26 KR KR1019890000785A patent/KR0158441B1/ko not_active IP Right Cessation
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1993
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JP2664757B2 (ja) | 1997-10-22 |
US5366928A (en) | 1994-11-22 |
JPH02205343A (ja) | 1990-08-15 |
NL8800220A (nl) | 1989-08-16 |
EP0326218A1 (en) | 1989-08-02 |
CN1016297B (zh) | 1992-04-15 |
KR890012361A (ko) | 1989-08-26 |
KR0158441B1 (ko) | 1999-02-01 |
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