CN103943553A - 半导体器件和形成具有垂直互连单元的低轮廓扇出式封装的方法 - Google Patents

半导体器件和形成具有垂直互连单元的低轮廓扇出式封装的方法 Download PDF

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CN103943553A
CN103943553A CN201310669363.XA CN201310669363A CN103943553A CN 103943553 A CN103943553 A CN 103943553A CN 201310669363 A CN201310669363 A CN 201310669363A CN 103943553 A CN103943553 A CN 103943553A
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semiconductor element
semiconductor
conductive layer
interconnection
layer
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CN103943553B (zh
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P.C.马里穆图
沈一权
林耀剑
崔源璟
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件和形成具有垂直互连单元的低轮廓扇出式封装的方法。一种半导体器件包括半导体管芯。第一互连结构被设置在半导体管芯的***区上。半导体部件被设置在半导体管芯上。半导体部件包括第二互连结构。半导体部件被设置在半导体管芯上以使第二互连结构与第一互连结构对准。第一互连结构包括多个互连单元，该多个互连单元围绕半导体管芯的第一和第二相邻侧设置以形成互连单元的围绕半导体管芯的L形边界。第三互连结构被形成在半导体管芯上，与第一互连结构垂直。绝缘层被形成在半导体管芯和第一互连结构上。形成通过绝缘层且进入第一互连结构的多个通孔，其中第二互连结构被设置在该通孔内。

Description

半导体器件和形成具有垂直互连单元的低轮廓扇出式封装的方法
要求保护本国优先权
本申请要求保护2012年12月11日提交的美国临时申请No. 61/735,926的权益，通过引用将该申请合并于此。
技术领域
本发明总体上涉及半导体器件，并且更特别地涉及半导体器件以及形成具有垂直互连单元的扇出式封装（fan-out package）或层叠封装（package-on-package）半导体器件的方法。
背景技术
半导体器件常见于现代电子产品中。半导体器件在电气部件的数目和密度方面变化。分立的半导体器件通常包含一种类型的电气部件，例如发光二极管（LED）、小型信号晶体管、电阻器、电容器、电感器以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含几百到几百万个电气部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行许多种功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将太阳光变换成电、以及为电视显示创建视觉投影。半导体器件见于娱乐、通信、功率转换、网络、计算机以及消费者产品的领域中。半导体器件还见于军事应用、飞机制造业、汽车、工业控制器以及办公设备中。
半导体器件利用了半导体材料的电气性质。半导体材料的结构允许通过施加电场或基底电流或者通过掺杂工艺来操纵其电导率。掺杂将杂质引入到半导体材料中以便操纵和控制半导体器件的电导率。
半导体器件包含有源和无源电气结构。包括双极型和场效应晶体管的有源结构控制电流的流动。通过改变掺杂级以及电场或基底电流的施加，晶体管提升或者约束电流的流动。包括电阻器、电容器和电感器的无源结构创建了执行各种各样的电气功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，该电路使半导体器件能够执行高速操作和其他有用功能。
通常使用两个复杂制造工艺（即前端制造和后端制造）来制造半导体器件，该前端制造和后端制造中的每一个都潜在地包括几百个步骤。前端制造包括将多个管芯形成在半导体晶片的表面上。每个半导体管芯通常相同且包含通过电连接有源和无源部件而形成的电路。后端制造包括从完成的晶片单切（singulate）个体半导体管芯以及封装该管芯以提供结构支撑和环境隔离。如这里所使用的术语“半导体管芯”指代该词语的单数和复数形式二者，并且相应地可以指代单个半导体器件和多个半导体器件二者。
半导体制造的一个目标是生产更小半导体器件。更小器件通常耗费更少功率，具有更高性能，并可以被更高效地生产。此外，更小半导体器件具有更小的覆盖区，这对于更小的最终产品来说是期望的。可以通过得到具有更小、更高密度的有源和无源部件的半导体管芯的前端工艺中的改进来实现更小的半导体管芯尺寸。后端工艺可以通过电互连以及封装材料中的改进来得到具有更小覆盖区的半导体器件封装。
对于蜂窝或智能电话产业中的封装来说，减小的封装轮廓特别重要。三维（3D）扇出式半导体封装和外部器件之间的电互连利用各种互连类型，诸如通过再分布层（RDL）的穿透式硅通孔（TSV）和穿孔式通孔（THV）互连。RDL用作包括具有封装输入/输出（I/O）焊盘的电互连的封装内的电互连的中间层，所述封装输入/输出（I/O）焊盘提供从半导体封装内的半导体管芯到半导体封装外的点的电连接。RDL可以被形成在半导体封装之内的半导体管芯的前表面和后表面二者上并且具有薄晶片和面板处理能力。然而，将多个RDL形成在半导体管芯的前表面和后表面上可能需要与定制接合材料的临时接合（这可能需要更高耐热性）并可以是一种用于针对半导体封装进行电互连从而产生更高制造成本的缓慢且昂贵方法。另外，RDL的薄堆叠包括结构限制和降低的设计灵活性。例如，RDL提供了有限的封装处理机械强度和可靠性。RDL缺少模块性且难以在半导体封装的特定区域中形成。
发明内容
存在对在减少RDL应用的情况下形成低轮廓（low profile）3D半导体封装结构的需要。相应地，在一个实施例中，本发明是一种制作半导体器件的方法，其包括下述步骤：提供半导体管芯；沿着半导体管芯的***区设置第一模块化互连结构；提供半导体部件，其包括在该半导体部件上形成的第二互连结构；以及将该半导体部件设置在半导体管芯上以使第二互连结构与第一模块化互连结构对准。
在另一实施例中，本发明是一种制作半导体器件的方法，其包括下述步骤：提供半导体管芯；以及沿着半导体管芯的第一和第二侧设置模块化互连结构。
在另一实施例中，本发明是一种半导体器件，其包括半导体管芯和在该半导体管芯的表面上形成的第一互连结构。沿着该半导体管芯的***区并且与第一互连结构垂直地设置第二互连结构。
附图说明
图1图示一种印刷电路板（PCB），具有安装到其表面的不同类型的封装；
图2a-2c图示安装到PCB的代表性半导体封装的进一步细节；
图3a-3c图示具有由锯道（saw street）分离的多个半导体管芯的半导体晶片；
图4a-4n图示形成具有3D垂直互连单元的低轮廓扇出式层叠封装结构的工艺；
图5图示具有互连单元的鲁棒半导体封装；
图6a-6h图示具有设置在支撑结构和半导体管芯的相对表面上的互连单元的另一半导体封装；
图7图示具有LGA焊盘的半导体封装的可替换实施例；以及
图8a-8g图示具有在半导体封装和背表面保护层之间形成的RDL的另一半导体封装。
具体实施方式
在以下描述中的一个或多个实施例中参考附图来描述本发明，在附图中，相似的数字表示相同或类似的元件。尽管按照用于实现本发明目的的最佳模式来描述本发明，但是本领域技术人员将认识到，本发明意图覆盖如可被包括在如由如得到下面的公开和附图支持的所附权利要求及其等同物限定的本发明精神和范围内的替换、修改和等同物。
通常使用两个复杂制造工艺（前端制造和后端制造）来制造半导体器件。前端制造包括将多个管芯形成在半导体晶片的表面上。晶片上的每个管芯包含有源和无源电气部件，它们被电连接以便形成功能性电路。有源电气部件（诸如晶体管和二极管）具有控制电流的流动的能力。无源电气部件（诸如电容器、电感器和电阻器）创建执行电路功能所必需的电压和电流之间的关系。
通过一系列工艺步骤（包括掺杂、沉积、光刻、蚀刻以及平坦化）将无源和有源部件形成在半导体晶片的表面上。掺杂通过诸如离子注入或热扩散之类的技术将杂质引入到半导体材料中。掺杂工艺通过响应于电场或基底电流动态地改变半导体材料电导率来修改有源器件中半导体材料的电导率。晶体管包含如使晶体管能够在施加电场或基底电流时提升或约束电流的流动所必需的那样布置的改变掺杂的类型和程度的区。
有源和无源部件由具有不同电气性质的材料的层形成。可以通过各种各样的沉积技术来形成这些层，所述沉积技术部分地由所沉积的材料的类型来确定。例如，薄膜沉积可以包括化学气相沉积（CVD）、物理气相沉积（PVD）、电解电镀以及无电解镀工艺。每个层通常被图案化以便形成有源部件部分、无源部件部分或各部件之间的电连接部分。
后端制造指的是将完成的晶片切割或单切成个体半导体管芯并且然后为了结构支撑和环境隔离而封装该半导体管芯。为了单切半导体管芯，沿着被称为锯道或痕的晶片非功能区对晶片刻痕（score）并使其断裂。使用激光切割工具或锯片来单切晶片。在单切之后，将个体半导体管芯安装到包括用于与其他***部件互连的接触焊盘或管脚的封装衬底。然后将在半导体管芯上形成的接触焊盘连接到封装内的接触焊盘。可以利用焊接凸块、柱形凸块（stud bump）、导电浆料或线接合来进行电连接。将密封剂或其他模制材料沉积在封装上以提供物理支撑和电隔离。然后将完成的封装***到电气***中并且使半导体器件的功能对其他***部件来说可用。
图1图示具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，在所述芯片载体衬底或印刷电路板（PCB）52的表面上安装有多个半导体封装。根据应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。为了说明目的，在图1中示出不同类型的半导体封装。
电子器件50可以是独立的***，其使用半导体封装来执行一个或多个电气功能。可替换地，电子器件50可以是更大***的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数字视频摄像机（DVC）或其他电子通信设备的一部分。可替换地，电子器件50可以是图形卡、网络接口卡或可被***到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、射频（RF）电路、分立器件、或者其他半导体管芯或电气部件。为了使产品被市场接受，小型化和重量减轻是根本的。可以减小半导体器件之间的距离来实现更高密度。
在图1中，PCB 52提供了用于在PCB上安装的半导体封装的结构支撑和电互连的一般衬底。使用蒸发、电解电镀、无电解镀、丝网印刷或其他适合的金属沉积工艺来在表面上或在PCB 52的层内形成导电信号迹线54。信号迹线54提供了半导体封装、所安装的部件以及其他外部***部件中的每一个之间的电通信。迹线54还提供了向每一个半导体封装的电源连接和接地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是一种用于将半导体管芯机械和电附着到中间载体的技术。第二级封装包括将中间载体机械和电附着到PCB。在其他实施例中，半导体器件可以仅具有第一级封装，在其中管芯直接机械和电安装到PCB。
为了说明的目的，在PCB 52上示出若干种类型的第一级封装，包括接合线封装56和倒装芯片58。另外，在PCB 52上示出安装了若干种类型的第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、焊盘栅阵列（LGA, land grid array）66、多芯片模块（MCM）68、四方扁平无引线封装（QFN）70以及四方扁平封装72。根据***需求，被配置有第一和第二级封装方式的任何组合的半导体封装以及其他电子部件的任何组合可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，而其他实施例要求多个互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预制的部件合并到电子器件和***中。因为半导体封装包括完善的功能，所以可以使用不太昂贵的部件和流线型制造工艺来制造电子器件。所得到的器件不太可能出现故障且在制造上不太昂贵，从而导致消费者的成本降低。
图2a-2c示出示例性半导体封装。图2a图示安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区，其包含被实施为根据管芯的电气设计而在管芯内形成且电互连的介电层、导电层、无源器件和有源器件的模拟或数字电路。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在半导体管芯74的有源区内形成的其他电路元件。接触焊盘76是导电材料（诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag）的一个或多个层，并电连接到在半导体管芯74内形成的电路元件。在DIP 64的组装期间，使用金-硅共熔层或粘附材料（诸如热环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装主体包括诸如聚合物或陶瓷之类的绝缘封装材料。导体引线80和接合线82提供半导体管芯74和PCB 52之间的电互连。将密封剂84沉积在封装上以便通过防止湿气和颗粒进入封装且污染半导体管芯74或接合线82来进行环境保护。
图2b图示安装在PCB 52上的BCC 62的进一步细节。使用底部填充或环氧树脂粘附材料92将半导体管芯88安装在载体90上。接合线94提供接触焊盘96和98之间的第一级封装互连。将模塑料或密封剂100沉积在半导体管芯88和接合线94上以便为该器件提供物理支撑和电隔离。使用诸如电解电镀或无电解镀之类的合适金属沉积工艺将接触焊盘102形成在PCB 52的表面上以防止氧化。接触焊盘102被电连接到PCB 52中的一个或多个导电信号迹线54。在BCC 62的接触焊盘98和PCB 52的接触焊盘102之间形成凸块104。
在图2c中，利用倒装芯片方式第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含被实施为根据管芯的电气设计而形成的介电层、导电层、无源器件和有源器件的模拟或数字电路。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及有源区108内的其他电路元件。通过凸块110将半导体管芯58电和机械连接到载体106。
利用使用凸块112的BGA方式第二级封装将BGA 60电和机械连接到PCB 52。通过凸块110、信号线114和凸块112将半导体管芯58电连接到PCB的52中的导电信号迹线54。将模塑料或密封剂116沉积在半导体管芯58和载体106上以便为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电迹线的短导电路径，以便减小信号传播距离、降低电容和改进总体电路性能。在另一实施例中，在没有中间载体106的情况下可以使用倒装芯片方式第一级封装将半导体管芯58直接机械和电连接到PCB 52。
图3a示出具有用于结构支撑的基底衬底材料122（诸如硅、锗、砷化镓、磷化铟或碳化硅）的半导体晶片120。在如上所述通过非有源、管芯间晶片区域或锯道126分离的晶片120上形成多个半导体管芯或部件124。锯道126提供切割区域以便将半导体晶片120单切成个体半导体管芯124。
图3b示出半导体晶片120的一部分的横截面视图。每个半导体管芯124具有背表面或非有源表面128和有源表面130，其包含被实施为根据管芯的电气设计和功能而在管芯内形成且电互连的介电层、导电层、无源器件和有源器件的模拟或数字电路。例如，该电路可以包括一个或多个晶体管、二极管、以及在有源表面130内形成以实施模拟或数字电路（诸如数字信号处理器（DSP）、ASIC、存储器或其他信号处理电路）的其他电路元件。半导体管芯124还可以包含用于RF信号处理的集成无源器件（IPD），诸如电感器、电容器和电阻器。
使用PVD、CVD、电解电镀、无电解镀工艺或其他适合的金属沉积工艺将导电层132形成在有源表面130上。导电层132可以是Al、Cu、Sn、Ni、Au、Ag、Ti、W、Pd、Pt或其他适合的导电材料的一个或多个层。导电层132操作为电连接到有源表面130上的电路的接触焊盘。导电层132可以被形成为在距半导体管芯124的边缘第一距离处并排设置的接触焊盘，如图3b中所示。可替换地，导电层132可以被形成为接触焊盘，该接触焊盘在多个行中偏移以使得第一行接触焊盘被设置成距管芯边缘第一距离，并且与第一行交替的第二行接触焊盘被设置成距管芯边缘第二距离。
使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化将可选绝缘或钝化层134形成在有源表面130上。绝缘层134包含二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）或者具有类似绝缘和结构性质的其他材料的一个或多个层。绝缘层134覆盖有源表面130并且为有源表面130提供保护。通过蚀刻工艺或者通过使用激光器135的激光直接消融（LDA）来去除绝缘层134的一部分以便形成暴露导电层132的开口136且提供后续的电互连。
半导体晶片120经受作为质量控制工艺的一部分的电气测试和检查。人工目视检查和自动化光学***被用来对半导体晶片120执行检查。可以在半导体晶片120的自动化光学分析中使用软件。目视检查方法可以采用诸如扫描电子显微镜、高强度或紫外光、或者金相显微镜之类的设备。针对结构特性（包括翘曲、厚度变化、表面颗粒、不规则性、裂缝、脱层和褪色）来检查半导体晶片120。
半导体管芯124内的有源和无源部件经受对电气性能和电路功能的晶片级处的测试。使用探头或其他测试器件来针对功能和电气参数测试每个半导体管芯124。探头被用来进行与每个半导体管芯124上的节点或接触焊盘132的电接触并向接触焊盘提供电刺激。半导体管芯124对该电刺激做出反应，测量该反应并且将其与预期反应进行比较以测试半导体管芯的功能。电气测试可以包括电路功能、引线完整性、电阻率、连续性、可靠性、结深度、静电放电（ESD）、射频（RF）性能、驱动电流、阈值电流、泄漏电流、以及部件类型所专用的操作参数。半导体晶片120的检查和电气测试使通过的半导体管芯124能够被指定为供在半导体封装中使用的成品管芯（KGD, known good die）。
在图3c中，使用锯片或激光切割工具138通过锯道126将半导体晶片120单切成个体半导体管芯124。可以针对KGD后单切的标识来检查和电气测试该个体半导体管芯124。
图4a-4n关于图1和2a-2c图示使用预制的模块化互连单元形成低轮廓3D半导体封装结构的工艺。图4a示出包含牺牲基底材料（诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其他适合的低成本刚性材料）的载体或临时衬底140的一部分的横截面视图。界面层或双面胶带142被形成在载体140上作为临时粘附接合膜、蚀刻终止层或热释放层。
载体140可以是具有针对多个半导体管芯124的容量的圆形或矩形面板（大于300mm）。载体140可以具有比半导体晶片120的表面积更大的表面积。较大的载体降低了半导体封装的制造成本，因为可以在较大的载体上处理更多半导体管芯从而降低每单位的成本。针对所处理的载体或晶片的尺寸来设计和配置半导体封装和处理设备。
为了进一步降低制造成本，与半导体管芯124的尺寸或半导体晶片120的尺寸无关地选择载体140的尺寸。也就是说，载体140具有固定或标准化尺寸，它可以容纳从一个或多个半导体晶片120单切的各种尺寸半导体管芯124。在一个实施例中，载体140是直径为330mm的圆形。在另一实施例中，载体140是宽为560mm且长为600mm的矩形。半导体管芯124可以具有被放置在标准化载体140上的10mm×10mm的尺度。可替换地，半导体管芯124可以具有被放置在同一标准化载体140上的20mm×20mm的尺度。相应地，标准化载体140可以处理任何尺寸半导体管芯124，这允许后续半导体处理设备针对普通载体而标准化，即与管芯尺寸或引入的晶片尺寸无关。可以使用根据任何引入的晶片尺寸处理任何半导体管芯尺寸的处理工具、设备和材料清单的普通集合来为标准载体设计和配置半导体封装设备。普通或标准化载体140通过减少或消除对基于管芯尺寸或引入的晶片尺寸的专用半导体工艺线的需要来降低制造成本和资本风险。通过从所有半导体晶片中选择用于任何尺寸半导体管芯的预定载体尺寸，可以实施灵活的生产线。
在图4b中，使用例如拾取和放置操作将来自图3c的半导体管芯124安装到载体140的管芯附着区域150，其中有源表面130被定向成朝向载体。可以从KGD选择被安装到管芯附着区域150的半导体管芯124。半导体管芯124被按压到界面层142中以使得绝缘层134的一部分被设置在界面层内且被界面层包围。
图4b还示出预制包括芯衬底572的模块化3D互连单元600，其中形成通过该芯衬底的多个穿透式导电通孔574-575。使用诸如印刷、PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺来将导电层或RDL 576形成在芯衬底572和导电通孔574-575上。导电层576包括Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。导电层576电连接到导电通孔574-575。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝涂覆、滚筒涂覆、层压、烧结或热氧化将绝缘或钝化层578形成在芯衬底572和导电层576上。绝缘层578包括SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、具有填料或纤维或者不具有填料或纤维的聚合物介电抗蚀剂、或者具有类似结构和介电性质的其他材料的一个或多个层。通过LDA、蚀刻或者其他适合的工艺来去除绝缘层578的一部分以便在导电通孔574上暴露导电层576的部分。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝涂覆、滚筒涂覆、层压、烧结或热氧化将绝缘或钝化层582形成在芯衬底572上。绝缘层582包括SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、具有填料或纤维或者不具有填料或纤维的聚合物介电抗蚀剂、或者具有类似结构和介电性质的其他材料的一个或多个层。通过LDA或蚀刻来去除绝缘层582的一部分以便暴露导电通孔574-575的部分。
使用诸如印刷、PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺来将导电层或RDL 580形成在与导电层576相对的导电通孔574和芯衬底572上。导电层580包括Al、Cu、Sn、Ni、Au、Ag、Ti、W、或其他适合导电材料的一个或多个层。导电层580电连接到导电通孔574。可替换地，在形成导电层576和导电层580之后形成通过芯衬底572的导电通孔574。
使用例如具有可选粘附剂的拾取和放置操作来将模块化互连单元600安装到载体140。互连单元600被设置在半导体管芯124的***区中的界面层142上。互连单元600以L形布置而设置在载体140上，在管芯附着区域150的拐角周围且至少部分地沿着半导体管芯124的两个侧的长度，如图4c中所示。互连单元600可以被群集在一起以形成互连单元的连续层，或者被设置在载体140上的隔离和预定部分之上。在一些实施例中，在安装互连单元600之前将半导体管芯124安装到载体140。可替换地，在安装半导体管芯124之前将互连单元600安装到载体140。可以将半导体管芯124和互连单元600同时安装到载体140。
互连单元600是容易地设置在半导体封装内以在半导体管芯124的侧部分上或其周围形成边界、缝隙或框架的模块化垂直互连部件。模块化互连单元600被设置在半导体管芯124周围以便在减少在半导体封装内形成的RDL的数目或数量的同时提供垂直互连。例如，互连单元600在制造步骤期间提供具有改进效率的部分背侧RDL。设置在半导体管芯124周围的互连单元600还在封装期间提供结构支撑并且在施加密封剂和附加半导体部件期间减小移位。互连单元600在提供有价值的垂直互连的同时扩展设计灵活性且减小z方向封装高度。作为各个模块化单元，互连单元600被设置在半导体封装内半导体管芯124周围的具体预定位置处，以便优化半导体封装内的空间。使用互连单元600减少了制造步骤，并大大增加了半导体封装设计的灵活性。
在一些实施例中，互连单元600具有比半导体管芯124的高度或厚度更大的高度。在其他实施例中，互连单元600具有等于或小于半导体管芯的高度或厚度的高度。当邻近半导体管芯124安装互连单元时，间隙或空间152可以保持围绕管芯附着区域150在管芯附着区域150和互连单元600之间。可替换地，管芯附着区域150被分配成使得半导体管芯124邻接或接触互连单元600。
图4d示出具有沉积在半导体管芯124和互连单元600上的密封剂160的复合衬底或重构晶片170。可以将重构晶片170处理成许多类型的半导体封装，包括三维（3D）封装（诸如层叠封装（PoP））、嵌入式晶片级球栅阵列（eWLB）、扇入式晶片级芯片尺寸封装（WLCSP）、重构或嵌入式晶片级芯片尺寸封装（eWLCSP）、扇出式WLCSP、倒装芯片封装或其他半导体封装。根据所得到的半导体封装的规范来配置重构晶片170。载体140上的半导体管芯124之间的距离被优化以便以最低单位成本制造半导体封装。载体140的较大表面积容纳更多半导体管芯124并降低制造成本，因为针对每重构晶片170处理了更多半导体管芯124。被安装到载体140的半导体管芯124的数目可以比从半导体晶片120单切的半导体管芯124的数目更大。载体140和重构晶片170提供了使用来自不同尺寸的半导体晶片120的不同尺寸半导体管芯124制造许多不同类型的半导体封装的灵活性。
使用压缩模制、传递模制、液体密封剂模制、真空层压、旋涂或其他适合的敷料器来将密封剂或模塑料160沉积在半导体管芯124和互连单元600上。可替换地，可以以套式模具（chase mold）将密封剂160形成在重构晶片170上。密封剂160可以是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯、或者具有适当填料的聚合物。密封剂160是非导电的并且在环境上保护半导体器件免于外部元件和污染物。在沉积密封剂160之前，重构晶片170可能经受高压退火工艺。密封剂160被形成在半导体管芯124的背表面128上，并可能在后续的背研磨步骤中变薄。还可以沉积密封剂160以使得密封剂与背表面128共面。半导体管芯124周围的互连单元600在密封期间减小半导体管芯124的移位并在封装期间提供结构支撑。
在图4e中，通过化学蚀刻、机械剥皮、CMP、机械研磨、热烘焙、UV光、激光扫描或湿法脱模来从重构晶片170去除载体140和界面层142，以暴露导电层132、互连单元600和密封剂160。还可以使用可选清洁工艺，诸如激光清洁、干式等离子体或湿法显影。
在图4f中，使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺将绝缘或钝化层174形成在半导体管芯124、密封剂160和互连单元600上。绝缘层174包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、具有填料或者不具有填料的低温（低于260℃）可固化聚合物介电抗蚀剂、或者具有类似绝缘和结构性质的其他材料的一个或多个层。通过LDA、蚀刻或者其他适合的工艺来去除绝缘层174的一部分以便暴露互连单元600和半导体管芯124的导电层132以用于后续电互连。
使用PVD、CVD、电解电镀、无电解镀工艺或其他金属沉积适合工艺来将导电层180形成在绝缘层174、半导体管芯124和互连单元600上。导电层180包含Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。导电层180电连接到导电层132和导电通孔574。导电层180的部分可以根据半导体管芯124的设计和功能而电共用或电隔离，并操作为RDL到扇出且将电连接从半导体管芯延伸到互连单元600。
在图4g中，使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺将绝缘或钝化层182形成在绝缘层174和导电层180上。绝缘层182包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、具有填料或者不具有填料的低温（低于260℃）可固化聚合物介电抗蚀剂、或者具有类似绝缘和结构性质的其他材料的一个或多个层。通过LDA、蚀刻或者其他适合的工艺来去除绝缘层182的一部分以便暴露导电层180以用于后续电互连。
使用PVD、CVD、电解电镀、无电解镀或其他金属沉积适合工艺来将导电层184形成在导电层180和绝缘层182上。导电层184包含Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。导电层184电连接到导电层180。导电层184的部分可以根据半导体管芯124的设计和功能而电共用或电隔离。
在图4h中，使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺将绝缘或钝化层186形成在绝缘层182和导电层184上。绝缘层186包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、具有填料或者不具有填料的低温（低于260℃）可固化聚合物介电抗蚀剂、或者具有类似绝缘和结构性质的其他材料的一个或多个层。通过LDA、蚀刻或者其他适合的工艺来去除绝缘层186的一部分以便暴露导电层184以用于后续电互连。
图4h还示出使用蒸发、电解电镀、无电解镀、落球或丝网印刷工艺将导电凸块材料沉积在导电层184上以及绝缘层186中的开口内。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和其组合与可选的助焊剂溶液。例如，凸块材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用适合的附着或接合工艺将凸块材料接合到导电层184。在一个实施例中，通过将凸块材料加热到其熔点以上来使该凸块材料回流以形成球或凸块188。在一些应用中，凸块188被第二次回流以便改进与导电层184的电接触。在一个实施例中，凸块188被形成在具有湿润层、阻挡层和粘附层的凸块下金属化（UBM）上。凸块还可以被压缩接合到导电层184。凸块188表示能够被形成在导电层184上的一种类型的互连结构。互连结构还可以使用导电浆料、柱形凸块、微凸块或其他电互连。在一些实施例中，在将第二半导体部件设置在半导体管芯124上之后形成凸块188。
综合在一起来看，绝缘层174、182和186以及导电层180、184和凸块188形成互连结构190。在互连结构190内包括的绝缘和导电层的数目取决于电路布线（routing）设计的复杂度并随着该复杂度而变化。相应地，互连结构190可以包括任何数目的绝缘和导电层以促进关于半导体管芯124的电互连。原本将被包括在背侧互连结构或RDL中的元件可以被集成为互连结构190的一部分，以简化制造且降低关于包括前侧和后侧互连或RDL二者的封装的制造成本。
在图4i中，与载体140类似的可选载体或临时衬底202被设置在互连结构190上。载体202可以是背研磨带、支撑带以及包含牺牲基底材料的其他载体，所述牺牲基底材料诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其他适合的低成本刚性材料。载体202可以包括被配置成接纳互连结构190的界面层（诸如双面胶带）。载体202可选地为半导体封装的后续工艺步骤提供附加支撑，如图4i-4n中所示。可替换地，在没有载体202的情况下执行后续工艺步骤。
图4i还示出在利用研磨机206对表面进行平坦化且减小密封剂160的厚度的研磨操作中密封剂160的与凸块188相对的顶表面。还可以使用化学蚀刻或CMP工艺来去除机械损坏并利用背表面128对密封剂160进行平坦化。在一个实施例中，在去除密封剂160的一部分之后，密封剂160具有范围为100μm到400μm的厚度。研磨操作去除密封剂160的一部分向下直到半导体管芯124的背表面128。可替换地，密封剂层160保持在半导体管芯124的背表面128上。在一些实施例中，研磨操作暴露导电层576并可以暴露互连单元600的导电材料574。可替换地，密封剂160的一部分保持在互连单元600上。
在图4j中，绝缘层、聚合物基复合膜或翘曲平衡层210被形成在半导体管芯124的背表面128、密封剂160和互连单元600上。绝缘层210包括环氧树脂、树脂或者具有强化纤维或织物（诸如酚醛棉纸、环氧树脂、树脂、编织玻璃、毛玻璃、聚酯、以及其他强化纤维或织物）的聚合物。在另一实施例中，绝缘层210包含模塑料、具有或不具有填料的聚合物电介质、SiO2、Si3N4、SiON、Ta2O5、Al2O3的一个或多个层、利用编织玻璃纤维增强的聚合物基、或具有类似绝缘和结构性质的其他材料。在另一实施例中，绝缘层210包括预浸料、FR 环氧树脂-4、FR-1、CEM-1或CEM-3的一个或多个层压层。使用具有或不具有热量的真空或压力层压、PVD、CVD、丝网印刷、旋涂、喷涂、注射涂覆、烧结、热氧化或其他适合的工艺来沉积绝缘层210。绝缘层210被选择成具有与Cu的热膨胀系数（CTE）类似的CTE，即在Cu的CTE的10ppm/℃内。针对绝缘层210选择的材料（诸如预浸料）增强半导体封装的总体强度并改进封装翘曲，特别在150℃到260℃的温度处。绝缘层210平衡遍及半导体器件的翘曲并在后续的器件集成期间提供附加的支撑。绝缘层210还保护半导体管芯124的暴露部分。在一些实施例中，半导体管芯124被绝缘层210、密封剂160和互连结构190完全嵌入。
在图4k中，通过LDA、蚀刻或其他适合的工艺去除绝缘层210和密封剂160的一部分，以便形成通过绝缘层210和密封剂160的通孔或开口216，从而暴露互连单元600的导电通孔574。在一些实施例中，通孔216的形成还包括去除绝缘层578的一部分。
在一些实施例中，在形成通孔216之后，使用蒸发、电解电镀、无电解镀、落球、丝网印刷、浆料印刷、喷射或其他适合的工艺将导电凸块材料沉积在通孔216中以及互连单元600上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和其组合与可选的助焊剂溶液。助焊剂溶液是在浸渍工艺中旋涂、模板印刷或涂敷的。助焊剂溶液是具有溶剂的免清洁助焊剂或者水清洁助焊剂。凸块材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用适合的附着或接合工艺将凸块材料接合到互连单元600。在一些实施例中，将凸块材料接合到在导电层576上形成的焊帽。在一个实施例中，通过将凸块材料加热到其熔点以上来使该凸块材料回流以形成球或凸块224，如图4m中所示。在一些应用中，凸块224被第二次回流以便改进与互连单元600的电接触。可以在具有或不具有来自载体202的支撑的情况下以及在具有来自分离载体的支撑的情况下使凸块224回流。在一个实施例中，凸块224被形成在具有湿润层、阻挡层和粘附层的UBM上。凸块224还可以被压缩接合到互连单元600。凸块224表示能够被形成在互连单元600上的一种类型的互连结构。互连结构还可以使用导电浆料、柱形凸块、微凸块、具有Cu芯的焊料球、具有浸渍的焊接浆料或焊接涂覆的Cu球或圆柱、或设置在通孔216内的其他电互连。
凸块224连同互连结构190、互连单元600和半导体管芯124一起形成用于下一级互连的3D互连。在一个实施例中，通过利用在重构晶片级沉积到通孔216中的浆料印刷的表面安装技术（SMT）来形成凸块224。在形成凸块224之后，可以在凸块上以及在凸块周围施加可选聚合物介电浆料堵塞以提供附加的支撑。通过印刷、喷涂、浸渍、喷射或其他适合的工艺来施加聚合物介电浆料堵塞，并且其后跟随有真空下的可选回流或热处理。可替换地，稍后在外部半导体封装上形成凸块，如图4l中所示。
图4k还示出使用锯片或激光切割工具226将复合衬底或重构晶片170单切成各个半导体封装227。通过在将附加的半导体器件安装在重构晶片170上之前单切该重构晶片170，通过将附加的半导体器件安装到各个半导体封装227来完成半导体封装的形成，而不是在重构晶片级完成半导体封装的形成。可替换地，在将附加的半导体器件安装到重构晶片170之后单切该重构晶片170。半导体封装227可能在单切之前或之后经受电气测试。
在将半导体器件单切成各个半导体封装227并且去除载体202之后，将可选载体、载体托盘或临时衬底228设置在互连结构190上，如图4l中所示。可替换地，连同重构晶片170一起单切载体202。载体228包括背研磨带、支撑带以及包含牺牲基底材料的其他载体，所述牺牲基底材料诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其他适合的低成本刚性材料。载体228可以包括被配置成接纳互连结构190和半导体封装227或复合衬底170的界面层、双面胶带和开口。载体228可选地为半导体封装的后续工艺步骤提供附加支撑，如图4l-4n中所示。可替换地，在没有载体228的情况下执行后续工艺步骤。
图4l还示出从与图3a-3c类似的半导体晶片单切的半导体封装、半导体管芯或半导体部件230，其具有背表面252和有源表面254，该有源表面254包含被实施为根据管芯的电气设计和功能而在管芯内形成且电互连的介电层、导电层、无源器件和有源器件的模拟或数字电路。例如，该电路可以包括一个或多个晶体管、二极管、以及在有源表面254内形成以实施模拟电路或数字电路（诸如DSP、ASIC、存储器或其他信号处理电路）的其他电路元件。半导体管芯230还可以包含用于RF信号处理的IPD，诸如电感器、电容器和电阻器。与图3a-3c的半导体管芯124类似地，半导体管芯230在从半导体晶片单切之前或之后经受电气测试。
使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺将绝缘或钝化层255形成在半导体管芯230上。绝缘层255包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有类似绝缘和结构性质的其他材料的一个或多个层。通过LDA、蚀刻或者其他适合的工艺来去除绝缘层255的一部分以用于后续的电互连。
使用PVD、CVD、电解电镀、无电解镀工艺或其他适合的金属沉积工艺来将导电层256形成在有源表面254上。导电层256可以是Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。导电层256操作为电连接到有源表面254上的电路的接触焊盘256。导电层256可以被形成为在距半导体管芯230的边缘第一距离处并排设置的接触焊盘256。可替换地，导电层256可以被形成为接触焊盘，该接触焊盘在多个行中偏移以使得第一行接触焊盘被设置成距管芯边缘第一距离，并且与第一行交替的第二行接触焊盘被设置成距管芯边缘第二距离。
使用蒸发、电解电镀、无电解镀、落球或丝网印刷工艺将导电凸块材料沉积在导电层256上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和其组合与可选的助焊剂溶液。例如，凸块材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用适合的附着或接合工艺将凸块材料接合到导电层256。在一个实施例中，通过将凸块材料加热到其熔点以上来使该凸块材料回流以形成球或凸块258。在一些应用中，凸块258被第二次回流以便改进与导电层256的电接触。在一些实施例中，凸块258被形成在具有湿润层、阻挡层和粘附层的UBM上。凸块还可以被压缩接合或热压缩接合到导电层256。凸块258表示能够被形成在导电层256上的一种类型的互连结构。互连结构还可以使用导电浆料、柱形凸块、微凸块或其他电互连。
在一些实施例中，凸块258形成在导电层256上形成的BGA的一部分。BGA被形成为使得凸块258与通孔216在互连单元600上的定向对准。可替换地，凸块258的第一部分与互连单元600上的通孔216对准，并且凸块258的第二部分与互连单元600隔离或者形成围绕半导体管芯230的附加互连结构的一部分。
使用拾取和放置操作，将半导体管芯230安装到个体半导体封装227，其中有源表面254是朝向通孔216定向的并且凸块258延伸到通孔216中以接触互连单元600。如先前所讨论，可以在堆叠组装之前将凸块224预先形成在通孔216之内（图4m）。在一些应用中，半导体管芯230具有比半导体管芯124的宽度更大的宽度。在已经将半导体管芯230安装到半导体封装227之后，半导体管芯230可以位于半导体管芯124的覆盖区之外或者部分地位于该覆盖区之外。在一些实施例中，互连结构被形成在半导体管芯230的有源表面254上，并且凸块258被形成在互连结构的表面上。在其他实施例中，半导体管芯230不具有凸块258，并且半导体管芯230在互连单元600处通过在通孔216中预先形成的凸块224与个体半导体封装227连接，如图4m中所示。在另一实施例中，半导体管芯230在互连单元600处通过凸块258和互连结构的组合或者通过没有凸块258的互连结构与个体半导体封装227连接。凸块258的形成可以恰在将半导体管芯230安装到个体半导体封装227之前或期间进行。
在将半导体管芯230安装在个体半导体封装227上之前，将底部填充材料260、环氧树脂粘附材料、环氧化合物或模制材料设置在半导体封装227的覆盖区内的绝缘层210上，如图4n中所示。虚线261指示半导体管芯230的管芯附着区域。通过如在个体半导体封装227的覆盖区内的绝缘层210上设置的点的平衡位置来施加底部填充材料260。底部填充材料260在堆叠组装以及将半导体管芯230安装在个体半导体封装227上期间支撑半导体管芯230。可替换地或者与底部填充材料260相结合，将非导电浆料设置在绝缘层210上，以在堆叠组装以及将半导体管芯230安装在个体半导体封装227上期间提供附加支撑。底部填充材料260在安装期间以及在后续的回流工艺期间提供支撑。可选地，可以将底部填充材料260设置在半导体管芯230的有源表面254上。
在一些实施例中，凸块258形成设置在半导体管芯230的有源表面254上的互连结构的一部分以便促进半导体管芯230的重新布线，与互连结构190类似。凸块258可以从互连结构延伸以使得互连结构、凸块258、互连结构190和互连单元600组成从半导体封装227到半导体管芯230形成的L形互连。
在堆叠组装之后或期间，通过化学蚀刻、机械剥皮、CMP、机械研磨、热烘焙、UV光、激光扫描或湿法脱模来去除载体228。可以将可选的密封剂沉积在半导体封装227和半导体管芯230上。
图5示出在与载体228分离之后在半导体管芯230和凸块258安装在半导体管芯124上的情况下使用图4a-4n中所示的工艺形成的半导体封装300。在一些实施例中，半导体管芯230在半导体管芯124上横向偏移，以使得半导体管芯230设置在半导体管芯124的一部分上。互连单元600被设置在半导体封装300之内与互连结构190垂直，并垂直地延伸在互连结构190上。在一些实施例中，凸块258连同互连单元600的高度大于半导体管芯124的厚度。因此，在有源表面254和背表面128之间存在间隙。使绝缘层210介于有源表面254和背表面128之间的间隙中。可替换地，凸块258连同互连单元600的高度等于或小于半导体管芯124的厚度。半导体管芯230的有源表面254可以倚靠在背表面128之上的绝缘层210上，其中在有源表面254和背表面128之间不存在间隙。在背表面128和密封剂160上形成且介于有源表面254和背表面128之间的绝缘层210提供物理支撑，控制总体封装翘曲，并在环境上保护半导体管芯124免于外部元件和污染物。绝缘层210为半导体封装300提供结构支撑，平衡封装上的压力，并在后续的处理和工艺期间减小封装300的翘曲或破裂。
半导体封装300通过互连结构190、互连单元600和凸块258的组合来提供3D垂直电互连。利用减小的背侧RDL来形成垂直互连。互连结构190被形成在半导体管芯124的有源表面130上以及密封剂160上，其中互连结构190的一部分围绕半导体管芯124的***。互连结构190包括形成扇出式互连结构的绝缘和导电层，并包括原本将被包括在背侧RDL或互连结构中的元件。互连单元600提供垂直互连以减小RDL层，并在没有与将完整的RDL层或多个RDL形成在半导体封装300的背侧上相关联的成本和更困难制造工艺的情况下提供部分背侧RDL。在半导体封装300内使用互连单元600提供了设计灵活性且减小了半导体封装300的高度。半导体封装300是低轮廓3D封装结构。
使用预制的模块化互连单元600在封装期间提供了附加的灵活性，因为可以在封装工艺的各种阶段处将互连单元600安装到载体140或半导体封装300。使用粘附剂安装互连单元600不需要在半导体封装300的封装期间将层形成在载体140上。互连单元600是能够设置在半导体封装（诸如半导体封装300）内或从其去除的模块化单元，而不像在半导体封装内形成的层那样。设置在半导体管芯124周围的互连单元600在减少RDL应用的情况下提供了垂直互连。围绕半导体管芯124形成的互连单元600在封装期间提供结构支撑并在施加密封剂160和外部半导体部件（诸如半导体管芯230）期间减小移位。在一些实施例中，从导电层256通过凸块258、互连单元600、导电层180、导电层184到凸块188制成沿垂直平面的连续垂直互连。在减小半导体封装300的高度的同时利用半导体封装300实现了真正的3D互连。作为垂直结构，互连单元600除了提供垂直电互连之外，还可以围绕半导体管芯124的侧部分或***区形成边界、框架、缝隙或其他类似支撑结构。互连单元600减少了在封装内形成的RDL的数量。互连单元600在没有与在半导体封装中形成多个RDL相关联的成本、时间和其他制造约束的情况下提供部分背侧RDL。互连单元600在减小z方向封装高度的同时提供设计灵活性。
可以以与设置在半导体管芯124周围的互连单元600的布局或定向相匹配的定向将凸块258或外部器件（诸如半导体管芯230）的互连结构设置或形成在半导体管芯230上。将凸块258或半导体管芯230的互连结构与互连单元600的布局相匹配减少了制造材料和成本。将互连单元600与凸块258或半导体管芯230的互连结构相匹配提供了一致且可靠的3D垂直互连。在一些实施例中，互连结构190还与半导体管芯124周围的互连单元600的定向相匹配。
通过将互连单元600设置成与堆积（build-up）层和RDL相对来创建垂直互连提供了封装设计的增强灵活性。互连单元600不必设置在整个表面区域上，而是可以作为模块化单元设置在半导体封装300内的定制位置处，这对于其他互连结构来说难以完成。例如，将互连单元600设置在半导体管芯124的第一侧部分上而不是围绕半导体管芯124的第二侧部分可以释放半导体封装300内的宝贵空间并暴露围绕半导体管芯124的第二侧部分以用于附加的电气部件。可替换地，在期望增加的垂直互连密度的情况下，互连单元600可以完全包围半导体管芯124以得到密集却灵活的垂直互连。互连单元600在优化半导体封装300内的空间的同时节省了材料。
图6a-6h图示利用与图4a-4n中的半导体封装300类似的工艺形成的半导体封装的可替换实施例的工艺流程。图6a示出与图4a的载体140类似的包含牺牲基底材料（诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其他适合的低成本刚性材料）的载体或临时衬底308的一部分的横截面视图。界面层或双面胶带310被形成在载体308上作为临时粘附接合膜、蚀刻终止层或热释放层。
图6a示出使用例如拾取和放置操作将来自图3c的半导体管芯124安装到界面层310，其中有源表面130被定向成朝向载体308。可以从KGD选择被安装到管芯附着区域150的半导体管芯124。半导体管芯124被按压到界面层310中以使得绝缘层134的一部分被设置在界面层内且被界面层包围。
利用可选的粘附剂将与互连单元600类似的预制模块化互连单元或互连结构326安装到界面层310。与互连单元600类似，利用处于面板/条带级的典型层压衬底来预制互连单元326并将该互连单元326单切成各个互连单元326。互连单元326包括互连层312、芯衬底323和导电通孔324。互连单元326被设置成距载体边缘一定距离，即，间隙或空间保持在载体边缘和互连单元326之间。可替换地，互连单元326扩展到载体308的边缘。互连单元326被设置成距半导体管芯124一定距离，即，间隙或空间保持在半导体管芯124和互连单元326之间。
互连层312包括芯衬底323上的第一绝缘或钝化层316，其包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有类似绝缘和结构性质的其他材料的一个或多个层。使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成绝缘层316。
互连层312包括使用诸如PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺而在绝缘层316中形成的第一导电层318。导电层318可以是Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。导电层318用作用于互连单元326的Cu焊盘。
互连层312还包括在导电层318和绝缘层316上形成的第二绝缘或钝化层320，其包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有类似绝缘和结构性质的其他材料的一个或多个层。使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成绝缘层320。
互连层312还包括使用诸如PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺而在绝缘层320和导电层318上形成的第二导电层322。导电层322可以是Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。导电层322电连接到导电层318和导电通孔324。根据半导体器件的设计和功能，导电层322的其他部分可以是电共用或电隔离的。
图6b示出围绕半导体管芯124将互连单元326安装到界面层310。互连单元326被安装在界面层310上半导体管芯124的相对侧上，如图6c中所示，其中半导体管芯124的有源表面130被定向成朝向界面层310和与界面层310相对的互连单元326的互连层312。
图6b还示出使用浆料印刷、压缩模制、传递模制、液体密封剂模制、真空层压、旋涂或其他适合的敷料器将密封剂或模塑料325沉积在半导体管芯124、互连单元326、载体308和界面层310上。可替换地，使用套式模具来施加密封剂325。密封剂325可以是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯、或者具有适当填料的聚合物。密封剂325是非导电的并且在环境上保护半导体器件免于外部元件和污染物。密封剂325被形成在半导体管芯124的背表面128上，并可能在后续的背研磨步骤中变薄。
图6c示出在密封剂325之前且在将互连单元326安装到界面层310之后来自图6b的半导体封装的顶视图。在一些实施例中，互连单元326被设置在半导体管芯124的相对侧上。虚线261表示用于半导体管芯230的后续安装的管芯附着区域。
在图6d中，通过化学蚀刻、机械剥皮、化学机械平坦化CMP、机械研磨、热烘焙、UV光、激光扫描或湿法脱模来去除载体308和界面层310。还可以使用可选清洁工艺，诸如激光清洁、干式等离子体或湿法显影。
在图6e中，在密封剂325、有源表面130和互连单元326上形成附加的堆积互连结构330。互连结构330包括在半导体管芯124上互连结构330中形成的腔338。在一些实施例中，腔338是管芯附着区域。在一些实施例中，腔338暴露该腔上的有源表面130以用于随后将半导体管芯230直接安装到半导体管芯124。在一些实施例中，如图6e中所示，互连结构330的变薄部分保持在半导体管芯124上，以使得有源表面130没有被腔338暴露。在互连结构330的形成期间，可以通过部分机械研磨或激光消融来完全去除或部分去除绝缘层327。
互连结构330包括绝缘或钝化层332，其包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有类似绝缘和结构性质的其他材料的一个或多个层。使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成绝缘层332。
互连结构330包括使用诸如PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺而在绝缘层332中形成的导电层334。导电层334可以是Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。在一些实施例中，导电层334的一部分电连接到互连单元326，且导电层334的一部分电连接到有源表面130上的导电层132。根据半导体器件的设计和功能，导电层334的其他部分可以是电共用或电隔离的。
互连结构330还包括使用诸如PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺而在绝缘层332中以及在导电层334上形成的导电层336。导电层336可以是Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。在一些实施例中，导电层336的一部分电连接到导电层334。根据半导体器件的设计和功能，导电层336的其他部分可以是电共用或电隔离的。
在图6f中，密封剂325的与互连结构330相对的表面经受利用研磨机206对表面进行平坦化且减小密封剂325的厚度的研磨操作，从而暴露导电层318。可替换地，使用浅LDA来通过密封剂325暴露互连单元326的导电层318。
在图6g中，将从与图3a-3c类似的半导体晶片单切的半导体封装、半导体管芯或半导体部件230设置在腔338上。使用拾取和放置操作，将半导体管芯230安装在互连结构330的腔338内。半导体管芯230的凸块258被接合到腔338之内且半导体管芯124的有源表面130之上的互连结构330的导电部分（诸如导电层334）。可替换地，腔338暴露有源表面130，且半导体管芯230通过凸块258与有源表面130上的导电层132直接连接。在一些实施例中，半导体管芯230具有小于半导体管芯124的宽度的宽度。在一些实施例中，半导体管芯230被设置在半导体管芯124的覆盖区上。在一些实施例中，半导体管芯230不具有凸块258，并且取而代之，将凸块预先形成在腔338内。
图6g还示出使用印刷、旋涂、喷涂、丝网印刷、模板印刷、喷射、层压或其他适合的工艺在背表面128上形成机械支撑层346。还可以使用可选的清洁工艺，诸如激光清洁、干式等离子体或湿法显影。机械支撑层346的材料包括具有或不具有填料的光敏聚合物介电膜、光敏复合抗蚀剂、非光敏聚合物介电膜、液晶聚合物（LCP）、层压复合膜、具有填料的绝缘浆料、液态模塑料、粒状模塑料、聚酰亚胺、聚合物助焊剂、底部填料或具有类似绝缘和结构性质的其他材料的一个或多个层。使用LDA来去除机械支撑层346的一个或多个部分。机械支撑层346提供结构支撑，平衡半导体封装上的压力，并减小翘曲和破裂。在一个实施例中，在进行激光消融以暴露导电层318之前将机械支撑层346层压在密封剂325和半导体管芯124的背表面128上。
图6h示出作为半导体封装306在半导体管芯124的有源表面130上互连结构330的腔338内安装半导体管芯230。通过化学蚀刻、机械剥皮、化学机械平坦化CMP、机械研磨、热烘焙、UV光、激光扫描或湿法脱模来去除载体308和界面层310。还可以使用可选清洁工艺，诸如激光清洁、干式等离子体或湿法显影。
可选底部填充材料340被设置在半导体管芯230和有源表面130之间围绕凸块258。在一些实施例中，如图6h中所示，半导体管芯230延伸到高于互连结构330的厚度。可替换地，半导体管芯230可以包括下述厚度：该厚度使得在将半导体管芯230安装在腔338内时，背表面252与互连结构330的与在互连单元326上形成的表面相对的表面共面，或低于该表面。互连单元326的至少一部分被密封剂325和互连结构330完全嵌入。
图6h还示出使用蒸发、电解电镀、无电解镀、落球或丝网印刷工艺将导电凸块材料沉积在互连单元326的导电层318上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和其组合与可选的助焊剂溶液。例如，凸块材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用适合的附着或接合工艺将凸块材料接合到导电层318。在一个实施例中，通过将凸块材料加热到其熔点以上来使该凸块材料回流以形成球或凸块348。在一些应用中，凸块348被第二次回流以便改进与导电层318的电接触。在一个实施例中，凸块348被形成在具有湿润层、阻挡层和粘附层的UBM上。凸块还可以被压缩接合到导电层318。凸块348表示能够被形成在导电层318上的一种类型的互连结构。互连结构还可以使用导电浆料、柱形凸块、微凸块或其他电互连。
围绕半导体管芯124设置的模块化互连单元326在减少RDL应用的情况下提供垂直互连。与图4c相类似，沿半导体管芯124的一侧设置或者以围绕半导体管芯124的L形配置而设置的互连单元326在封装期间提供结构支撑并在施加密封剂325和外部半导体部件（诸如半导体管芯230）期间减小移位。互连单元326可以围绕半导体管芯124的一个或多个侧部分或者在半导体管芯124的***区上形成边界、框架、缝隙或其他类似支撑结构。互连单元326减少了在封装内形成的RDL的数量。互连单元326在没有与在半导体封装中形成多个RDL相关联的成本、时间和其他制造约束的情况下提供部分背侧RDL。互连单元326在降低z方向封装高度的同时提供设计灵活性。
可以以与设置在半导体管芯124周围的互连单元326的布局或定向相匹配的定向将凸块258或外部器件（诸如半导体管芯230）的互连结构设置或形成在半导体管芯230上。将凸块258或半导体管芯230的互连结构与互连单元326的布局相匹配减少了制造材料和成本。将互连单元326与凸块258或半导体管芯230的互连结构相匹配提供了一致且可靠的3D垂直互连。
通过将互连单元326设置成与堆积层和RDL相对来创建垂直互连提供了封装设计的增强灵活性。互连单元326不必设置在整个表面区域上，而是可以设置在半导体封装306内的定制位置处，这对于其他互连结构来说难以完成。例如，将互连单元326设置在半导体管芯124的第一侧部分上而不是围绕半导体管芯124的第二侧部分可以释放半导体封装306内的宝贵空间并且暴露围绕半导体管芯124的第二侧部分以用于附加的电气部件。可替换地，在期望增加的垂直互连密度的情况下，互连单元326可以完全包围半导体管芯124以得到密集却灵活的垂直互连。互连单元326帮助节省了材料并且还优化了半导体封装306内的空间。
图7示出利用与图6a-6h中的半导体封装306类似的工艺形成的半导体封装350的可替换实施例。对于半导体封装350，凸块348被去除且用在互连层312上或互连层312内形成的LGA焊盘352代替。LGA焊盘352针对半导体封装350提供I/O而不是凸块348以便减小封装的高度或厚度。
还从半导体封装350去除机械支撑层346。从半导体封装350去除机械支撑层346和凸块348提供了减小的轮廓并减少了制造步骤。在一些实施例中，半导体封装350包括与背表面128、互连层312的底表面以及密封剂325的底表面共面的底表面。由此，针对半导体封装350提供了纤细却鲁棒的轮廓。
图8a-8g图示利用与图6a-6h中图示的半导体封装306类似的工艺形成的半导体封装的可替换实施例的工艺流程。图8a示出包含牺牲基底材料（诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其他适合的低成本刚性材料）的与图4a的载体140类似的载体或临时衬底308的一部分的横截面视图。界面层或双面胶带310被形成在载体308上作为临时粘附接合膜、蚀刻终止层或热释放层。
图8a示出使用例如拾取和放置操作将来自图3c的半导体管芯124安装到界面层310，其中有源表面130被定向成朝向载体308。可以从KGD选择被安装到管芯附着区域150的半导体管芯124。半导体管芯124被按压到界面层310中以使得绝缘层134的一部分被设置在界面层内且被界面层包围。
利用可选的粘附剂将与图6a中的互连单元326类似的预制模块化互连单元或互连结构364安装到界面层310。与互连单元600类似，利用处于面板/条带级的典型层压衬底来预制互连单元364并将互连单元364单切成各个互连单元364。互连单元364包括互连层366、绝缘层362、导电材料363和互连层374。互连单元364被设置成距半导体管芯124一定距离。间隙或空间保持在半导体管芯124和互连单元364之间。
互连层366是互连单元364的一部分并针对互连单元364提供包括Cu焊盘的附加垂直互连。作为互连单元364的一部分，互连层366从互连单元364的覆盖区延伸并处于该覆盖区内。互连层366包括绝缘或钝化层367，其包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有类似绝缘和结构性质的其他材料的一个或多个层。使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成绝缘层367。
互连层366还包括使用诸如PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺而在绝缘层367中形成的导电层368。导电层368可以是Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。
互连层366还包括使用诸如PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺而在绝缘层367中以及在导电层368上形成的导电层370。导电层370可以是Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。在一些实施例中，导电层370的一部分电连接到导电层368。根据半导体器件的设计和功能，导电层370的其他部分可以是电共用或电隔离的。导电层370形成用于互连单元364的Cu焊盘。
与互连层366相对的互连层374是互连单元364的一部分。作为互连单元364的一部分，互连层374从互连单元364的覆盖区延伸并处于该覆盖区内。互连层374包括绝缘或钝化层375，其包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有类似绝缘和结构性质的其他材料的一个或多个层。使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成绝缘层375。
互连层374还包括使用诸如PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺而在绝缘层375中形成的导电层376。导电层376可以是Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。
互连层374还包括使用诸如PVD、CVD、溅射、电解电镀和无电解镀之类的图案化和金属沉积工艺而在绝缘层375中以及在导电层376上形成的导电层378。导电层378可以是Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料的一个或多个层。在一些实施例中，导电层378的一部分电连接到导电层376。根据半导体器件的设计和功能，导电层378的其他部分可以是电共用或电隔离的。
图8b示出围绕半导体管芯124将互连单元364安装到界面层310。互连单元364被安装在半导体管芯124的侧部分上界面层310上。
图8b还示出使用浆料印刷、压缩模制、传递模制、液体密封剂模制、真空层压、旋涂或其他适合的敷料器将密封剂或模塑料372沉积在半导体管芯124、互连单元364、载体308和界面层310上。可替换地，使用套式模具来施加密封剂372。密封剂372可以是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯、或者具有适当填料的聚合物。密封剂372是非导电的并且在环境上保护半导体器件免于外部元件和污染物。密封剂372被形成在半导体管芯124的背表面128上。
在图8c中，在绝缘层375的表面、绝缘层134、有源表面130和密封剂372上形成堆积的互连结构382。互连结构382包括在密封剂372、绝缘层134、绝缘层375、导电层378和有源表面130上形成的绝缘或钝化层383。在一些实施例中，绝缘层383包含具有填料或者不具有填料的低温可固化聚合物介电抗蚀剂（即，在低于260℃处固化）、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构性质的其他材料的一个或多个层。使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺来沉积绝缘层383。通过LDA、蚀刻或者其他适合的工艺来去除绝缘层383的一部分以便在导电层132上形成开口。该开口暴露半导体管芯124的导电层132以用于后续电互连。
导电层384被形成在绝缘层383、绝缘层134上、被形成在半导体管芯124和互连单元364上、并且被设置在绝缘层383中的开口内以填充开口并接触导电层132。导电层384的一个或多个层包括Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料。导电层384的沉积使用PVD、CVD、电解电镀、无电解镀或其他适合的工艺。在一些实施例中，导电层384操作为RDL到扇出且将电连接从半导体管芯124延伸到半导体管芯124外的点（诸如互连单元364）。
绝缘或钝化层385被共形地施加到绝缘层383和导电层384，并遵循绝缘层383和导电层384的轮廓。绝缘层385包含具有填料或者不具有填料的低温可固化聚合物介电抗蚀剂（即，在低于260℃处固化）、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构性质的其他材料的一个或多个层。使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺来沉积绝缘层385。通过暴露或显影工艺、LDA、蚀刻或者其他适合的工艺来去除绝缘层385的一部分以便在绝缘层中形成开口，其暴露导电层384的部分以用于后续电互连。
导电层386被形成在绝缘层385上、被形成在导电层384上、并且被设置在绝缘层385中的开口内以填充开口并接触导电层384。导电层386的一个或多个层包括Al、Cu、Sn、Ni、Au、Ag或其他适合导电材料。导电层386的沉积使用PVD、CVD、电解电镀、无电解镀或其他适合的工艺。在一些实施例中，导电层386操作为RDL到扇出且将电连接从半导体管芯124延伸到半导体管芯124外的点。
在图8d中，密封剂372的与互连结构382相对的表面经受利用研磨机206来减小密封剂372的厚度的研磨操作，与图6f类似。研磨操作暴露导电层370，如图8e中所示。可替换地或与研磨操作相结合，使用浅LDA来通过密封剂372暴露互连单元364的导电层370，如图8e中所示。在一些实施例中，使用化学蚀刻来去除密封剂372的一个或多个部分。图8e还示出使用印刷、旋涂、喷涂、丝网印刷、模板印刷、喷射、层压或其他适合的工艺在背表面128和密封剂372上形成机械支撑层380。还可以使用可选的清洁工艺，诸如激光清洁、干式等离子体或湿法显影。机械支撑层380的材料包括具有或不具有填料的光敏聚合物介电膜、光敏复合抗蚀剂、非光敏聚合物介电膜、LCP、层压复合膜、具有填料的绝缘浆料、液态模塑料、粒状模塑料、聚酰亚胺、聚合物助焊剂、底部填料或具有类似绝缘和结构性质的其他材料的一个或多个层。通过LDA来去除机械支撑层380的一个或多个部分。
在图8f中，绝缘或钝化层388被共形地形成在导电层386和绝缘层385上并遵循导电层386和绝缘层385的轮廓。绝缘层388包含具有填料或者不具有填料的低温可固化聚合物介电抗蚀剂（即，在低于260℃处固化）、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构性质的其他材料的一个或多个层。使用PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其他适合的工艺来沉积绝缘层388。通过暴露或显影工艺、LDA、蚀刻或其他适合的工艺来去除绝缘层388的一部分以便在绝缘层中形成开口390，其暴露导电层386的部分以用于后续电互连。在一些实施例中，绝缘层388包括与密封剂372类似的密封剂。
图8f还示出在绝缘层388中的开口390上设置从与图3a-3c类似的半导体晶片单切的半导体封装、半导体管芯或半导体部件230。使用拾取和放置操作，将半导体管芯230安装在绝缘层388上，以使得凸块258被设置在开口390内以便与导电层386的暴露部分接合。在一些实施例中，半导体管芯230不具有凸块258，并且取而代之，将凸块预先形成在开口390内。
图8g示出作为半导体封装400利用设置在绝缘层388的通孔390内的凸块258在半导体管芯124上安装半导体管芯230。使用蒸发、电解电镀、无电解镀、落球或丝网印刷工艺将导电凸块材料沉积在导电层370上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和其组合与可选的助焊剂溶液。例如，凸块材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用适合的附着或接合工艺将凸块材料接合到导电层370。在一个实施例中，通过将凸块材料加热到其熔点以上来使该凸块材料回流以形成球或凸块392。在一些应用中，凸块392被第二次回流以便改进与导电层370的电接触。在一个实施例中，凸块392被形成在具有湿润层、阻挡层和粘附层的UBM上。凸块还可以被压缩接合到导电层370。凸块392表示能够被形成在导电层370上的一种类型的互连结构。互连结构还可以使用导电浆料、柱形凸块、微凸块或其他电互连。
围绕半导体管芯124设置的模块化互连单元364在减少RDL应用的情况下提供垂直互连。与图4c相类似，沿半导体管芯124的一侧设置或者以围绕半导体管芯124的L形配置而设置的互连单元364在封装期间提供结构支撑并在施加密封剂372和外部半导体部件（诸如半导体管芯230）期间减小移位。互连单元364可以围绕半导体管芯124的一个或多个侧部分或者在半导体管芯124的***区上形成边界、框架、缝隙或其他类似支撑结构。互连单元364增加了结构支撑并在密封期间减小了半导体器件124的移位。互连单元364减少了在封装内形成的RDL的数量。互连单元364在没有与在半导体封装中形成多个RDL相关联的成本、时间和其他制造约束的情况下提供部分背侧RDL。互连单元364在减小z方向封装高度的同时提供设计灵活性。机械支撑层380是背侧保护/平衡层，其针对半导体封装400提供结构支撑，平衡半导体封装400上的压力，并减小半导体封装400的翘曲或破裂。
可以以与设置在半导体管芯124周围的互连单元364的布局或定向相匹配的定向将凸块258或外部器件（诸如半导体管芯230）的互连结构设置或形成在半导体管芯230上。将凸块258或半导体管芯230的互连结构与互连单元364的布局相匹配减少了制造材料和成本。将互连单元364与凸块258或半导体管芯230的互连结构相匹配提供了一致且可靠的3D垂直互连。
通过将互连单元364形成为与堆积层和RDL相对来创建垂直互连提供了封装设计的增强灵活性。互连单元364不必设置在整个表面区域上，而是可以设置在半导体封装400内的定制位置处，这对于其他互连结构来说难以完成。例如，将互连单元364设置在半导体管芯124的第一侧部分上而不是围绕半导体管芯124的第二侧部分可以释放半导体封装400内的宝贵空间并且暴露围绕半导体管芯124的第二侧部分以用于附加的电气部件。可替换地，在期望增加的垂直互连密度的情况下，互连单元364可以完全包围半导体管芯124以得到密集却灵活的垂直互连。互连单元364帮助节省了材料并且还优化了半导体封装400内的空间。
尽管已经详细说明了本发明的一个或多个实施例，但是本领域技术人员将认识到，可以在不偏离如随后的权利要求中所阐述的本发明范围的情况下对这些实施例做出修改和改编。

Claims (15)

1.一种制作半导体器件的方法，包括：
提供半导体管芯；
沿所述半导体管芯的***区设置第一模块化互连结构；
提供半导体部件，其包括在所述半导体部件上形成的第二互连结构；以及
将所述半导体部件设置在所述半导体管芯上以使所述第二互连结构与所述第一模块化互连结构对准。
2.根据权利要求1的方法，还包括沿所述半导体管芯的第一和第二相邻侧以L形形成所述第一模块化互连结构。
3.根据权利要求1的方法，还包括沿所述半导体管芯的第一和第二相对侧形成所述第一模块化互连结构。
4.根据权利要求1的方法，还包括预制所述第一模块化互连结构。
5.根据权利要求1的方法，还包括：
在所述半导体管芯的表面上以及在所述第一模块化互连结构上形成绝缘层；
形成通过所述绝缘层且延伸到所述第一模块化互连结构中的多个通孔；以及
将所述第二互连结构设置在所述通孔内。
6.一种制作半导体器件的方法，包括：
提供半导体管芯；以及
沿所述半导体管芯的第一和第二侧设置模块化互连结构。
7.根据权利要求6的方法，还包括：
将密封剂沉积在所述半导体管芯和模块化互连结构上；
在所述半导体管芯、密封剂和模块化互连结构上形成绝缘层；以及
形成通过所述绝缘层和密封剂到所述模块化互连结构的导电通孔。
8.根据权利要求6的方法，其中所述模块化互连结构包括：
提供衬底；
在所述衬底中形成多个开口；以及
将导电材料沉积在所述衬底的开口中。
9.根据权利要求6的方法，其中所述模块化互连结构包括沿所述半导体管芯的第一和第二相邻侧设置的L形。
10.一种半导体器件，包括：
半导体管芯；
第一互连结构，其被形成在所述半导体管芯的表面上；以及
第二互连结构，其是沿所述半导体管芯的***区且与所述第一互连结构垂直地设置的。
11.根据权利要求10的半导体器件，其中所述第二互连结构包括：
衬底；
在所述衬底中形成的开口；以及
在所述衬底的开口中设置的导电材料。
12.根据权利要求10的半导体器件，其中所述第二互连结构是围绕所述半导体管芯的第一和第二相邻侧设置的。
13.根据权利要求10的半导体器件，其中所述第二互连结构是围绕所述半导体管芯的第一和第二相对侧设置的。
14.根据权利要求10的半导体器件，还包括在所述第二互连结构上设置的半导体部件。
15.根据权利要求10的半导体器件，还包括在所述半导体管芯上设置的底部填充材料。
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