CN102005477A - 集成电路、鳍式场效应晶体管及其制造方法 - Google Patents

集成电路、鳍式场效应晶体管及其制造方法 Download PDF

Info

Publication number
CN102005477A
CN102005477A CN2010102638023A CN201010263802A CN102005477A CN 102005477 A CN102005477 A CN 102005477A CN 2010102638023 A CN2010102638023 A CN 2010102638023A CN 201010263802 A CN201010263802 A CN 201010263802A CN 102005477 A CN102005477 A CN 102005477A
Authority
CN
China
Prior art keywords
fin formula
raceway groove
effect transistor
field effect
formula field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010102638023A
Other languages
English (en)
Other versions
CN102005477B (zh
Inventor
叶致锴
张智胜
万幸仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102005477A publication Critical patent/CN102005477A/zh
Application granted granted Critical
Publication of CN102005477B publication Critical patent/CN102005477B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7857—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET of the accumulation type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种集成电路、鳍式场效应晶体管及其制造方法，该鳍式场效应晶体管包括一基材及一鳍式结构于此基材上。此鳍式结构包含一沟道，位于一源极及一漏极之间，其中此源极、此漏极及此沟道具有一第一型掺杂。此沟道包含锗、锗化硅或III-V族半导体。一栅极介电层涂布于此沟道上，且一栅极位于此栅极介电层上。本发明可抑制界面缺陷的影响，还可掺入锗化硅应力源至锗的鳍式场效应晶体管NMOS中，以增进效能。

Description

集成电路、鳍式场效应晶体管及其制造方法
技术领域
本发明涉及一种半导体装置，尤其涉及一种累积型(accumulation type)鳍式场效应晶体管。
背景技术
随着集成电路尺寸微缩，需克服因尺寸微缩所面临的问题。例如，金属氧化物半导体场效应晶体管(MOSFET)因沟道长度缩减而造成效能降低，包括漏电流增加。因此，业界需要新颖的方法及结构来改善金属氧化物半导体场效应晶体管的效能。
发明内容
为了解决现有技术的问题，本发明提供一种鳍式场效应晶体管，包括：一基材；一鳍式结构，位于此基材上，此鳍式结构包含一沟道，位于一源极及一漏极之间，其中此源极、此漏极及此沟道具有一第一型掺杂，且此沟道包含锗、锗化硅或III-V族半导体至少其一；一栅极介电层，位于此沟道上；以及一栅极，位于此栅极介电层上。
本发明也提供一种鳍式场效应晶体管的制造方法，包括：形成一鳍式结构于一基材上，此鳍式结构包含一沟道，位于一源极及一漏极之间，其中此源极、此漏极及此沟道具有一第一型掺杂，且此源极、此漏极及此沟道包含锗、锗化硅或III-V族半导体；形成一栅极介电层于此沟道上；以及形成一栅极于此栅极介电层上。
本发明还提供一种集成电路，包括：一基材；一虚置图案，包含至少一第一鳍式结构于此基材上，此第一鳍式结构包含一第一沟道，位于一第一源极及一第一漏极之间，其中此第一源极、此第一漏极及此第一沟道具有一第一型掺杂；以及一鳍式场效应晶体管，位于此基材上，此鳍式场效应晶体管包含：一第二鳍式结构，位于此基材上，此第二鳍式结构包含一第二沟道，位于一第二源极及一第二漏极之间，其中此第二源极、此第二漏极及此第二沟道具有一第二型掺杂，且此第二沟道包含锗、锗化硅或III-V族半导体至少其一；一栅极介电层，位于此第二沟道上；及一栅极，位于此栅极介电层上。
本发明可抑制界面缺陷的影响，还可掺入锗化硅应力源至锗的鳍式场效应晶体管NMOS中，以增进效能。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1A显示为鳍式场效应晶体管，并显示用于图1B及图1C的不同的剖面方向；
图1B～图1C显示为依照本发明一实施例的累积型鳍式场效应晶体管的剖面图；
图2显示为依照本发明一实施例的累积型鳍式场效应晶体管与传统装置的开电流Ion的比较；
图3显示为本发明一实施例的累积型鳍式场效应晶体管与传统装置的内部电子密度的比较；
图4显示为依照本发明另一实施例的形成累积型鳍式场效应晶体管的工艺；及
图5显示为依照本发明又一实施例的具有虚置图案及含多个累积型鳍式场效应晶体管结构的鳍式场效应晶体管装置的集成电路的剖面图。
其中，附图标记说明如下：
106～源极108～沟道
107～硅化物110～漏极
111～硅化物112～阱区
114～栅极介电层115～氧化层
116～栅极117～氮化间隔层
118～浅沟槽隔离120～基材
502～虚置图案
504～鳍式场效应晶体管装置
506～鳍式场效应晶体管装置
508～沟道
具体实施方式
以下将详细讨论本发明各种实施例的制造及使用方法。然而值得注意的是，本发明所提供的许多可行的发明概念可实施在各种特定范围中。这些特定实施例仅用于举例说明本发明的制造及使用方法，但非用于限定本发明的范围。
某些使用材料不同于硅的平面金属氧化物半导体场效应晶体管相较于传统的硅平面金属氧化物半导体装置(Si planar MOS device)具有优势，例如锗平面金属氧化物半导体装置(Ge planar MOS device)，其载流子(电子/空穴)迁移率较硅高约2.64倍。经发现，锗平面MOS装置面临下列问题：(1)较低的能隙间距Eg及高次临界漏电流Isub(subthreshold leakage current)、(2)高介电常数ε及短沟道效应(short channel effect，SCE)、(3)高界面缺陷(Nit)导致锗的NMOS中的载流子迁移率μ不佳。
当沟道长度缩短时，平面金属氧化物半导体场效应晶体管可具有的沟道长度与源极及漏极所接合的耗尽层的宽度具有相同的数量级。相较于其他金属氧化物半导体场效应晶体管，短沟道效应使平面金属氧化物半导体场效应晶体管的效能更加衰退。当缩短沟道长度以同时增加操作速度及芯片积集度时，短沟道效应也会增加。短沟道效应可归因于两种物理现象：(1)沟道中的电子漂移有其限制，及(2)由于沟道缩短而修改了临界电压。短沟道效应包含：(1)漏极引致势垒下降(drain-induced barrier lowering，DIBL)、(2)表面散射、(3)速度饱和、(4)撞击游离及(5)热电子。特别的是，由于锗平面型MOS具有较高的介电常数ε，显示出更糟的漏极引致势垒下降(DIBL)。
在锗的NMOS中，发现到在介电层及靠近锗的导带(Ec)之间的界面有高密度的界面缺陷(Nit)，而大幅降低电子迁移率。相较于二氧化硅与硅的***，氧化锗(或其他介电层)及锗不具有理想的界面，二氧化硅/硅具有良好的界面而提供硅的MOS所需的界面品质及低界面缺陷。
如上所述，业界所需的是金属氧化物半导体场效应晶体管结构及其制造方法。在本发明实施例中，提供一种累积型鳍式场效应晶体管(accumulation-type FinFET)装置100，以增进金属氧化物半导体场效应晶体管的效能。图1A显示为一实施例的鳍式场效应晶体管。在图1A中，鳍式场效应晶体管100可包含鳍式结构102。图1B及图1C各自显示图1A所示的鳍式场效应晶体管100沿着线段1B及1C的剖面图。在图1A-图1B中，显示累积型鳍式场效应晶体管100具有基材120及鳍式结构102于基材120上。鳍式结构102包含位于源极106及漏极110之间的沟道108。源极106、漏极110及沟道108具有第一型掺杂。位于源极106、漏极110及沟道108之下的阱区112具有第二型掺杂。沟道108包含锗、锗化硅或III-V族半导体。栅极介电层114位于沟道108上。栅极116位于栅极介电层114上。
在一形成锗的N型累积型鳍式场效应晶体管(N-type accumulation GeFinFET)的实施例中，源极106(例如n+源极区)可通过硅化物107连接至源极电压VS。沟道108(例如n-沟道区)可例如包含锗鳍式区(Ge fin region)。漏极110(例如n+漏极区)可通过硅化物111连接至漏极电压VD。阱区112(例如p型阱区)可提供与其他装置电性隔离。栅极介电层114可包含氧化物、氮化物、氮氧化物、高介电常数介电质或前述的任意组合。栅极116(例如金属栅极)可连接至栅极电压VG。氧化层115及氮化间隔物117显示位于栅极116后方。基材120可包含硅、锗、锗化硅、III-V族半导体及/或前述的组合。高介电常数材料可例如包含硅酸铪(HfSiO)、硅酸锆(ZrSiO4)、二氧化锆、其他高介电常数介电材料或前述的任意组合。在其他实施例中，沟道108可包含锗化硅或III-V族半导体，例如AlGaAs、InGaAs等。
图1C显示为累积型鳍式场效应晶体管100的剖面图，其具有沟道108、栅极介电层114及栅极116。位于鳍底下的阱区112提供电性隔离。在一实施例中，沟道108(例如n-沟道)包含锗鳍式区。阱区112(例如p型阱区)提供电性隔离。栅极116可设置于栅极介电层114上。浅沟槽隔离118可形成邻近于阱区112。在其他实施例中，沟道108可包含锗化硅或III-V族半导体，例如AlGaAs、InGaAs等。
在N型累积型鳍式场效应晶体管102中，沟道108、源极106及漏极110可具有n型掺杂。在另一实施例中，P型累积型PMOS装置的沟道108、源极106及漏极110可具有p型掺杂。累积型鳍式场效应晶体管可改变电子/空穴轮廓(electron/hole profile)及费米能阶(EF)位置，其可抑制界面缺陷(Nit)的影响。此外，可掺入锗化硅应力源至锗的鳍式场效应晶体管NMOS中，以增进效能。
于传统反转型(inversion type)NMOS(具有p-沟道)中，电子堆积在界面层，且装置可能会因界面缺陷而降低迁移率。然而，累积型NMOS与传统反转型NMOS相反，块材反转(bulk inversion)减少了可造成降低次临界电流摆幅及电子迁移率的界面缺陷。块材反转(bulk inversion)意指大多数的反转电荷位于图1C所示的鳍中的块材鳍状区(bulk Fin region)作为内部电子(bulk electrons)。然而，在传统的表面反转型装置中，大多数电子堆积于栅极介电质/鳍的表面作为表面电子。使用等同于电源供应电压的栅极电压(VG＝VDD)，累积的费米能阶较靠近能隙(Eg)中间值(mid-bandgap)，且可实质上减少界面缺陷(Nit)的影响。
经发现，沟道掺杂浓度及/或施予漏极110的电源供应电压VDD可影响累积型鳍式场效应晶体管100的电性效能。例如，在NMOS/PMOS的一实施例中，沟道中的反掺杂密度(counter doping density)为n型/p型1e18cm-3～3e18cm-3，电源供应电压VDD为0.5V。在NMOS累积型装置中，n型沟道可减少费米能阶(EF)，增加内部电子密度(bulk electron density)，因此减少表面界面缺陷(Nit)的影响。例如，在一累积型NMOS的实施例中，电子密度为7.1e12cm-2，相比较的反转型NMOS的电子密度为6.7e12cm-2。此外，低的电源供应电压VDD使费米能阶EF移向能隙中间值，增加内部电子/空穴百分比，及减少在NMOS/PMOS中的表面界面缺陷(Nit)的影响。
锗及III-V族半导体沟道材料，例如AlGaAs、InGaAs等，可提供较硅高的载流子迁移率。鳍式场效应晶体管结构提供较佳的栅极控制、较低的漏电流及较佳的尺寸可调性(scalability)。基材120可为硅或锗基材晶片。在一实施例中，可在基材120上进行锗的外延，以形成用于沟道108的锗鳍(Ge-fin)。在NMOS的实施例中，由于锗化硅或硅的源极/漏极可在沟道108中(例如锗沟道)具有拉伸应力以提高电子迁移率，较佳可选择锗化硅或硅的源极/漏极。在P型金属氧化物半导体导体的实施例中，也可使用锗的源极/漏极区，但较佳为GeSn、SiGeSn或III-V族半导体，由于GeSn、SiGeSn或III-V族半导体源极/漏极可在沟道108(例如锗沟道)中具有压缩应力以提高空穴迁移率。
具有锗鳍式沟道区108的鳍式场效应晶体管结构可帮助降低由高介电常数ε所导致的短沟道效应(SCE)。在累积型装置中，鳍式场效应晶体管结构可显著抑制漏电流。相较于平面装置，鳍式场效应晶体管结构可借由较低的沟道掺杂(例如1e17cm-3)及降低的电源供应电压VDD来显著减少能带穿遂(Band to band tunneling，BTBT)漏电流。
图2显示本发明一实施例的锗的累积型鳍式场效应晶体管与传统装置的开电流Ion(turn-on current)的比较。结果呈现在NMOS中，鳍的表面区域的电子迁移率降低了80％，这是由于在锗装置中的界面缺陷Nit(陷阱)的影响。
在图2中，显示传统无界面缺陷(Nit)的硅反转型鳍式场效应晶体管NMOS的开电流Ion。将锗的鳍式场效应晶体管的开电流Ion正规化并与硅的反转型鳍式场效应晶体管相比，具有界面缺陷的锗的反转型鳍式场效应晶体管NMOS装置仅有74％的开电流Ion，这是由于电子迁移率在鳍表面上因锗的界面缺陷而降低。换言之，由TACD模拟可显示出，相较于硅的场效应晶体管(反转模式)，界面缺陷造成了开电流Ion降低26％。上述的锗的反转型鳍式场效应晶体管NMOS，非为累积型态且不具有应力源。然而，具有累积型态的锗的反转型鳍式场效应晶体管NMOS装置，虽然同样具有锗的界面缺陷，但开电流Ion增加至108％。因此，使用累积型沟道可实现34％增益的开电流Ion，也表示锗的累积型沟道的开电流Ion较硅的鳍式场效应晶体管高8％。另外，当加入锗化硅(SiGe)应力源，开电流Ion更增进至132％。在一些实施例中，还可使用表面钝化技术以进一步降低锗累积型鳍式场效应晶体管的界面缺陷。
在累积型装置中，鳍区(Wfin)的宽度较窄，可抑制闭路漏电流Ioff及改善装置效能因短沟道效应(SCE)/漏极引致势垒下降(DIBL)的影响。在一实施例中，鳍宽度小于30nm而具有较佳的效能。在鳍区(Wfin)较宽的平面结构中，需高浓度袋状掺杂(pocket doping)且实际上较难制造累积型沟道。
此外，累积型装置显示在块材区域具有较高的电子密度，特别是在低的电源供应电压VDD及栅极电压VG(例如0.5V)。图3显示本发明一实施例的块材内部电子密度与传统装置的比较。如图3所示，在一实施例中，在栅极电压为0.5V的条件下，锗的累积型鳍式场效应晶体管约有70％的内部电子密度，相较之下，反转型装置则具有约40％的内部电子体积密度。锗的累积型鳍式场效应晶体管NMOS装置具有约1e18cm-3(N型)的沟道掺杂密度，及漏极引致势垒下降(DIBL)为105mV/V，然而，反转型态装置的沟道掺杂浓度为5e18cm-3(p型)。
图4显示依照本发明另一实施例制造鳍式场效应晶体管的工艺流程图。于步骤402，形成鳍式结构于基材120上，其中鳍式结构包含位于源极106及漏极110之间的沟道108(源极106、漏极110及沟道108皆具有相同型态的半导体，且沟道108包含锗、锗化硅或III-V族半导体)。于步骤404，形成栅极介电层104(例如氧化物及/或高介电常数介电质)于沟道108上。于步骤406，形成栅极116于栅极介电层114上。此工艺可还包含沉积及蚀刻浅沟槽隔离(shallow trench isolation，STI)118层，其可提供与邻近装置的隔离。
此工艺可还包含在源极106、漏极110及沟道108下方形成阱区112，其中阱区112具有第二型掺杂。沟道108可具有约1e18cm-3至3e18cm-3的掺杂浓度。栅极116能接收电压，且此电压能使沟道的费米能阶移向沟道的能隙中间值。形成鳍式结构可包含定义沟道108的宽度。在一实施例中，沟道108的宽度可为约30nm或更小。源极106或漏极110至少其一包含用于NMOS装置的锗、锗化硅或硅。源极106或漏极110至少其一包含用于NMOS装置的锗、锗化硅、硅或III-V族半导体。
图5显示为依照本发明又一实施例的包含虚置图案及含多个累积型鳍式场效应晶体管结构的鳍式场效应晶体管装置的集成电路。集成电路包含基材120、虚置图案502及鳍式场效应晶体管装置504、506。虚置图案502包含至少一鳍式结构于基材上。鳍式结构包含位于第一源极及第一漏极之间的沟道508。此源极、漏极及沟道508具有第一型掺杂。阱区112具有第二型掺杂，并提供与其他邻近装置的电性隔离。
位于基材120上的鳍式场效应晶体管装置504、506也包含位于基材120上的鳍式结构。鳍式结构包含位于源极及漏极之间的沟道。此源极、漏极及第二沟道108具有第一型掺杂。沟道108包含锗、锗化硅或III-V族半导体。栅极介电层114位于沟道108上。栅极116位于栅极介电层114上。在此实施例中，在同一装置中使用多个沟道108。
此装置具有累积型沟道，因而鳍式场效应晶体管装置504、506具有相同型态的半导体的沟道108、源极、漏极，例如各自用于NMOS/PMOS的n型/p型半导体。用于NMOS的阱区112为p型，而用于PMOS的阱区112为n型，此阱区112与浅沟槽隔离(STI)各自用作装置间的电性隔离及物理隔离。也可设置无栅极116的虚置图案502，以利于化学机械研磨(CMP)、蚀刻或鳍式轮廓的一致性。此装置可形成于硅或锗基材120上。
如前述，累积型鳍式场效应晶体管可提供所需电子或空穴迁移率，而可增进装置效能。借由使用累积型鳍式场效应晶体管结构，漏电流、界面缺陷(陷阱)及短沟道效应等先前传统锗平面装置所具有的缺点，已不复存于本发明实施例中。在本实施中，不仅可应用于锗沟道、也可应用于锗化硅或其他III-V族沟道材料。
另外，在同一装置中可使用多个鳍式结构，而可提供每单位面积有较高的电流。例如，既然锗及硅之间有晶格失配(lattice mismatch)，较窄的鳍相较于较宽的鳍易于成长良好品质的锗外延层。晶格失配导致的应力可由宽度较窄的鳍及缺陷及错位较少的锗外延层获得抒解。例如，当用于传统锗装置的鳍宽度为50nm时，其可被分隔成两个25nm的鳍。本领域普通技术人员可知本发明还具有许多其他变化实施例。
虽然本发明已以数个优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰。此外，本发明的范围不限定于现有或未来所发展的特定程序、机器、制造、物质的组合、功能、方法或步骤，其实质上进行与依照本发明所述的实施例相同的功能或达成相同的结果。因此，本发明的保护范围当视所附的权利要求所界定的范围为准。此外，每个权利要求建构成一独立的实施例，且各种权利要求及实施例的组合均介于本发明的范围内。

Claims (10)

1.一种鳍式场效应晶体管，包括：
一基材；
一鳍式结构，位于该基材上，该鳍式结构包含一沟道，位于一源极及一漏极之间，其中该源极、该漏极及该沟道具有一第一型掺杂，且该沟道包含锗、锗化硅或III-V族半导体至少其一；以及
一栅极介电层，位于该沟道上；以及
一栅极，位于该栅极介电层上。
2.如权利要求1所述的鳍式场效应晶体管，其中该沟道的掺杂浓度介于约1e18cm-3至3e18cm-3之间。
3.如权利要求1所述的鳍式场效应晶体管，其中该栅极能接受一电压，且该电压能使该沟道的费米能阶移向该沟道的能隙中间值。
4.如权利要求1所述的鳍式场效应晶体管，其中该鳍式场效应晶体管为一N型鳍式场效应晶体管，且该源极及该漏极至少其一包含锗、锗化硅或硅至少其一。
5.如权利要求1所述的鳍式场效应晶体管，其中该鳍式场效应晶体管为一P型鳍式场效应晶体管，且该源极及该漏极至少其一包含Ge、GeSn、SiGeSn或III-V族半导体至少其一。
6.一种鳍式场效应晶体管的制造方法，包括：
形成一鳍式结构于一基材上，该鳍式结构包含一沟道，位于一源极及一漏极之间，其中该源极、该漏极及该沟道具有一第一型掺杂，且该源极、该漏极及该沟道包含锗、锗化硅或III-V族半导体；
形成一栅极介电层于该沟道上；以及
形成一栅极于该栅极介电层上。
7.如权利要求6所述的鳍式场效应晶体管的制造方法，其中该沟道的掺杂浓度介于约1e18cm-3至3e18cm-3之间。
8.一种集成电路，包括：
一基材；
一虚置图案，包含至少一第一鳍式结构于该基材上，该第一鳍式结构包含一第一沟道，位于一第一源极及一第一漏极之间，其中该第一源极、该第一漏极及该第一沟道具有一第一型掺杂；以及
一鳍式场效应晶体管，位于该基材上，该鳍式场效应晶体管包含：
一第二鳍式结构，位于该基材上，该第二鳍式结构包含一第二沟道，位于一第二源极及一第二漏极之间，其中该第二源极、该第二漏极及该第二沟道具有一第二型掺杂，且该第二沟道包含锗、锗化硅或III-V族半导体至少其一；
一栅极介电层，位于该第二沟道上；及
一栅极，位于该栅极介电层上。
9.如权利要求8所述的集成电路，其中该第二沟道的掺杂浓度介于约1e18cm-3至3e18cm-3之间。
10.如权利要求8所述的集成电路，其中该第二源极及该第二漏极至少其一包含锗、锗化硅、硅、GeSn、SiGeSn或III-V族半导体至少其一。
CN2010102638023A 2009-09-01 2010-08-25 集成电路、鳍式场效应晶体管及其制造方法 Active CN102005477B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US23882809P 2009-09-01 2009-09-01
US61/238,828 2009-09-01
US12/757,271 2010-04-09
US12/757,271 US8264032B2 (en) 2009-09-01 2010-04-09 Accumulation type FinFET, circuits and fabrication method thereof

Publications (2)

Publication Number Publication Date
CN102005477A true CN102005477A (zh) 2011-04-06
CN102005477B CN102005477B (zh) 2013-10-02

Family

ID=43623559

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010102638023A Active CN102005477B (zh) 2009-09-01 2010-08-25 集成电路、鳍式场效应晶体管及其制造方法

Country Status (5)

Country Link
US (2) US8264032B2 (zh)
JP (1) JP5373722B2 (zh)
KR (2) KR20110025075A (zh)
CN (1) CN102005477B (zh)
TW (1) TWI426607B (zh)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832135A (zh) * 2012-09-05 2012-12-19 北京大学 锗、三五族半导体材料衬底上制备FinFET的方法
WO2013026213A1 (zh) * 2011-08-22 2013-02-28 中国科学院微电子研究所 半导体器件结构及其制作方法
US8492206B2 (en) 2011-08-22 2013-07-23 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device structure and method for manufacturing the same
CN103594495A (zh) * 2012-08-16 2014-02-19 中国科学院微电子研究所 半导体器件及其制造方法
CN103715258A (zh) * 2012-09-28 2014-04-09 台湾积体电路制造股份有限公司 用于半导体器件的源极/漏极堆叠件压力源
CN103811341A (zh) * 2012-11-09 2014-05-21 中国科学院微电子研究所 半导体器件及其制造方法
CN103840004A (zh) * 2014-02-25 2014-06-04 清华大学 具有SiGeSn源漏的鳍式场效应晶体管及其形成方法
CN103839832A (zh) * 2014-02-25 2014-06-04 清华大学 具有GeSn源漏的鳍式场效应晶体管及其形成方法
CN103840005A (zh) * 2014-02-25 2014-06-04 清华大学 具有SiGeSn源漏的鳍式场效应晶体管及其形成方法
CN103855033A (zh) * 2014-02-25 2014-06-11 清华大学 具有SiGeSn沟道的鳍式场效应晶体管及其形成方法
CN103855156A (zh) * 2012-11-29 2014-06-11 台湾积体电路制造股份有限公司 与finfet工艺相兼容的二极管结构
CN104282566A (zh) * 2013-07-03 2015-01-14 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN104517857A (zh) * 2013-09-27 2015-04-15 三星电子株式会社 包括鳍形场效应晶体管的集成电路器件及其形成方法
CN104671194A (zh) * 2013-12-03 2015-06-03 中芯国际集成电路制造(上海)有限公司 防止结构层脱落的mems器件及其制备方法
CN104733390A (zh) * 2013-12-20 2015-06-24 台湾积体电路制造股份有限公司 用于FinFET阱掺杂的机制
CN103187296B (zh) * 2011-12-31 2015-07-08 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
WO2015127701A1 (en) * 2014-02-25 2015-09-03 Tsinghua University Method for forming fin field effect transistor
CN105374874A (zh) * 2014-08-19 2016-03-02 台湾积体电路制造股份有限公司 用于FinFET器件的结构和方法
CN107221499A (zh) * 2016-03-21 2017-09-29 三星电子株式会社 包括InGaAs沟道的FET装置及制造该FET装置的方法
CN107230729A (zh) * 2016-03-25 2017-10-03 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN107636838A (zh) * 2015-06-27 2018-01-26 英特尔公司 低损害自对准两性finfet尖端掺杂

Families Citing this family (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8440517B2 (en) * 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8492235B2 (en) * 2010-12-29 2013-07-23 Globalfoundries Singapore Pte. Ltd. FinFET with stressors
US8969999B2 (en) 2011-10-27 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) based, metal-semiconductor alloy fuse device and method of manufacturing same
CN103107139B (zh) * 2011-11-09 2017-06-06 联华电子股份有限公司 具有鳍状结构的场效晶体管的结构及其制作方法
US8987824B2 (en) 2011-11-22 2015-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate semiconductor devices
CN103137685B (zh) * 2011-11-24 2015-09-30 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
US8742457B2 (en) * 2011-12-16 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Anti-fuses on semiconductor fins
CN106847811B (zh) 2011-12-20 2021-04-27 英特尔公司 减小的接触电阻的自对准接触金属化
WO2013095376A1 (en) * 2011-12-20 2013-06-27 Intel Corporation Strained channel region transistors employing source and drain stressors and systems including the same
US9048260B2 (en) 2011-12-31 2015-06-02 Intel Corporation Method of forming a semiconductor device with tall fins and using hard mask etch stops
US9171925B2 (en) * 2012-01-24 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate devices with replaced-channels and methods for forming the same
US9281378B2 (en) 2012-01-24 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin recess last process for FinFET fabrication
US8809178B2 (en) 2012-02-29 2014-08-19 Globalfoundries Inc. Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US9082684B2 (en) * 2012-04-02 2015-07-14 Applied Materials, Inc. Method of epitaxial doped germanium tin alloy formation
US8866195B2 (en) * 2012-07-06 2014-10-21 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having metal contacts and method of making the same
CN103426926B (zh) * 2012-05-14 2016-05-25 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、pmos晶体管及其形成方法
US8901615B2 (en) 2012-06-13 2014-12-02 Synopsys, Inc. N-channel and P-channel end-to-end finfet cell architecture
US9583398B2 (en) 2012-06-29 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having FinFETS with different fin profiles
US8629420B1 (en) * 2012-07-03 2014-01-14 Intel Mobile Communications GmbH Drain extended MOS device for bulk FinFET technology
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
CN102810555B (zh) * 2012-08-14 2015-04-15 北京大学 一种锗锡隧穿场效应晶体管及其制备方法
US8912070B2 (en) * 2012-08-16 2014-12-16 The Institute of Microelectronics Chinese Academy of Science Method for manufacturing semiconductor device
US9564367B2 (en) * 2012-09-13 2017-02-07 Globalfoundries Inc. Methods of forming different FinFET devices with different threshold voltages and integrated circuit products containing such devices
US8890264B2 (en) 2012-09-26 2014-11-18 Intel Corporation Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface
US9287138B2 (en) 2012-09-27 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET low resistivity contact formation method
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) * 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8765563B2 (en) * 2012-09-28 2014-07-01 Intel Corporation Trench confined epitaxially grown device layer(s)
US9082853B2 (en) * 2012-10-31 2015-07-14 International Business Machines Corporation Bulk finFET with punchthrough stopper region and method of fabrication
US9443962B2 (en) 2012-11-09 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase fin height in fin-first process
US8836018B2 (en) * 2012-11-16 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor integrated device with channel region
CN103824775B (zh) * 2012-11-16 2018-04-24 中国科学院微电子研究所 FinFET及其制造方法
US20140167162A1 (en) 2012-12-13 2014-06-19 International Business Machines Corporation Finfet with merge-free fins
US8748940B1 (en) * 2012-12-17 2014-06-10 Intel Corporation Semiconductor devices with germanium-rich active layers and doped transition layers
US8896101B2 (en) 2012-12-21 2014-11-25 Intel Corporation Nonplanar III-N transistors with compositionally graded semiconductor channels
US8933435B2 (en) * 2012-12-26 2015-01-13 Globalfoundries Singapore Pte. Ltd. Tunneling transistor
US9093530B2 (en) * 2012-12-28 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of FinFET
US20140264607A1 (en) 2013-03-13 2014-09-18 International Business Machines Corporation Iii-v finfets on silicon substrate
US8975125B2 (en) * 2013-03-14 2015-03-10 International Business Machines Corporation Formation of bulk SiGe fin with dielectric isolation by anodization
US20140264488A1 (en) * 2013-03-15 2014-09-18 Globalfoundries Inc. Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
US8940602B2 (en) * 2013-04-11 2015-01-27 International Business Machines Corporation Self-aligned structure for bulk FinFET
US9412664B2 (en) 2013-05-06 2016-08-09 International Business Machines Corporation Dual material finFET on single substrate
US8859355B1 (en) * 2013-05-06 2014-10-14 International Business Machines Corporation Method to make dual material finFET on same substrate
US9293534B2 (en) 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
US8957478B2 (en) 2013-06-24 2015-02-17 International Business Machines Corporation Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer
CN104282561B (zh) * 2013-07-02 2018-11-06 中国科学院微电子研究所 FinFET器件及其制作方法
KR102176513B1 (ko) 2013-09-25 2020-11-09 인텔 코포레이션 Finfet 아키텍처용 고체-상태 확산 소스를 갖는 분리 웰 도핑
WO2015047264A1 (en) * 2013-09-26 2015-04-02 Intel Corporation Methods of forming low band gap source and drain structures in microelectronic devices
US9583590B2 (en) 2013-09-27 2017-02-28 Samsung Electronics Co., Ltd. Integrated circuit devices including FinFETs and methods of forming the same
KR102099195B1 (ko) * 2013-09-27 2020-04-09 인텔 코포레이션 다층형 순응성 기판들을 갖는 비-평면형 반도체 디바이스들
US9184089B2 (en) 2013-10-04 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanism of forming a trench structure
US9312387B2 (en) * 2013-11-01 2016-04-12 Globalfoundries Inc. Methods of forming FinFET devices with alternative channel materials
US9716176B2 (en) 2013-11-26 2017-07-25 Samsung Electronics Co., Ltd. FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
US10825738B2 (en) * 2013-11-28 2020-11-03 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor arrangements and methods of manufacturing the same
US9054192B1 (en) 2013-12-20 2015-06-09 International Business Machines Corporation Integration of Ge-containing fins and compound semiconductor fins
US9076869B1 (en) 2014-01-08 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method
US9048303B1 (en) 2014-01-30 2015-06-02 Infineon Technologies Austria Ag Group III-nitride-based enhancement mode transistor
US9105663B1 (en) 2014-01-30 2015-08-11 International Business Machines Corporation FinFET with silicon germanium stressor and method of forming
US9337279B2 (en) 2014-03-03 2016-05-10 Infineon Technologies Austria Ag Group III-nitride-based enhancement mode transistor
US10468528B2 (en) 2014-04-16 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device with high-k metal gate stack
US9721955B2 (en) 2014-04-25 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for SRAM FinFET device having an oxide feature
US9178067B1 (en) 2014-04-25 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET device
CN106463535B (zh) * 2014-06-24 2021-04-27 英特尔公司 用于在相同管芯上形成Ge/SiGe沟道和III-V族沟道晶体管的技术
US9224736B1 (en) 2014-06-27 2015-12-29 Taiwan Semicondcutor Manufacturing Company, Ltd. Structure and method for SRAM FinFET device
CN106471624B (zh) * 2014-07-14 2021-01-05 英特尔公司 用于基于鳍状物的电子设备的固体源扩散结
US9735153B2 (en) 2014-07-14 2017-08-15 Samsung Electronics Co., Ltd. Semiconductor device having fin-type field effect transistor and method of manufacturing the same
KR102263045B1 (ko) * 2014-07-25 2021-06-10 삼성전자주식회사 공통 스트레인-완화 버퍼를 구비하는 cmos 장치 및 그 제조 방법
US9293588B1 (en) * 2014-08-28 2016-03-22 International Business Machines Corporation FinFET with a silicon germanium alloy channel and method of fabrication thereof
US10854735B2 (en) 2014-09-03 2020-12-01 Taiwan Semiconductor Manufacturing Company Limited Method of forming transistor
US9847329B2 (en) * 2014-09-04 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of fin feature and method of making same
US9773865B2 (en) 2014-09-22 2017-09-26 International Business Machines Corporation Self-forming spacers using oxidation
KR102255174B1 (ko) 2014-10-10 2021-05-24 삼성전자주식회사 활성 영역을 갖는 반도체 소자 및 그 형성 방법
US9741811B2 (en) 2014-12-15 2017-08-22 Samsung Electronics Co., Ltd. Integrated circuit devices including source/drain extension regions and methods of forming the same
CN107004709B (zh) * 2014-12-22 2021-10-15 英特尔公司 防止子沟道漏电流的半导体装置
US9859423B2 (en) * 2014-12-31 2018-01-02 Stmicroelectronics, Inc. Hetero-channel FinFET
US9601626B2 (en) * 2015-01-23 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structure with two channel layers and manufacturing method thereof
US9537010B2 (en) * 2015-02-04 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US9553172B2 (en) * 2015-02-11 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for FinFET devices
US9673112B2 (en) 2015-02-13 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor fabrication with height control through active region profile
KR102395071B1 (ko) 2015-05-14 2022-05-10 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자
US9761584B2 (en) * 2015-06-05 2017-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Buried channel semiconductor device and method for manufacturing the same
US10510848B2 (en) * 2015-06-24 2019-12-17 Intel Corporation Sub-fin sidewall passivation in replacement channel FinFETS
US10211208B2 (en) * 2015-06-26 2019-02-19 Intel Corporation High-mobility semiconductor source/drain spacer
US9660025B2 (en) 2015-08-31 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US10411007B2 (en) 2015-09-25 2019-09-10 Intel Corporation High mobility field effect transistors with a band-offset semiconductor source/drain spacer
US11222947B2 (en) 2015-09-25 2022-01-11 Intel Corporation Methods of doping fin structures of non-planar transistor devices
WO2017052609A1 (en) 2015-09-25 2017-03-30 Intel Corporation High-electron-mobility transistors with heterojunction dopant diffusion barrier
WO2017052608A1 (en) 2015-09-25 2017-03-30 Intel Corporation High-electron-mobility transistors with counter-doped dopant diffusion barrier
WO2017052619A1 (en) 2015-09-25 2017-03-30 Intel Corporation High mobility field effect transistors with a retrograded semiconductor source/drain
KR102323943B1 (ko) 2015-10-21 2021-11-08 삼성전자주식회사 반도체 장치 제조 방법
KR102509925B1 (ko) * 2015-12-03 2023-03-15 삼성전자주식회사 반도체 소자의 제조 방법
US10593785B2 (en) 2015-12-22 2020-03-17 Intel Corporation Transistors having ultra thin fin profiles and their methods of fabrication
WO2017111806A1 (en) * 2015-12-24 2017-06-29 Intel Corporation Methods of forming doped source/drain contacts and structures formed thereby
US10466731B2 (en) 2016-01-27 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Two-transistor bandgap reference circuit and FinFET device suited for same
WO2017218015A1 (en) 2016-06-17 2017-12-21 Intel Corporation High-mobility field effect transistors with wide bandgap fin cladding
US10580901B2 (en) * 2016-09-02 2020-03-03 International Business Machines Corporation Stacked series connected VFETs for high voltage applications
US20180076280A1 (en) * 2016-09-12 2018-03-15 Jeng-Jye Shau Shallow drain metal-oxide-semiconductor transistors
US20180076281A1 (en) * 2016-09-12 2018-03-15 Jeng-Jye Shau Deep channel isolated drain metal-oxide-semiconductor transistors
US9847392B1 (en) * 2016-10-11 2017-12-19 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US10553494B2 (en) 2016-11-29 2020-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Breakdown resistant semiconductor apparatus and method of making same
JP2019050314A (ja) * 2017-09-11 2019-03-28 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10460993B2 (en) * 2017-11-30 2019-10-29 Intel Corporation Fin cut and fin trim isolation for advanced integrated circuit structure fabrication
DE102018126911A1 (de) 2017-11-30 2019-06-06 Intel Corporation Gate-Schnitt und Finnentrimmisolation für fortschrittliche Integrierter-Schaltkreis-Struktur-Fertigung
JP2020096000A (ja) * 2018-12-10 2020-06-18 ソニーセミコンダクタソリューションズ株式会社 半導体素子および半導体素子の製造方法
US20220190159A1 (en) * 2020-12-15 2022-06-16 Intel Corporation Integrated circuit structures having gesnb source or drain structures

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1518771A (zh) * 2002-08-23 2004-08-04 ض� 三栅极器件及其加工方法
CN1551368A (zh) * 2003-05-09 2004-12-01 台湾积体电路制造股份有限公司 半导体组件、累积模式多重闸晶体管及其制造方法
US20050019993A1 (en) * 2003-07-24 2005-01-27 Deok-Hyung Lee Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
CN1622336A (zh) * 2003-11-24 2005-06-01 三星电子株式会社 具有锗沟道区域的非平面晶体管及其制备方法
US20060160302A1 (en) * 2004-12-10 2006-07-20 Kim Sung-Min Method of fabricating a fin field effect transistor having a plurality of protruding channels

Family Cites Families (170)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590573A (ja) * 1991-09-30 1993-04-09 Sharp Corp 半導体装置
JP2833946B2 (ja) * 1992-12-08 1998-12-09 日本電気株式会社 エッチング方法および装置
JP3144967B2 (ja) * 1993-11-08 2001-03-12 株式会社日立製作所 半導体集積回路およびその製造方法
KR0146203B1 (ko) * 1995-06-26 1998-12-01 김광호 반도체 집적회로의 회로소자값 조정회로
US5963789A (en) * 1996-07-08 1999-10-05 Kabushiki Kaisha Toshiba Method for silicon island formation
JPH10223901A (ja) * 1996-12-04 1998-08-21 Sony Corp 電界効果型トランジスタおよびその製造方法
US6065481A (en) * 1997-03-26 2000-05-23 Fsi International, Inc. Direct vapor delivery of enabling chemical for enhanced HF etch process performance
TW468273B (en) * 1997-04-10 2001-12-11 Hitachi Ltd Semiconductor integrated circuit device and method for manufacturing the same
JP3660783B2 (ja) * 1997-06-30 2005-06-15 松下電器産業株式会社 半導体集積回路
JP3586072B2 (ja) 1997-07-10 2004-11-10 株式会社東芝 不揮発性半導体記憶装置
US6740247B1 (en) * 1999-02-05 2004-05-25 Massachusetts Institute Of Technology HF vapor phase wafer cleaning and oxide etching
JP4037029B2 (ja) * 2000-02-21 2008-01-23 株式会社ルネサステクノロジ 半導体集積回路装置
WO2001086726A1 (en) * 2000-05-10 2001-11-15 Koninklijke Philips Electronics N.V. A semiconductor device
JP4044721B2 (ja) * 2000-08-15 2008-02-06 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6558477B1 (en) * 2000-10-16 2003-05-06 Micron Technology, Inc. Removal of photoresist through the use of hot deionized water bath, water vapor and ozone gas
US6830994B2 (en) * 2001-03-09 2004-12-14 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device having a crystallized semiconductor film
US6531412B2 (en) * 2001-08-10 2003-03-11 International Business Machines Corporation Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications
FR2830984B1 (fr) * 2001-10-17 2005-02-25 St Microelectronics Sa Tranchee d'isolement et procede de realisation
US6737302B2 (en) 2001-10-31 2004-05-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for field-effect transistor
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
JP4118045B2 (ja) * 2001-12-07 2008-07-16 富士通株式会社 半導体装置
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
JP2004014737A (ja) * 2002-06-06 2004-01-15 Renesas Technology Corp 半導体装置およびその製造方法
US6812103B2 (en) * 2002-06-20 2004-11-02 Micron Technology, Inc. Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects
US6974729B2 (en) * 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
US6713365B2 (en) 2002-09-04 2004-03-30 Macronix International Co., Ltd. Methods for filling shallow trench isolations having high aspect ratios
JP4031329B2 (ja) * 2002-09-19 2008-01-09 株式会社東芝 半導体装置及びその製造方法
US6791155B1 (en) 2002-09-20 2004-09-14 Integrated Device Technology, Inc. Stress-relieved shallow trench isolation (STI) structure and method for forming the same
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6833588B2 (en) 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6946373B2 (en) * 2002-11-20 2005-09-20 International Business Machines Corporation Relaxed, low-defect SGOI for strained Si CMOS applications
US7087499B2 (en) * 2002-12-20 2006-08-08 International Business Machines Corporation Integrated antifuse structure for FINFET and CMOS devices
US20040192067A1 (en) * 2003-02-28 2004-09-30 Bruno Ghyselen Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
DE10310740A1 (de) * 2003-03-10 2004-09-30 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen
US6762448B1 (en) * 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US6838322B2 (en) 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US6872647B1 (en) * 2003-05-06 2005-03-29 Advanced Micro Devices, Inc. Method for forming multiple fins in a semiconductor device
US7906441B2 (en) * 2003-05-13 2011-03-15 Texas Instruments Incorporated System and method for mitigating oxide growth in a gate dielectric
TWI242232B (en) * 2003-06-09 2005-10-21 Canon Kk Semiconductor substrate, semiconductor device, and method of manufacturing the same
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US7172943B2 (en) 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
US7112495B2 (en) * 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
JP4212435B2 (ja) * 2003-08-29 2009-01-21 株式会社東芝 半導体装置およびその製造方法
US7078312B1 (en) 2003-09-02 2006-07-18 Novellus Systems, Inc. Method for controlling etch process repeatability
US6881668B2 (en) 2003-09-05 2005-04-19 Mosel Vitel, Inc. Control of air gap position in a dielectric layer
US20050054164A1 (en) * 2003-09-09 2005-03-10 Advanced Micro Devices, Inc. Strained silicon MOSFETs having reduced diffusion of n-type dopants
JP2005116969A (ja) 2003-10-10 2005-04-28 Toshiba Corp 半導体装置及びその製造方法
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
KR100513405B1 (ko) * 2003-12-16 2005-09-09 삼성전자주식회사 핀 트랜지스터의 형성 방법
KR100702552B1 (ko) 2003-12-22 2007-04-04 인터내셔널 비지네스 머신즈 코포레이션 이중 게이트 ＦｉｎＦＥＴ 디자인을 위한 자동화 레이어생성 방법 및 장치
KR100552058B1 (ko) * 2004-01-06 2006-02-20 삼성전자주식회사 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 제조 방법
KR100587672B1 (ko) * 2004-02-02 2006-06-08 삼성전자주식회사 다마신 공법을 이용한 핀 트랜지스터 형성방법
US6956277B1 (en) * 2004-03-23 2005-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Diode junction poly fuse
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050221591A1 (en) * 2004-04-06 2005-10-06 International Business Machines Corporation Method of forming high-quality relaxed SiGe alloy layers on bulk Si substrates
US7115920B2 (en) 2004-04-12 2006-10-03 International Business Machines Corporation FinFET transistor and circuit
KR100568448B1 (ko) 2004-04-19 2006-04-07 삼성전자주식회사 감소된 불순물을 갖는 고유전막의 제조방법
US7259050B2 (en) 2004-04-29 2007-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of making the same
US7300837B2 (en) * 2004-04-30 2007-11-27 Taiwan Semiconductor Manufacturing Co., Ltd FinFET transistor device on SOI and method of fabrication
KR100605104B1 (ko) 2004-05-04 2006-07-26 삼성전자주식회사 핀-펫 소자 및 그 제조 방법
JP4493398B2 (ja) * 2004-05-13 2010-06-30 富士通マイクロエレクトロニクス株式会社 半導体装置
US7157351B2 (en) * 2004-05-20 2007-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Ozone vapor clean method
US20060153995A1 (en) 2004-05-21 2006-07-13 Applied Materials, Inc. Method for fabricating a dielectric stack
JP4796329B2 (ja) * 2004-05-25 2011-10-19 三星電子株式会社 マルチ−ブリッジチャンネル型ｍｏｓトランジスタの製造方法
US7015150B2 (en) * 2004-05-26 2006-03-21 International Business Machines Corporation Exposed pore sealing post patterning
KR100634372B1 (ko) 2004-06-04 2006-10-16 삼성전자주식회사 반도체 소자들 및 그 형성 방법들
US7989855B2 (en) * 2004-06-10 2011-08-02 Nec Corporation Semiconductor device including a deflected part
KR100604870B1 (ko) * 2004-06-16 2006-07-31 삼성전자주식회사 접합 영역의 어브럽트니스를 개선시킬 수 있는 전계 효과트랜지스터 및 그 제조방법
US7361563B2 (en) 2004-06-17 2008-04-22 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device using a selective epitaxial growth technique
JP5203558B2 (ja) * 2004-08-20 2013-06-05 三星電子株式会社 トランジスタ及びこれの製造方法
TWI283066B (en) 2004-09-07 2007-06-21 Samsung Electronics Co Ltd Field effect transistor (FET) having wire channels and method of fabricating the same
US7067400B2 (en) * 2004-09-17 2006-06-27 International Business Machines Corporation Method for preventing sidewall consumption during oxidation of SGOI islands
JP2008514813A (ja) 2004-09-27 2008-05-08 ダウ グローバル テクノロジーズ インコーポレーテッド プラズマ強化化学蒸着による多層被膜
US7018901B1 (en) * 2004-09-29 2006-03-28 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
KR100652381B1 (ko) 2004-10-28 2006-12-01 삼성전자주식회사 다수의 나노 와이어 채널을 구비한 멀티 브릿지 채널 전계효과 트랜지스터 및 그 제조방법
KR100605499B1 (ko) 2004-11-02 2006-07-28 삼성전자주식회사 리세스된 게이트 전극을 갖는 모스 트랜지스터 및 그제조방법
KR100693783B1 (ko) * 2004-11-04 2007-03-12 주식회사 하이닉스반도체 내부전원 발생장치
US7235472B2 (en) * 2004-11-12 2007-06-26 Infineon Technologies Ag Method of making fully silicided gate electrode
JP4696127B2 (ja) * 2004-12-06 2011-06-08 エヌエックスピー ビー ヴィ 半導体基板上にエピタキシャル層を形成する方法およびこの方法によって形成するデバイス
US7026232B1 (en) * 2004-12-23 2006-04-11 Texas Instruments Incorporated Systems and methods for low leakage strained-channel transistor
US20060151808A1 (en) * 2005-01-12 2006-07-13 Chien-Hao Chen MOSFET device with localized stressor
US7282766B2 (en) 2005-01-17 2007-10-16 Fujitsu Limited Fin-type semiconductor device with low contact resistance
CN100481345C (zh) * 2005-02-24 2009-04-22 硅绝缘体技术有限公司 SiGe层的热氧化及其应用
JP2006303451A (ja) * 2005-03-23 2006-11-02 Renesas Technology Corp 半導体装置及び半導体装置の製造方法
US7338614B2 (en) 2005-04-05 2008-03-04 Analog Devices, Inc. Vapor HF etch process mask and method
JP2006324628A (ja) * 2005-05-16 2006-11-30 Interuniv Micro Electronica Centrum Vzw 完全ケイ化ゲート形成方法及び当該方法によって得られたデバイス
WO2006132172A1 (ja) * 2005-06-07 2006-12-14 Nec Corporation フィン型電界効果型トランジスタ、半導体装置及びその製造方法
JP4427489B2 (ja) * 2005-06-13 2010-03-10 株式会社東芝 半導体装置の製造方法
US7547637B2 (en) * 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7960791B2 (en) * 2005-06-24 2011-06-14 International Business Machines Corporation Dense pitch bulk FinFET process by selective EPI and etch
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
KR100655788B1 (ko) 2005-06-30 2006-12-08 삼성전자주식회사 반도체 소자의 세정방법 및 이를 이용한 반도체 소자의제조방법.
US7807523B2 (en) 2005-07-01 2010-10-05 Synopsys, Inc. Sequential selective epitaxial growth
US7265008B2 (en) 2005-07-01 2007-09-04 Synopsys, Inc. Method of IC production using corrugated substrate
US7247887B2 (en) 2005-07-01 2007-07-24 Synopsys, Inc. Segmented channel MOS transistor
US7190050B2 (en) 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
US7605449B2 (en) 2005-07-01 2009-10-20 Synopsys, Inc. Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material
US8466490B2 (en) 2005-07-01 2013-06-18 Synopsys, Inc. Enhanced segmented channel MOS transistor with multi layer regions
US7508031B2 (en) 2005-07-01 2009-03-24 Synopsys, Inc. Enhanced segmented channel MOS transistor with narrowed base regions
EP1744351A3 (en) * 2005-07-11 2008-11-26 Interuniversitair Microelektronica Centrum ( Imec) Method for forming a fully silicided gate MOSFET and devices obtained thereof
JP4774247B2 (ja) * 2005-07-21 2011-09-14 Ｏｋｉセミコンダクタ株式会社 電圧レギュレータ
KR101172853B1 (ko) 2005-07-22 2012-08-10 삼성전자주식회사 반도체 소자의 형성 방법
JP4749076B2 (ja) * 2005-07-27 2011-08-17 ルネサスエレクトロニクス株式会社 半導体装置
US20070029576A1 (en) 2005-08-03 2007-02-08 International Business Machines Corporation Programmable semiconductor device containing a vertically notched fusible link region and methods of making and using same
KR101155097B1 (ko) * 2005-08-24 2012-06-11 삼성전자주식회사 반도체 장치의 제조 방법 및 그에 의해 제조된 반도체 장치
JP2007088255A (ja) * 2005-09-22 2007-04-05 Toshiba Corp 半導体装置の製造方法
US7589387B2 (en) * 2005-10-05 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. SONOS type two-bit FinFET flash memory cell
US7425740B2 (en) 2005-10-07 2008-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for a 1T-RAM bit cell and macro
JP5167816B2 (ja) * 2005-10-21 2013-03-21 富士通株式会社 フィン型半導体装置及びその製造方法
US8513066B2 (en) * 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
US7767541B2 (en) * 2005-10-26 2010-08-03 International Business Machines Corporation Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
DE102005052055B3 (de) * 2005-10-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben
US7718500B2 (en) 2005-12-16 2010-05-18 Chartered Semiconductor Manufacturing, Ltd Formation of raised source/drain structures in NFET with embedded SiGe in PFET
US7525160B2 (en) 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US20070152276A1 (en) 2005-12-30 2007-07-05 International Business Machines Corporation High performance CMOS circuits, and methods for fabricating the same
US7410844B2 (en) * 2006-01-17 2008-08-12 International Business Machines Corporation Device fabrication by anisotropic wet etch
JP2007194336A (ja) 2006-01-18 2007-08-02 Sumco Corp 半導体ウェーハの製造方法
KR100827435B1 (ko) 2006-01-31 2008-05-06 삼성전자주식회사 반도체 소자에서 무산소 애싱 공정을 적용한 게이트 형성방법
JP2007258485A (ja) * 2006-03-23 2007-10-04 Toshiba Corp 半導体装置及びその製造方法
US7407847B2 (en) 2006-03-31 2008-08-05 Intel Corporation Stacked multi-gate transistor design and method of fabrication
KR100813527B1 (ko) * 2006-04-06 2008-03-17 주식회사 하이닉스반도체 반도체 메모리의 내부 전압 발생 장치
WO2007115585A1 (en) 2006-04-11 2007-10-18 Freescale Semiconductor, Inc. Method of forming a semiconductor device and semiconductor device
US7663185B2 (en) * 2006-05-27 2010-02-16 Taiwan Semiconductor Manufacturing Co, Ltd FIN-FET device structure formed employing bulk semiconductor substrate
EP1868233B1 (fr) * 2006-06-12 2009-03-11 Commissariat A L'energie Atomique Procédé de réalisation de zones à base de Si1-yGey de différentes teneurs en Ge sur un même substrat par condensation de germanium
JP4271210B2 (ja) * 2006-06-30 2009-06-03 株式会社東芝 電界効果トランジスタ、集積回路素子、及びそれらの製造方法
US8211761B2 (en) * 2006-08-16 2012-07-03 Globalfoundries Singapore Pte. Ltd. Semiconductor system using germanium condensation
US7554110B2 (en) * 2006-09-15 2009-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with partial stressor channel
US7494862B2 (en) 2006-09-29 2009-02-24 Intel Corporation Methods for uniform doping of non-planar transistor structures
US7410854B2 (en) 2006-10-05 2008-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making FUSI gate and resulting structure
CN100527380C (zh) 2006-11-06 2009-08-12 北京北方微电子基地设备工艺研究中心有限责任公司 硅片浅沟槽隔离刻蚀的方法
US7534689B2 (en) * 2006-11-21 2009-05-19 Advanced Micro Devices, Inc. Stress enhanced MOS transistor and methods for its fabrication
US7943469B2 (en) 2006-11-28 2011-05-17 Intel Corporation Multi-component strain-inducing semiconductor regions
US7538387B2 (en) * 2006-12-29 2009-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Stack SiGe for short channel improvement
US7968952B2 (en) * 2006-12-29 2011-06-28 Intel Corporation Stressed barrier plug slot contact structure for transistor performance enhancement
US7456087B2 (en) * 2007-02-09 2008-11-25 United Microelectronics Corp. Semiconductor device and method of fabricating the same
JP2008227026A (ja) 2007-03-12 2008-09-25 Toshiba Corp 半導体装置の製造方法
KR100844938B1 (ko) 2007-03-16 2008-07-09 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
US8258029B2 (en) 2007-04-10 2012-09-04 Macronix International Co., Ltd. Semiconductor structure and process for reducing the second bit effect of a memory device
US7727842B2 (en) 2007-04-27 2010-06-01 Texas Instruments Incorporated Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device
US7939862B2 (en) 2007-05-30 2011-05-10 Synopsys, Inc. Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers
US8174073B2 (en) * 2007-05-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structures with multiple FinFETs
TW200901368A (en) 2007-06-23 2009-01-01 Promos Technologies Inc Shallow trench isolation structure and method for forming thereof
JP2009016418A (ja) 2007-07-02 2009-01-22 Nec Electronics Corp 半導体装置
US7851865B2 (en) 2007-10-17 2010-12-14 International Business Machines Corporation Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
US7812370B2 (en) * 2007-07-25 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling
US8063437B2 (en) 2007-07-27 2011-11-22 Panasonic Corporation Semiconductor device and method for producing the same
US8883597B2 (en) * 2007-07-31 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabrication of a FinFET element
US7692213B2 (en) * 2007-08-07 2010-04-06 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing a condensation process
US20090053883A1 (en) 2007-08-24 2009-02-26 Texas Instruments Incorporated Method of setting a work function of a fully silicided semiconductor device, and related device
JP4361102B2 (ja) * 2007-09-12 2009-11-11 富士フイルム株式会社 圧電素子の製造方法
US7795097B2 (en) 2007-11-20 2010-09-14 Texas Instruments Incorporated Semiconductor device manufactured by removing sidewalls during replacement gate integration scheme
US7767579B2 (en) * 2007-12-12 2010-08-03 International Business Machines Corporation Protection of SiGe during etch and clean operations
US20090166625A1 (en) * 2007-12-28 2009-07-02 United Microelectronics Corp. Mos device structure
EP2257974A1 (en) * 2008-02-26 2010-12-08 Nxp B.V. Method for manufacturing semiconductor device and semiconductor device
US8003466B2 (en) 2008-04-08 2011-08-23 Advanced Micro Devices, Inc. Method of forming multiple fins for a semiconductor device
US8258585B2 (en) 2008-05-29 2012-09-04 Panasonic Corporation Semiconductor device
DE102008030864B4 (de) 2008-06-30 2010-06-17 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement als Doppelgate- und Tri-Gatetransistor, die auf einem Vollsubstrat aufgebaut sind und Verfahren zur Herstellung des Transistors
US7923321B2 (en) 2008-11-03 2011-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for gap filling in a gate last process
US8247285B2 (en) * 2008-12-22 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. N-FET with a highly doped source/drain and strain booster
US8120063B2 (en) * 2008-12-29 2012-02-21 Intel Corporation Modulation-doped multi-gate devices
CA2659912C (en) 2009-03-24 2012-04-24 Sarah Mary Brunet Nasal prong protector
US8236658B2 (en) 2009-06-03 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming a transistor with a strained channel
US8759943B2 (en) * 2010-10-08 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having notched fin structure and method of making the same
US8043920B2 (en) 2009-09-17 2011-10-25 International Business Machines Corporation finFETS and methods of making same
US7993999B2 (en) 2009-11-09 2011-08-09 International Business Machines Corporation High-K/metal gate CMOS finFET with improved pFET threshold voltage
US8114761B2 (en) * 2009-11-30 2012-02-14 Applied Materials, Inc. Method for doping non-planar transistors
US8785286B2 (en) 2010-02-09 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Techniques for FinFET doping
US8088685B2 (en) 2010-02-09 2012-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Integration of bottom-up metal film deposition
US20110256682A1 (en) 2010-04-15 2011-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1518771A (zh) * 2002-08-23 2004-08-04 ض� 三栅极器件及其加工方法
CN1551368A (zh) * 2003-05-09 2004-12-01 台湾积体电路制造股份有限公司 半导体组件、累积模式多重闸晶体管及其制造方法
US20050019993A1 (en) * 2003-07-24 2005-01-27 Deok-Hyung Lee Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
CN1622336A (zh) * 2003-11-24 2005-06-01 三星电子株式会社 具有锗沟道区域的非平面晶体管及其制备方法
US20060160302A1 (en) * 2004-12-10 2006-07-20 Kim Sung-Min Method of fabricating a fin field effect transistor having a plurality of protruding channels

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KAZUHIKO ENDO,ETC: "《Experimental evaluation of effects of channel doping on characteristics of FinFETs》", 《IEEE ELECTRION DEVICE LETTERS》 *

Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013026213A1 (zh) * 2011-08-22 2013-02-28 中国科学院微电子研究所 半导体器件结构及其制作方法
CN102956483A (zh) * 2011-08-22 2013-03-06 中国科学院微电子研究所 半导体器件结构及其制作方法
US8492206B2 (en) 2011-08-22 2013-07-23 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device structure and method for manufacturing the same
CN102956483B (zh) * 2011-08-22 2015-06-03 中国科学院微电子研究所 半导体器件结构及其制作方法
CN103187296B (zh) * 2011-12-31 2015-07-08 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
CN103594495A (zh) * 2012-08-16 2014-02-19 中国科学院微电子研究所 半导体器件及其制造方法
CN102832135A (zh) * 2012-09-05 2012-12-19 北京大学 锗、三五族半导体材料衬底上制备FinFET的方法
CN103715258A (zh) * 2012-09-28 2014-04-09 台湾积体电路制造股份有限公司 用于半导体器件的源极/漏极堆叠件压力源
CN103715258B (zh) * 2012-09-28 2016-08-17 台湾积体电路制造股份有限公司 用于半导体器件的源极/漏极堆叠件压力源
CN103811341A (zh) * 2012-11-09 2014-05-21 中国科学院微电子研究所 半导体器件及其制造方法
CN103811341B (zh) * 2012-11-09 2016-05-11 中国科学院微电子研究所 半导体器件及其制造方法
CN103855156B (zh) * 2012-11-29 2016-08-17 台湾积体电路制造股份有限公司 与finfet工艺相兼容的二极管结构
CN103855156A (zh) * 2012-11-29 2014-06-11 台湾积体电路制造股份有限公司 与finfet工艺相兼容的二极管结构
CN104282566A (zh) * 2013-07-03 2015-01-14 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN104517857B (zh) * 2013-09-27 2019-05-07 三星电子株式会社 包括鳍形场效应晶体管的集成电路器件及其形成方法
CN104517857A (zh) * 2013-09-27 2015-04-15 三星电子株式会社 包括鳍形场效应晶体管的集成电路器件及其形成方法
CN104671194A (zh) * 2013-12-03 2015-06-03 中芯国际集成电路制造(上海)有限公司 防止结构层脱落的mems器件及其制备方法
CN104671194B (zh) * 2013-12-03 2016-08-17 中芯国际集成电路制造(上海)有限公司 防止结构层脱落的mems器件及其制备方法
CN104733390B (zh) * 2013-12-20 2018-06-26 台湾积体电路制造股份有限公司 用于FinFET阱掺杂的机制
CN104733390A (zh) * 2013-12-20 2015-06-24 台湾积体电路制造股份有限公司 用于FinFET阱掺杂的机制
CN103839832A (zh) * 2014-02-25 2014-06-04 清华大学 具有GeSn源漏的鳍式场效应晶体管及其形成方法
WO2015127701A1 (en) * 2014-02-25 2015-09-03 Tsinghua University Method for forming fin field effect transistor
CN103855033A (zh) * 2014-02-25 2014-06-11 清华大学 具有SiGeSn沟道的鳍式场效应晶体管及其形成方法
CN103840004A (zh) * 2014-02-25 2014-06-04 清华大学 具有SiGeSn源漏的鳍式场效应晶体管及其形成方法
CN103840005A (zh) * 2014-02-25 2014-06-04 清华大学 具有SiGeSn源漏的鳍式场效应晶体管及其形成方法
CN105374874B (zh) * 2014-08-19 2018-06-05 台湾积体电路制造股份有限公司 用于FinFET器件的结构和方法
CN105374874A (zh) * 2014-08-19 2016-03-02 台湾积体电路制造股份有限公司 用于FinFET器件的结构和方法
CN107636838B (zh) * 2015-06-27 2022-01-14 英特尔公司 低损害自对准两性finfet尖端掺杂
CN107636838A (zh) * 2015-06-27 2018-01-26 英特尔公司 低损害自对准两性finfet尖端掺杂
CN107221499A (zh) * 2016-03-21 2017-09-29 三星电子株式会社 包括InGaAs沟道的FET装置及制造该FET装置的方法
CN107221499B (zh) * 2016-03-21 2022-07-26 三星电子株式会社 包括InGaAs沟道的FET装置及制造该FET装置的方法
CN107230729A (zh) * 2016-03-25 2017-10-03 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN107230729B (zh) * 2016-03-25 2022-04-19 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US11631768B2 (en) 2016-03-25 2023-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing thereof

Also Published As

Publication number Publication date
US20110049613A1 (en) 2011-03-03
US8264032B2 (en) 2012-09-11
TW201110352A (en) 2011-03-16
JP5373722B2 (ja) 2013-12-18
KR20140083964A (ko) 2014-07-04
CN102005477B (zh) 2013-10-02
TWI426607B (zh) 2014-02-11
US20120306002A1 (en) 2012-12-06
JP2011061196A (ja) 2011-03-24
US8896055B2 (en) 2014-11-25
KR20110025075A (ko) 2011-03-09

Similar Documents

Publication Publication Date Title
CN102005477B (zh) 集成电路、鳍式场效应晶体管及其制造方法
US9698060B2 (en) Germanium FinFETs with metal gates and stressors
KR101226827B1 (ko) 경사 3가 또는 4가 멀티-게이트 트랜지스터
KR101386838B1 (ko) 도핑된 ＳｉＧｅ 소스/드레인 스트레서 증착을 위한 방법 및 장치
US7834345B2 (en) Tunnel field-effect transistors with superlattice channels
US8674341B2 (en) High-mobility multiple-gate transistor with improved on-to-off current ratio
US8587075B2 (en) Tunnel field-effect transistor with metal source
US9947788B2 (en) Device with diffusion blocking layer in source/drain region
US9698270B2 (en) FinFET with dual workfunction gate structure
US9159809B2 (en) Multi-gate transistor device
CN101764062A (zh) 具有高掺杂源/漏极和应变增强器的n型场效应晶体管
US8723223B2 (en) Hybrid Fin field-effect transistors
US9852954B2 (en) Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures
US20150084130A1 (en) Semiconductor structure and method for manufacturing the same
JP2007123880A (ja) 電界効果トランジスタ（ｆｅｔ）およびその製造方法（高性能および低リーク電界効果トランジスタを製造するための構造および方法）
CN102315268A (zh) 半导体器件及其制造方法
US11183591B2 (en) Lateral double-diffused metal-oxide-semiconductor (LDMOS) fin field effect transistor with enhanced capabilities
US20160190318A1 (en) Semiconductor device and manufacturing method thereof
US20180076281A1 (en) Deep channel isolated drain metal-oxide-semiconductor transistors
Kim et al. Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) Si nanowire MOSFETs (SNWFET)
Luan et al. Performance investigations of novel dual-material gate (DMG) MOSFET with dielectric pockets (DP)
CN116632006A (zh) 一种纵向堆叠的栅极自对准反相器集成电路结构
CN103811557A (zh) 无掺杂GeSn量子阱的金属氧化物半导体场效应晶体管

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant