CN104733390B - 用于FinFET阱掺杂的机制 - Google Patents

用于FinFET阱掺杂的机制 Download PDF

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Publication number
CN104733390B
CN104733390B CN201410800475.9A CN201410800475A CN104733390B CN 104733390 B CN104733390 B CN 104733390B CN 201410800475 A CN201410800475 A CN 201410800475A CN 104733390 B CN104733390 B CN 104733390B
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Prior art keywords
doping
dopant
multiple fin
fin
dielectric material
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CN104733390A (zh
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蔡俊雄
林衍廷
万幸仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US14/137,690 external-priority patent/US9406546B2/en
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Abstract

在本发明中描述了用于掺杂FinFET器件的阱的机制的实施例，该实施例利用沉积掺杂膜以掺杂阱区。该机制使得在接近掺杂的阱区的沟道区中维持较低的掺杂剂浓度。结果，可以大大提高晶体管性能。该机制包括在形成晶体管的隔离结构之前沉积掺杂膜。掺杂膜中的掺杂剂用于掺杂靠近鳍的阱区。隔离结构填充有可流动介电材料，在使用微波退火的情况下，可流动介电材料转化为氧化硅。微波退火使得可流动介电材料转化为氧化硅而不会引起掺杂剂扩散。可以实施额外的阱注入以形成深阱。微波退火可用于退火衬底和鳍中的缺陷。本发明涉及用于FinFET阱掺杂的机制。

Description

用于FinFET阱掺杂的机制
相关申请的交叉引用
本申请涉及以下于2013年10月04日提交的标题为“用于形成沟槽结构的机制”的共同代决和共同转让的美国专利申请第14/046,384号(代理卷号：TSM13-0875)和于2013年10月10日提交的标题为“用于形成沟槽结构的机制”的美国临时专利申请第61/889,376号(代理卷号：TSM13-0415)。上述专利申请的全部内容结合于此作为参考。
技术领域
本发明涉及用于FinFET阱掺杂的机制。
背景技术
半导体集成电路(IC)产业经历了快速发展。在IC发展过程中，器件的功能密度已经普遍地增加而器件部件尺寸或几何尺寸却已减小。通常这种按比例缩小工艺通过提高生产效率、降低成本和/或改进性能而带来益处。这种按比例缩小工艺也增大了加工和制造IC的复杂度并且为了实现这些进步，需要IC制造中的类似发展。
而且，对于IC性能的增加和几何尺寸的缩小的需求已导致多栅极器件的引入。这些多栅极器件包括多栅极鳍式场效应晶体管，也称为finFET，之所以如此称为finFET是因为沟道形成在从衬底延伸出来的“鳍”上。FinFET器件允许在包括沟道区的鳍的顶部和/或侧边上提供栅极的同时，缩小器件的栅极宽度。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种在半导体衬底上形成半导体器件的方法，包括：形成从所述半导体衬底延伸的多个鳍；沉积掺杂有第一类型的掺杂剂的第一掺杂膜以覆盖所述多个鳍的第一组；沉积掺杂有第二类型的掺杂剂的第二掺杂膜以覆盖所述多个鳍的第二组；在所述多个鳍的下部之间和所述多个鳍的下部周围形成隔离结构，其中，所述多个鳍的上部未被所述第一掺杂膜或所述第二掺杂膜覆盖；以及实施掺杂剂扩散工艺以扩散所述第一掺杂膜中的所述第一掺杂剂，从而在所述多个鳍的第一组中和靠近所述多个鳍的第一组的衬底区域中形成第一类型的阱，并且扩散所述第二掺杂膜中的所述第二掺杂剂，从而在被所述第二掺杂膜覆盖的所述多个鳍的第二组中形成第二类型的阱。
在上述方法中，所述第一类型的掺杂剂和所述第二类型的掺杂剂是相反类型的掺杂剂。
在上述方法中，所述隔离结构是浅沟槽隔离结构。
在上述方法中，形成所述隔离结构还包括：沉积介电材料以填充所述多个鳍之间和所述多个鳍周围的间隔；固化所述介电材料；对所述介电材料实施蒸汽退火；实施第一退火以将所述介电材料转化为氧化硅；实施平坦化工艺以去除位于所述多个鳍之上的所述介电材料；以及实施一个或多个蚀刻工艺以将所述介电材料凹进为位于所述多个鳍的顶面下方，并且去除覆盖所述多个鳍的第一组且位于所述介电材料之上的所述第一掺杂膜，以及去除覆盖所述多个鳍的第二组且位于所述介电材料之上的所述第二掺杂膜。
在上述方法中，还包括：实施第二退火以降低所述衬底和所述多个鳍中的缺陷。
在上述方法中，还包括：实施深阱注入，其中，在所述第一类型的阱和所述第二类型的阱下方形成深阱。
在上述方法中，还包括：实施另一深阱注入，其中，在所述第一类型的阱和所述深阱之间或者所述第二类型的阱和所述深阱之间形成另一深阱。
在上述方法中，所述掺杂剂扩散工艺是快速热退火工艺或毫秒退火工艺。
在上述方法中，所述第一退火是微波退火并且在介于约400℃至约600℃的范围内的衬底温度下实施。
在上述方法中，所述第二退火是微波退火并且在介于约400℃至约600℃的范围内的衬底温度下实施。
在上述方法中，还包括：实施第三退火以减少所述衬底中和所述多个鳍中的残留缺陷。
在上述方法中，所述第一类型的阱和所述第二类型的阱的掺杂剂浓度介于约1E18原子/cm3至约6E18原子/cm3的范围内。
在上述方法中，所述多个鳍的所述上部的沟道区的掺杂剂浓度介于约5E16原子/cm3至约5E17原子/cm3的范围内。
在上述方法中，所述第一掺杂膜是硼掺杂的硅玻璃(BSG)膜而所述第二掺杂膜是磷掺杂的硅玻璃(PSG)膜。
在上述方法中，所述介电材料是可流动介电材料。
根据本发明的另一方面，还提供了一种在半导体衬底上形成半导体器件的方法，包括：通过蚀刻所述半导体衬底形成多个鳍；沉积掺杂有第一类型的掺杂剂的第一掺杂膜以覆盖所述多个鳍的第一组；沉积掺杂有第二类型的掺杂剂的第二掺杂膜以覆盖所述多个鳍的第二组；形成隔离结构以隔离所述多个鳍，其中，所述隔离结构位于所述多个鳍的下部之间和所述多个鳍的下部周围，其中，所述多个鳍的上部未被所述第一掺杂膜或所述第二掺杂膜覆盖；实施掺杂剂扩散工艺以扩散所述第一掺杂膜中的所述第一掺杂剂，从而在所述多个鳍的第一组中和靠近所述多个鳍的第一组的衬底区域中形成第一类型的阱，并且扩散所述第二掺杂膜中的所述第二掺杂剂，从而在被所述第二掺杂膜覆盖的所述多个鳍的第二组中形成第二类型的阱；以及实施微波退火。
在上述方法中，形成所述隔离结构还包括：沉积可流动介电材料以填充所述多个鳍之间和所述多个鳍周围的间隔；固化所述可流动介电材料；对所述可流动介电材料实施蒸汽退火；实施第一微波退火以将所述可流动介电材料转化为氧化硅；实施平坦化工艺以去除位于所述多个鳍之上的所述可流动介电材料；以及实施一个或多个蚀刻工艺以将所述可流动介电材料凹进为位于所述多个鳍的顶面下方，并且去除覆盖所述多个鳍的第一组且位于所述可流动介电材料之上的所述第一掺杂膜，以及去除覆盖所述多个鳍的第二组且位于所述可流动介电材料之上的所述第二掺杂膜。
根据本发明的又一方面，还提供了一种半导体器件结构，包括：衬底，具有鳍场效应晶体管(finFET)区；栅极结构，在鳍结构上方形成，其中，所述鳍结构含有含硅晶体材料，并且其中，所述鳍结构的一部分在邻近的隔离结构之上突出；沟道区，位于所述鳍结构中，其中，所述沟道区由所述栅极结构围绕，其中，所述沟道区的掺杂剂浓度介于约5E16原子/cm3至约5E17原子/cm3的范围内；以及阱区，位于所述沟道区下方并且接近所述沟道区，其中，所述阱区的掺杂剂浓度介于约1E18原子/cm3至约6E18原子/cm3的范围内。
在上述半导体器件结构中，掺杂的硅玻璃膜内衬于所述隔离结构；其中，所述掺杂的硅玻璃膜中的掺杂剂与所述阱区中的掺杂剂为相同类型。
在上述半导体器件结构中，所述掺杂的硅玻璃膜的掺杂剂浓度介于约1E19原子/cm3至约5E20原子/cm3的范围内。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A是根据一些实施例的半导体器件结构的实施例的透视图。
图1B示出了根据一些实施例的图1A的晶体管区的顶视图。
图1C示出了根据一些实施例的图1A的半导体器件结构的截面图。
图2示出了由Bar Van Zeghbroeck在2007年公开的电子和空穴的迁移率相对于衬底掺杂(或掺杂剂)密度的示意图。
图3A至图3P示出了根据一些实施例的用于形成finFET结构的连续工艺的截面图。
图4A示出了根据一些实施例的靠近表面的SiONH网(Ⅰ)和靠近沟槽的底部的另一SiONH网(Ⅱ)。
图4B示出了根据一些实施例的在低温热退火之后的SiOH+SiO网(III)。
图4C示出了根据一些实施例的在微波退火(MWA)之后的SiO网(IV)。
具体实施方式
应当理解以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。应当理解，本领域普通技术人员将能够想到虽然未在本文中明确描述但是体现本发明的原理的各种等效物。
也需要指出的是，本发明公开了多栅极晶体管的形式或本文中称为finFET器件的鳍式多栅极晶体管的形式的实施例。这种器件可以包括p型金属氧化物半导体finFET器件或n型金属氧化物半导体finFET器件。finFET器件可以是双栅极器件、三栅极器件和/或其他结构。FinFET器件可以包括在诸如微处理器、存储器件的IC、和/或其他IC中。本领域普通技术人员将能够认识到可以受益于本发明的各个方面的半导体器件的其他实施例。
图1A示出了根据一些实施例的半导体器件结构100的透视图。半导体器件结构100包括finFETT型结构。半导体器件结构100包括衬底20、多个鳍104、多个隔离结构106、和设置在每个鳍104上的栅极结构108。隔离结构106也可称为浅槽隔离(STI)结构。栅极结构108可以包括栅极介电层115、栅电极层117，和/或一个或多个额外的层。硬掩模层120位于栅电极层117上方。硬掩模层120用于图案化(诸如蚀刻)栅极结构108。在一些实施例中，硬掩模层120由诸如氧化硅的介电材料制成。图1A的透视图是在栅极结构108的图案化(或形成)工艺之后截取的。图1A仅示出了一个栅极结构108。可以存在类似于且平行于图1A中示出的栅极结构108的额外的栅极结构(未示出)。
多个鳍104的每个均包括源极区110S和漏极区110D，其中源极或漏极部件形成在鳍104中、上和/或周围。鳍104的沟道区112位于栅极结构108下面。如图1A所示，鳍104的沟道区112具有长度(栅极长度)L和宽度(栅极宽度)W。在一些实施例中，长度(栅极长度)L介于从约10nm至约30nm的范围内。在一些实施例中，宽度(栅极宽度)W介于从约10nm至约20nm的范围内。在一些实施例中，从鳍104的顶部至栅极结构108的顶部测量的栅极结构108的高度(栅极高度)HG介于从约50nm至约80nm的范围内。在一些实施例中，从隔离结构106的表面至鳍104的顶部测量的鳍104的高度(鳍高度)H介于从约25nm至约35nm的范围内。
衬底20可以是硅衬底。可选地，衬底20可以包括诸如锗的另一元素半导体；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP的合金半导体；或它们的组合。在实施例中，衬底20是绝缘体上半导体(SOI)。
隔离结构106是由介电材料制成的，并且可以由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料、和/或其他合适的绝缘材料形成。隔离结构106可以是浅槽隔离(STI)部件。在实施例中，隔离部件是STI部件并且通过在衬底20中蚀刻沟槽而形成。然后可以用隔离材料填充沟槽，随后进行化学机械抛光(CMP)。用于隔离结构106和/或鳍结构104的其他制造技术也是可行的。隔离结构106可以包括多层结构，例如，具有一个或多个衬垫层。
鳍结构104可以提供形成一个或多个器件的有源区。在实施例中，晶体管器件的沟道区112形成于鳍104中。鳍104可以包括硅或诸如锗的其他元素半导体；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP的合金半导体；或它们的组合。可以使用包括光刻和蚀刻工艺的合适的工艺制造鳍104。光刻工艺可以包括：在衬底上面(例如，在硅层上)形成光刻胶层(抗蚀剂)、曝光光刻胶以图案化、实施曝光后烘烤工艺、以及显影光刻胶以形成包括光刻胶的掩蔽元件。然后掩蔽元件用于在通过蚀刻工艺在隔离结构106内形成凹槽时保护衬底的区域，留下突出的鳍。可以使用反应离子蚀刻(RIE)和/或其他合适的工艺蚀刻凹槽。用于在衬底20上形成鳍104的方法的许多其他实施例也可以适用。
栅极结构108可以包括栅极介电层115、栅电极层117，和/或一个或多个额外的层。在实施例中，该栅极结构108是诸如在替代栅极工艺中形成的用于形成金属栅极结构的牺牲栅极结构。在实施例中，该栅极结构108包括多晶硅层(作为栅电极层117)。
栅极结构108的栅极介电层115可以包括二氧化硅。可以通过合适的氧化和/或沉积方法形成氧化硅。可选地，栅极结构108的栅极介电层可以包括诸如氧化铪(HfO2)的高k介电层。可选地，高k介电层可以可选地包括其他高k电介质，诸如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合、或其他合适的材料。可以由原子层沉积(ALD)和/或其他合适的方法形成高k介电层。
在实施例中，该栅极结构108可以是金属栅极结构。金属栅极结构可以包括界面层、栅极介电层、功函层、填充金属层、和/或用于金属栅极结构的其他合适的材料。在其他实施例中，金属栅极结构108还可以包括覆盖层、蚀刻停止层、和/或其他合适的材料。界面层可以包括诸如氧化硅层(SiO2)或氮氧化硅(SiON)的介电材料。可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)、和/或其他合适的形成工艺形成界面介电层。
可以包括在栅极结构108中的示例性p型功函金属包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其他合适的p型功函材料或它们的组合。可以包括在栅极结构108中的示例性n型功函金属包括Ti、Ag、TaAl、TaAlC、iAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合适的n型功函材料或它们的组合。功函值是与功函层的材料组成相关，并且因此，选择第一功函层的材料以调整它的功函值，从而使得在将形成于相应区域中的器件中获得期望的阈值电压Vt。可以通过CVD、物理汽相沉积(PVD)、和/或其他合适的工艺沉积功函层。填充金属层可以包括Al、W或Cu和/或其他合适的材料。可以通过CVD、PVD、镀、和/或其他合适的工艺形成填充金属。填充金属可以沉积在功函金属层上方，并且因此填充在通过去除伪栅极结构形成的沟槽或者开口的剩余部分中。
上述的半导体器件结构100包括鳍104和栅极结构108。半导体器件结构100需要额外的加工以形成不同的部件，诸如利用结构100的晶体管的轻掺杂的漏极(LDD)区和掺杂的源极/漏极区。LDD区接近沟道区并且位于间隔件下方。术语LDD区用于描述接近源极和漏极区的轻掺杂区。
图1B示出了根据一些实施例的形成为具有图1A的鳍104中的一个的晶体管区150的顶视图，并且通过与隔离结构106的顶面118平齐的表面截取该顶视图。晶体管区150包括掺杂的源极区110S’和掺杂的漏极区110D’，该掺杂的源极区110S’和掺杂的漏极区110D’分别与平面118处的图1A的掺杂的源极区110S和掺杂的漏极区110D具有相同的截面。
如图1A所示，晶体管区150也包括沟道区112，沟道区112是鳍104的部分并且在3侧上由栅极结构108围绕。沟道区112具有长度(栅极长度)L和宽度(栅极宽度)W。晶体管区150也包括栅极介电层115和栅电极层117。图1B示出了LDD区113位于源极区110S’和沟道区112之间，并且位于漏极区110D’和沟道区112之间。LDD区113具有宽度W和长度LS，长度LS由间隔件111的宽度限定。在一些实施例中，LS介于从约5nm至约10nm的范围内。图1B通过虚线示出了另一栅极结构108。这些其他栅极结构108在上文中描述为类似于且平行于栅极结构108并且在图1A中未示出。
图1C示出了根据一些实施例的根据图1A中示出的切线131截取的半导体器件结构的截面图。图1C示出了两个邻近的栅极结构108。正如上面提到的，可能存在类似于且平行于图1A中示出的栅极结构108的额外的栅极结构。在每个栅极结构108中，都存在一个沟道区112。如图1C所示，沟道区112包括位于隔离结构106之上的鳍104的部分(或暴露的鳍部)和轻微地在隔离结构106的表面121下方延伸的部分。根据一些实施例，通过两条虚线122示出了位于暴露的鳍部下方的沟道区112的边缘。位于沟道区112下方的区域是阱区123(由衬底20中的虚边界线124标记)。如图1C所示，阱区123正好位于沟道区112下方并且包括位于鳍104的沟道区112的下方的区域。阱区123延伸进入衬底20的鳍104下方的区域内。
对于n型场效应(NFET)晶体管，阱区123应当掺杂有p型掺杂剂以与沟道区112、源极区(110S)、和漏极区(110D)形成PN结。类似地，对于p型FET(或PFET)，阱区123应当掺杂有n型掺杂剂。
对于先进的半导体器件，期望使电子和空穴在沟道区112中移动以具有高迁移率。为了提高电子和空穴的迁移率，沟道区112中的掺杂剂密度需要保持较低。图2示出了由BarVan Zeghbroeck在2007年公开的电子和空穴的迁移率相对于衬底掺杂(或掺杂剂)密度的示意图。该图示出了电子和空穴的迁移率随着掺杂剂密度的降低而增大。当掺杂剂密度从约1018原子/cm-3降低至约1016原子/cm-3时候，迁移率的增加非常显著(对于电子而言约六倍且对于空穴而言约三倍)。模拟结果表明，通过将沟道区112中的掺杂剂浓度从约1018原子/cm-3降低至约1016原子/cm-3，离子(电流上)增益可以在从FET的约5％至FET的约10％的范围内增加，这是非常显著的。
然而，为了与FET的源极区和漏极区形成PN结，阱区123需要有足够量(或浓度)的掺杂剂，并且阱区123的掺杂剂的量(或浓度)显著高于诸如沟道区112的沟道区的掺杂剂的量(或浓度)。
可以通过注入掺杂剂实现阱掺杂。然而，沟道区112紧挨着阱区123。如果通过注入掺杂阱区123，由于来自邻近阱区123的注入的掺杂剂的背侧散射效应，因此保持沟道区112的一些部分具有较低的掺杂剂浓度具有挑战性。因此，期望具有用于掺杂邻近沟道区(诸如区域112)的阱区(诸如区域123)的另一种机制。
图3A至图3P根据一些实施例示出了用于形成finFET结构100’的连续工艺的截面图。根据一些实施例，图3A示出了在衬底20上方形成的多个鳍104。衬底20可以是硅衬底。可选地，衬底20可以包括诸如锗的另一元素半导体；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP的合金半导体；或它们的组合。在实施例中，衬底20是绝缘体上半导体(SOI)并且在图3A至图3P中仅示出了半导体部分。
通过在衬底20上方沉积氧化物层21和硬掩模层22形成鳍104。通过首先利用光刻来图案化光刻胶层(未示出)和然后利用蚀刻工艺蚀刻未被保护的硬掩模层22来图案化硬掩模层22。在一些实施例中，由SiN或SiON制成硬掩模层22。氧化物层21是位于衬底20和硬掩模层22之间的缓冲层。在一些实施例中，氧化物层21的厚度介于约3nm至约10nm的范围内。在一些实施例中，硬掩模层22的厚度介于从约20nm至约50nm的范围内。在图案化硬掩模层22之后，实施蚀刻工艺以去除未被图案化的硬掩模层22覆盖的衬底材料以形成鳍104。图3A中的鳍104可以或可以不具有相同的宽度。在一些实施例中，鳍104的宽度W介于约6nm至约15nm的范围内。在一些实施例中，鳍104的高度D介于约28nm至约45nm的范围内。
如图3B所示，根据一些实施例，在形成鳍104之后，在衬底20上方沉积p型掺杂剂层26以覆盖鳍104。p型掺杂剂层26包括诸如硼(B)等的p型掺杂剂。在一些实施例中，由硼掺杂的硅玻璃(BSG，或硼掺杂的氧化硅)制成p型掺杂剂层26。p型掺杂剂将用作掺杂剂源并提供用于掺杂n型场效应晶体管(NFET)下方的p阱的掺杂剂。在一些实施例中，p型掺杂剂浓度介于约1E19原子/cm3至约5E20原子/cm3的范围内。在一些实施例中，p型掺杂剂层26的厚度介于约1nm至约10nm的范围内。在一些实施例中，通过化学汽相沉积(CVD)工艺、等离子体增强CVD(PECVD)工艺、或原子层沉积(ALD)工艺沉积p型掺杂剂层26。也可以使用其他适用的工艺。
在一些实施例中，在p型掺杂剂层26上方形成保护层27。保护层在后续处理期间保护p型掺杂剂层26以保持p型掺杂剂层26的厚度、质量和掺杂剂浓度。在一些实施例中，由SiN或SiON制成保护层27。在一些实施例中，保护层27的厚度介于约2nm至约7nm的范围内。在一些实施例中，通过化学汽相沉积(CVD)工艺、等离子体增强CVD(PECVD)工艺沉积保护层27。也可以使用其他适用的工艺。
如图3C所示，在一些实施例中，在沉积p型掺杂剂层26和保护层27之后，沉积和图案化光刻胶层28以覆盖NFET区110和暴露p型FET(PFET)区120。如图3C所示，暴露的PFET区120包括多个鳍104。在去除位于PFET区120上方的光刻胶之后，通过一个或多个蚀刻工艺去除PFET区120中的保护层27和p型掺杂剂层26。用于去除PFET区120中的这两个层的一个或多个蚀刻工艺包括一个或多个湿工艺、一个或多个干工艺，或湿工艺和干工艺两者的组合。
在去除PFET区120中的保护层27和p型掺杂剂层26之后，去除剩余的光刻胶层28。如图3D所示，根据一些实施例，沉积n型掺杂剂层29以覆盖衬底20上方的表面和结构。n型掺杂剂层29包括n型掺杂剂，诸如磷(P)、砷(As)等。在一些实施例中，n型掺杂剂层29由磷掺杂的硅玻璃(PSG)制成。n型掺杂剂将用作掺杂剂源并提供用于掺杂p型场效应晶体管(PFET)下方的n阱的掺杂剂。在一些实施例中，n型掺杂剂浓度介于约1E19原子/cm3至约5E20原子/cm3的范围内。在一些实施例中，n型掺杂剂层29的厚度介于约1nm至约10nm的范围内。在一些实施例中，通过化学汽相沉积(CVD)工艺、等离子体增强CVD(PECVD)工艺、或原子层沉积(ALD)工艺沉积n型掺杂剂层29。也可以使用其他适用的工艺。
如图3E所示，根据一些实施例，在沉积n型掺杂剂层29之后，沉积并图案化光刻胶层30以覆盖PFET区120和暴露NFET区110。暴露的NFET区110具有n型掺杂剂层29和形成在n型层26上方的保护层27。如图3F所示，根据一些实施例，由一个或多个蚀刻工艺去除暴露的NFET区110中的n型掺杂剂层29和保护层27。用于去除暴露的NFET区110中的n型掺杂剂层29和保护层27的蚀刻工艺可以包括一个或多个湿工艺、一个或多个干工艺，或湿工艺和干工艺两者的组合。之后去除光刻胶层30。图3F示出了形成在NFET区110的表面上方的p型掺杂剂层26。p型掺杂剂层26覆盖区域110中的鳍(对于NFET)104N的表面。图3F也示出了形成在PFET区120的表面上方的n型掺杂剂层29。n型掺杂剂层29覆盖区域120中的鳍(对于PFET)104P的表面。如图3F所示，在鳍104之间具有沟槽300。鳍104N和104P是鳍104的部分。
之后，填充鳍104之间的沟槽300以形成隔离结构(或STI结构)106。随着晶体管尺寸的减小，与形成晶体管相关的各种部件的尺寸也减小。部件尺寸的减少导致隔离结构106的高宽比增加。隔离结构(或STI结构)106的高宽比定义为沟槽300的高度除以沟槽300的宽度。用于填充具有低高宽比的STI的技术不能用于充分填充具有高高宽比的先进技术的STI。在许多化学汽相沉积(CVD)工艺中，使用等离子体与含硅前体和含氧前体气体以在衬底的表面上直接形成氧化硅。这些基于等离子体的CVD工艺在沉积时形成氧化硅；然而对于具有高高宽比的结构，它们填充性较差。
一种用于改进填充性的可选的方法涉及使用可流动的介电材料代替传统的沉积态氧化硅。可流动的介电材料，如它们的名字所表明的，在沉积过程中可以“流动”以填充间隙中的空隙。通常，将各种化学物质加入到含硅前体以允许沉积的膜流动。在一些实施例中，添加氮氢键合物。可流动的电介质前体的实例，特别是可流动的氧化硅前体，包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍硅半氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)、或甲硅烷基胺，诸如三甲硅烷基胺(TSA)。在多步操作工艺中形成这些可流动的氧化硅材料。在沉积可流动膜之后，固化和退火可流动膜以去除不期望的元素(诸如溶剂)以形成氧化硅。当去除不期望的元素之后，可流动膜变得致密和收缩。在一些实施例中，进行多个退火工艺。固化和退火可能会导致沟槽壁氧化和拓宽隔离区。此外，在诸如从约1000℃至约1200℃的范围内的高温下对可流动膜进行固化和退火不止一次。
参考图3G，可流动介电材料过填充沟槽300，并且覆盖鳍结构以形成可流动介电层315。在一些实施例中，在沉积可流动介电层315之前，沉积氧化硅衬垫(未示出)以内衬于结构的表面。
通过使用旋涂电介质(SOD)形成工艺或通过诸如自由基组分CVD的化学汽相沉积(CVD)工艺沉积可流动的电介质来形成可流动介电层315。可流动的氧化硅前体的实例包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍硅半氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或甲硅烷基胺(SA)。
在一些实施例中，通过使用含硅前体以与诸如通过等离子体产生的“氮自由基”前体的另一前体反应来沉积可流动介电层315。在一些实施例中，含硅前体是无碳的并且包括甲硅烷基胺，诸如H2N(SiH3)、HN(SiH3)2、N(SiH3)3或它们的组合。甲硅烷基胺可以混合有额外的气体，额外的气体可以用作载气和/或反应气体。除其他气体之外，额外的气体的实例可以包括H2、N2、NH3、He和Ar。甲硅烷基胺也可以混合有其他无碳含硅气体，诸如硅烷(SiH4)和乙硅烷(Si2H6)、氢(例如，H2)和/或氮(例如，N2、NH3)。
氮可以包括在自由基前体和/或含硅前体中。当氮存在于自由基前体中时，可以被称为氮自由基前体。氮自由基前体也可以伴随着诸如氩气、氦气等的载气。氧可以同时传送到远程等离子体区(以O2或O3的形式)来调节氮自由基前体中的氧含量，从而形成利用该技术沉积的可流动介电层315。
在衬底温度维持在相对较低的温度时，可以进行可流动介电层315的沉积。在一些实施例中，在低温下在衬底表面上沉积可流动介电层315，该低温是通过在沉积期间冷却衬底来维持的。在一些实施例中，在介于约-40℃至约200℃的范围内实施沉积。在一些实施例中，在小于约100℃的温度下实施沉积。在一些实施例中，可以通过***形成这一特定的介电膜，***由加利福尼亚圣克拉拉的应用材料(AppliedMaterials of Santa Clara,California)提供。在美国专利第8,318,584号中描述了上述通过自由基组分CVD工艺沉积可流动介电层315的示例性细节。
沉积态可流动介电层315能够填充窄和深的间隙并且防止沟槽300中的空隙和不连续性。沉积态可流动介电层315包括可流动的SIONH网。在一些实施例中，位于鳍结构(包括鳍104、氧化物层21、硬掩模层22以及p型掺杂剂层26或n型掺杂剂层29中的一个)上方的可流动介电层315的厚度介于约至约的范围内。
在沉积可流动介电层315之后，对沉积态可流动介电层315实施原位固化工艺。原位是指在用于沉积可流动介电层315的工艺室中实施固化工艺。在一些实施例中，在不同的室中实施固化工艺(或非原位)。在一些实施例中，利用O3(臭氧)或蒸汽来操作固化工艺。
图4A示出了根据一些实施例的靠近沟槽300的表面的SiONH网(I)和靠近沟槽300的底部的另一SiONH网(II)。靠近表面的SiONH网比靠近底部的SiONH网含有更多的氧(或O)。
在一些实施例中，进行注入工艺以创建氧源到达远离表面的SiONH网的通道。注入的元素可以包括H、He、Si、O或N。注入工艺在固化的可流动介电层315的表面部分中创建微小通道(或沟道)。通道允许随后热退火的氧源到达靠近沟槽300的底部的SiONH。
如图3G所示，根据一些实施例，在固化工艺和可能的注入工艺之后，实施低温热退火320以将SiONH网转化为SiOH+SiO网。根据一些实施例，在图4B中示出了低温热退火320之后的SiOH+SiO网(III)。在一些实施例中，可以在介于约200℃至约400℃的温度范围内进行低温热退火320。它被称为“低温”热退火以区别于已知的STI的介电层的热退火，已知的STI的介电层的热退火发生在约1000℃或更高的温度下。热退火320的低工艺温度不会引起顶部表面层快速转换为氧化物层，并为氧源渗透到可流动介电层315的底部提供足够的时间。此外，低温热退火320的退火温度不会引起掺杂剂扩散。
可以提供诸如蒸汽(H2O)或H2O2的氧源以协助将SiONH网转化为SiOH+SiO网。由于相对较低的工艺温度，氧源具有足够的时间渗透到可流动介电层315内以到达远离表面的层的部分。在一些实施例中，在熔炉中实施低温退火工艺320。在一些实施例中，在介于约500℃至约600℃的范围内的温度下，工艺持续时间介于约30分钟至约1小时的范围内。
如图3H所示，根据一些实施例，在以上描述的蒸汽热退火工艺之后，进行“干”(无蒸汽)热退火工艺330以将SiOH和SiO网转化为SiO(或SiO2)网。根据一些实施例，在图4C中示出了MWA330之后的SiO网(IV)。在干热退火工艺330期间，不使用蒸汽。在一些实施例中，在干热退火工艺330期间，使用诸如N2的惰性气体。高退火温度可以导致先进的沟道材料的沟道外延松弛或位错(例如，对于先进的SiGe，大于750℃)和/或导致对于先进的器件制造的不期望的掺杂剂扩散(大于750℃)。为了避免这样的问题，退火温度需要保持低于限度和在可能的情况下具有缓冲件。
为了实现退火的目的，退火温度小于n型和p型掺杂剂的低掺杂剂扩散温度，根据一些实施例，使用微波退火(MWA)工艺330。MWA工艺330利用具有缺陷(或悬空键)的SiONH网中的偶极，特别是位于可流动介电层315中的SiOH键合物的偶极以局部地增大可流动介电层315的退火温度，以将SiOH+SiO网转化为SiO网。
如图上述4B所示，可流动介电层315在整个膜中包括SiOH+SiO网。整个膜(从表面至底部)的SiOH键合物中的偶极可以用于增大可流动介电层315的温度。由于微波可以穿透可流动介电层315，它可以与偶极有效地相互作用并退火整个可流动介电层315，包括可流动介电层315的底部。结果，MWA工艺330可以有效地退火整个可流动介电层315。
MWA可以依赖于几个极化机制。对于本文中描述的可流动介电层315的退火，MWA工艺330依赖于可流动介电层315中的偶极极化。位于可流动介电层315周围或下方的各个层/结构的具有极性的偶极不如可流动介电层315的具有极性的偶极的强度大。结果，可流动介电层315的温度可以升高为高于其他层和结构的温度。例如，当衬底50的温度为约500℃时，可流动介电层315的温度可以为约1000℃或更高。
可以优化MWA工艺330以充分利用可流动介电层315中的偶极极化以将可流动介电层315的温度增大至可流动介电层315的退火温度，诸如约1000℃或更高。在一些实施例中，微波的频率介于约2GHz至约10GHz的范围内。在一些实施例中，微波的频率介于约5GHz至约6GHz的范围内。在一些实施例中，MWA 330的功率被证明是介于约3000瓦至约9000瓦的范围内。衬底20的温度介于约400℃至约600℃的范围内。MWA 330的持续时间介于约30秒至约1200秒的范围内。在描述的退火温度范围下，不存在掺杂剂从p型掺杂剂层26扩散至鳍104N或从n型掺杂剂层29扩散至鳍104P的风险。因此，通过利用上述工艺条件的MWA 330的退火被称为无扩散退火。
形成可流动介电层以填充沟槽的其他细节在于2013年10月10日提交的标题为“用于形成沟槽结构的机制(Mechanism for Forming a Trench Structure)”的第61/889,376号美国临时专利申请(代理卷号：TMS 13-0415)中进行了描述，其全部内容结合于此作为参考。
如图3I所示，根据一些实施例，在MWA 330之后，实施诸如化学机械抛光(CMP)的平坦化工艺335以去除位于鳍结构上方的退火的可流动介电层315。硬掩模层22在CMP工艺期间用作抛光停止层并且在CMP工艺结束时可以被去除。如图3J所示，根据一些实施例，在平坦化工艺之后，实施一个或多个蚀刻工艺338以将鳍104之间的可流动介电层315蚀刻(或凹进)至位于鳍104的顶面下方以形成凹槽316。蚀刻工艺也去除靠近鳍104N的暴露部分的p型掺杂剂层26和靠近鳍104P的暴露部分的n型掺杂剂层29。如图3J所示，根据一些实施例，蚀刻工艺进一步去除氧化物层21和位于鳍104(包括104N和104P)上方的残留的硬掩模层22。一个或多个蚀刻工艺可以包括至少湿蚀刻、干蚀刻或两者的组合。
如图3K所示，在一些实施例中，在完成蚀刻工艺之后，可以实施另一MWA340以进一步退火可流动介电层315。MWA340工艺条件类似于上述的MWA330工艺条件。在一些实施例中，省略这一第二MWA工艺操作。在一些实施例中，省略CMP之前的MWA 330工艺，并且实施CMP之后的MWA 340工艺。
之后，如图3L所示，根据一些实施例，实施掺杂剂扩散工艺350。掺杂剂扩散工艺350使掺杂剂层26中的p型掺杂剂扩散至邻近的鳍104N内，并且也使掺杂剂层29中的n型掺杂剂扩散至邻近的鳍104P内。掺杂剂扩散工艺350可以是快速热退火(RTA)工艺或其他适用的工艺，诸如激光退火工艺、闪蒸工艺或MWA工艺。在一些实施例中，如果使用RTA工艺，则温度介于约900℃至约1000℃的范围内。在一些实施例中，RTA工艺的持续时间介于约1秒至约10秒的范围内。如果在一些实施例中使用激光退火工艺，则激光退火温度大于约1100℃，持续时间介于约200μs至约400μs的范围内。在一些实施例中使用闪蒸退火，闪蒸退火温度也大于约1100℃，持续时间介于约0.2ms至约3ms的范围内。
MWA也可以用于掺杂剂扩散工艺350。MWA350工艺将依赖于扩散到鳍104内的掺杂剂的原子极化和界面极化。原子极化和界面极化将会使p型掺杂剂层26、n型掺杂剂层29和鳍104的温度增加至高于周围的结构和材料的温度。在一些实施例中，微波的频率介于约2GHz至约10GHz的范围内。在一些实施例中，微波的频率介于约5GHz至约6GHz的范围内。在一些实施例中，MWA 350的功率被证明是介于约3000瓦至约9000瓦的范围内。衬底20的温度介于约400℃至约600℃的范围内。MWA 350的工艺持续时间介于约100秒至约1200秒的范围内。
根据一些实施例，图3L示出了掺杂剂扩散工艺350之后的由靠近鳍104N的虚线标记的p阱317和由靠近鳍104P的双虚线标记的n阱318。如图3L所示，掺杂剂远离暴露的鳍104。在一些实施例中，p阱(边界317内)的浓度介于约1E18原子/cm3至约6E18原子/cm3的范围内。在一些实施例中，n阱(边界318内)的浓度介于约1E18原子/cm3至约6E18原子/cm3的范围内。在一些实施例中，p阱317和n阱318重叠在鳍104下方的衬底20中。p阱317在沟槽300的表面下方具有深度D1。在一些实施例中，深度D1介于约80nm至约200nm的范围内。n阱318在沟槽300的表面下方具有深度D2。在一些实施例中，深度D2介于约80nm至约150nm的范围内。
p型掺杂剂层26和n型掺杂剂层29均由介电膜制成。它们变为形成在鳍104之间的隔离结构106的部分。每个隔离结构106包括p型掺杂剂层26、n型掺杂剂层29、或p型掺杂剂层26和n型掺杂剂层29。
一些器件需要深阱。如图3M所示，根据一些实施例，在形成p阱317和n阱318之后，通过注入工艺360形成深p阱319。通过光刻胶层210覆盖PFET区。在一些实施例中，对位于p阱317下方的目标区实施阱注入360。在一些实施例中，在介于约25K eV至约35K eV的范围内的能量水平下注入p型掺杂剂。在一些实施例中，p型掺杂剂的掺杂剂浓度介于约1E13原子/cm3至约6E13原子/cm3的范围内。在一些实施例中，p阱319从鳍104N的顶面的深度介于约至约的范围内。在一些实施例中，通过注入工艺360’形成位于深p阱319下方的另一深p阱320。在一些实施例中，在介于约80K eV至约90K eV的范围内的能量水平下注入p型掺杂剂。在一些实施例中，p型掺杂剂的掺杂剂浓度介于约1E13原子/cm3至约6E13原子/cm3的范围内。
如图3N所示，根据一些实施例，之后通过注入工艺370形成深n阱321。通过光刻胶层220覆盖NFET区。在一些实施例中，对位于n阱318下方的目标区实施阱注入370。在一些实施例中，在介于约90K eV至约110K eV的范围内的能量水平下注入n型掺杂剂。在一些实施例中，n型掺杂剂的掺杂剂浓度介于约1E13原子/cm3至约6E13原子/cm3的范围内。在一些实施例中，n阱321从鳍104P的顶面的深度介于约至约的范围内。在一些实施例中，通过注入工艺370’形成位于深n阱321下方的另一深n阱322。在一些实施例中，在介于约160K eV至约200K eV的范围内的能量水平下注入n型掺杂剂。在一些实施例中，n型掺杂剂的掺杂剂浓度介于约5E12原子/cm3至约6E13原子/cm3的范围内。
如图3O所示，根据一些实施例，在实施阱注入360、阱注入370或二者的组合之后，实施MWA退火以修复由于形成隔离结构106而在衬底20(包括鳍104)中产生的缺陷。如上所述，MWA利用多个极化机制以进行加热。衬底20中的缺陷可以导致原子极化和界面极化，这可以被用作MW加热机制。对于常规的熔炉退火和快速热退火，用于减少缺陷的退火温度介于约900℃至约1200℃的范围内。MWA 380使局部加热。靠近缺陷位置的温度可以通过MW以比周围的结构和/或材料以更快的速率加热升温。在一些实施例中，微波的频率介于约2GHz至约10GHz的范围内。在一些实施例中，微波的频率介于约5GHz至约6GHz的范围内。在一些实施例中，MWA 380的功率被证明是介于约3000瓦至约9000瓦的范围内。衬底20的温度介于约400℃至约600℃的范围内。MWA 380的持续时间介于约100秒至约1200秒的范围内。通过使用MWA，解决了由于退火引起的掺杂剂扩散的问题。
如图3P所示，根据一些实施例，在MWA380之后，实施MWA390以修复衬底20中的残留的缺陷。然而，MWA390是可选择的。只有当MWA380没有退火掉所有的缺陷的情况下，才需要MWA390。在一些实施例中，微波的频率介于约2GHz至约10GHz的范围内。在一些实施例中，微波的频率介于约5GHz至约6GHz的范围内。在一些实施例中，MWA 390的功率被证明是介于约3000瓦至约9000瓦的范围内。衬底20的温度介于约400℃至约600℃的范围内。MWA 390的持续时间介于约100秒至约1200秒的范围内。在退火工艺之后，实施额外的工艺顺序以完成衬底20上的器件结构的形成。
上述的用于掺杂p阱和n阱的机制的实施例在形成n型掺杂剂层29之前形成p型掺杂剂层26。然而，可以颠倒p型掺杂剂层26和n型掺杂剂层29的形成次序。首先形成n型掺杂剂层29和随后形成p型掺杂剂层26以提供掺杂剂源，接下来进行与以上描述类似的加工顺序。
上述的用于掺杂finFET器件的阱的机制的实施例利用沉积的掺杂膜以掺杂阱区。该机制使得接近掺杂的阱区的沟道区中的掺杂剂浓度维持较低。结果，晶体管的性能可以大大提高。该机制涉及在形成晶体管的隔离结构之前，沉积掺杂膜。掺杂膜中的掺杂剂用于掺杂靠近鳍的阱区。隔离结构填充有可流动介电材料，在使用微波退火下，可流动介电材料转化为氧化硅。微波退火使可流动介电材料转化为氧化硅而不会引起掺杂剂扩散。可以实施额外的阱注入以形成深阱。微波退火可用于退火衬底和鳍中的缺陷。
在一些实施例中，提供了一种在半导体衬底上形成半导体器件的方法。该方法包括：形成从半导体衬底延伸的多个鳍；和沉积掺杂有第一类型的掺杂剂的第一掺杂膜以覆盖多个鳍的第一组。该方法还包括沉积掺杂有第二类型的掺杂剂的第二掺杂膜以覆盖多个鳍的第二组。该方法还包括在多个鳍的下部之间和多个鳍的下部周围形成隔离结构，并且多个鳍的上部未被第一掺杂膜或第二掺杂膜覆盖。此外，该方法包括实施掺杂剂扩散工艺以扩散第一掺杂膜中的第一掺杂剂，从而在多个鳍的第一组中和靠近多个鳍的第一组的衬底区域中形成第一类型的阱并且扩散第二掺杂膜中的第二掺杂剂，从而在被第二掺杂膜覆盖的多个鳍的第二组中形成第二类型的阱。
在一些其他实施例中，提供了一种在半导体衬底上形成半导体器件的方法。该方法包括：通过蚀刻半导体衬底形成多个鳍；和沉积掺杂有第一类型的掺杂剂的第一掺杂膜以覆盖多个鳍的第一组。该方法还包括沉积掺杂有第二类型的掺杂剂的第二掺杂膜以覆盖多个鳍的第二组；和形成隔离结构以隔离多个鳍。隔离结构位于多个鳍的下部之间并且围绕多个鳍的下部，并且多个鳍的上部未被第一掺杂膜或第二掺杂膜覆盖。该方法还包括实施掺杂剂扩散工艺以扩散第一掺杂膜中的第一掺杂剂，从而在多个鳍的第一组中和靠近多个鳍的第一组的衬底区域中形成第一类型的阱，并且扩散第二掺杂膜中的第二掺杂剂，从而在被第二掺杂膜覆盖的多个鳍的第二组中形成第二类型的阱。此外，该方法包括实施微波退火。
在又一些其他实施例中，提供了一种半导体器件结构。该半导体器件结构包括：具有鳍场效应晶体管(finFET)区的衬底；和在鳍结构上方形成的栅极结构。鳍结构含有晶体含硅材料，并且鳍结构的一部分在邻近的隔离结构之上突出。该半导体器件结构还包括位于鳍结构中的沟道区，并且沟道区由栅极结构围绕，其中，沟道区的掺杂剂浓度介于约5E16原子/cm3至约5E17原子/cm3的范围内。该半导体器件结构还包括位于沟道区下方并且接近沟道区的阱区，并且阱区的掺杂剂浓度介于约1E18原子/cm3至约6E18原子/cm3的范围内。
应当理解本发明公开的不同实施例提供了不同的公开内容，并且本领域普通技术人员在不背离本发明的精神和范围的情况下，可以对本发明做出各种变化、替换和修改。例如，本文中公开的实施例描述了在鳍区中形成拉伸应力。然而，其他实施例可以包括通过在鳍区上面提供相关的应力层(例如，应力转移层)在鳍区中形成压缩应力。生成膜的压缩应力的实例可以包括金属氮化物组合物。

Claims (16)

1.一种在半导体衬底上形成半导体器件的方法，包括：
形成从所述半导体衬底延伸的多个鳍；
沉积掺杂有第一类型的掺杂剂的第一掺杂膜以覆盖所述多个鳍的第一组；
沉积掺杂有第二类型的掺杂剂的第二掺杂膜以覆盖所述多个鳍的第二组；
在所述多个鳍的下部之间和所述多个鳍的下部周围形成隔离结构，其中，所述多个鳍的上部未被所述第一掺杂膜或所述第二掺杂膜覆盖，其中，形成所述隔离结构还包括：
沉积介电材料以填充所述多个鳍之间和所述多个鳍周围的间隔；
固化所述介电材料；
对所述介电材料实施蒸汽退火；
实施第一退火以将所述介电材料转化为氧化硅，所述第一退火是微波退火并且在介于400℃至600℃的范围内的衬底温度下实施；以及
实施掺杂剂扩散工艺以扩散所述第一掺杂膜中的所述第一类型的掺杂剂，从而在所述多个鳍的第一组中和靠近所述多个鳍的第一组的衬底区域中形成第一类型的阱，并且扩散所述第二掺杂膜中的所述第二类型的掺杂剂，从而在被所述第二掺杂膜覆盖的所述多个鳍的第二组中形成第二类型的阱。
2.根据权利要求1所述的方法，其中，所述第一类型的掺杂剂和所述第二类型的掺杂剂是相反类型的掺杂剂。
3.根据权利要求1所述的方法，其中，所述隔离结构是浅沟槽隔离结构。
4.根据权利要求1所述的方法，其中，形成所述隔离结构还包括：
实施平坦化工艺以去除位于所述多个鳍之上的所述介电材料；以及
实施一个或多个蚀刻工艺以将所述介电材料凹进为位于所述多个鳍的顶面下方，并且去除覆盖所述多个鳍的第一组且位于所述介电材料之上的所述第一掺杂膜，以及去除覆盖所述多个鳍的第二组且位于所述介电材料之上的所述第二掺杂膜。
5.根据权利要求1所述的方法，还包括：
实施第二退火以降低所述半导体衬底和所述多个鳍中的缺陷。
6.根据权利要求1所述的方法，还包括：
实施深阱注入，其中，在所述第一类型的阱和所述第二类型的阱下方形成深阱。
7.根据权利要求6所述的方法，还包括：
实施另一深阱注入，其中，在所述第一类型的阱和所述深阱之间或者所述第二类型的阱和所述深阱之间形成另一深阱。
8.根据权利要求1所述的方法，其中，所述掺杂剂扩散工艺是快速热退火工艺或毫秒退火工艺。
9.根据权利要求5所述的方法，其中，所述第二退火是微波退火并且在介于400℃至600℃的范围内的衬底温度下实施。
10.根据权利要求5所述的方法，还包括：
实施第三退火以减少所述半导体衬底中和所述多个鳍中的残留缺陷。
11.根据权利要求1所述的方法，其中，所述第一类型的阱和所述第二类型的阱的掺杂剂浓度介于1E18原子/cm3至6E18原子/cm3的范围内。
12.根据权利要求1所述的方法，其中，所述多个鳍的所述上部的沟道区的掺杂剂浓度介于5E16原子/cm3至5E17原子/cm3的范围内。
13.根据权利要求1所述的方法，其中，所述第一掺杂膜是硼掺杂的硅玻璃(BSG)膜而所述第二掺杂膜是磷掺杂的硅玻璃(PSG)膜。
14.根据权利要求4所述的方法，其中，所述介电材料是可流动介电材料。
15.一种在半导体衬底上形成半导体器件的方法，包括：
通过蚀刻所述半导体衬底形成多个鳍；
沉积掺杂有第一类型的掺杂剂的第一掺杂膜以覆盖所述多个鳍的第一组；
沉积掺杂有第二类型的掺杂剂的第二掺杂膜以覆盖所述多个鳍的第二组；
形成隔离结构以隔离所述多个鳍，其中，所述隔离结构位于所述多个鳍的下部之间和所述多个鳍的下部周围，其中，所述多个鳍的上部未被所述第一掺杂膜或所述第二掺杂膜覆盖，其中，形成所述隔离结构还包括：
沉积可流动介电材料以填充所述多个鳍之间和所述多个鳍周围的间隔；
固化所述可流动介电材料；
对所述可流动介电材料实施蒸汽退火；
实施第一微波退火以将所述可流动介电材料转化为氧化硅，所述第一微波退火在介于400℃至600℃的范围内的衬底温度下实施；
实施掺杂剂扩散工艺以扩散所述第一掺杂膜中的所述第一类型的掺杂剂，从而在所述多个鳍的第一组中和靠近所述多个鳍的第一组的衬底区域中形成第一类型的阱，并且扩散所述第二掺杂膜中的所述第二类型的掺杂剂，从而在被所述第二掺杂膜覆盖的所述多个鳍的第二组中形成第二类型的阱；以及
实施第二微波退火。
16.根据权利要求15所述的方法，其中，形成所述隔离结构还包括：
实施平坦化工艺以去除位于所述多个鳍之上的所述可流动介电材料；以及
实施一个或多个蚀刻工艺以将所述可流动介电材料凹进为位于所述多个鳍的顶面下方，并且去除覆盖所述多个鳍的第一组且位于所述可流动介电材料之上的所述第一掺杂膜，以及去除覆盖所述多个鳍的第二组且位于所述可流动介电材料之上的所述第二掺杂膜。
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