CN100477189C - 半导体装置及制造方法、电子部件、电路基板及电子设备 - Google Patents
半导体装置及制造方法、电子部件、电路基板及电子设备 Download PDFInfo
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- CN100477189C CN100477189C CNB2006101101452A CN200610110145A CN100477189C CN 100477189 C CN100477189 C CN 100477189C CN B2006101101452 A CNB2006101101452 A CN B2006101101452A CN 200610110145 A CN200610110145 A CN 200610110145A CN 100477189 C CN100477189 C CN 100477189C
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Abstract
本发明提供一种半导体装置,包括:具有有源面的半导体基板;设置于所述有源面一侧的第一电极;外部连接端子,其设置于所述有源面一侧,并与所述第一电极电连接;和设置于所述半导体基板的有源面一侧的连接用端子。
Description
技术领域
本发明涉及半导体装置、半导体装置的制造方法、电子部件、电路基板及电子设备。
背景技术
为了进一步高密度地安装半导体装置,裸片安装是理想的。
但是,裸片存在品质难以保证以及难以处理的问题。
因此,一直以来正在开发应用了CSP(Chip Scale/Size Package)的半导体装置。
而且,尤其是近年来,如国家公布01/071805号公报和特开2004-165415号公报所公开的那样,以晶片级(wafer level)形成CSP的所谓晶片级CSP(W-CSP)受到关注。
关于晶片级CSP,是在晶片(wafer)上形成实施了重新布线的多个半导体元件(集成电路),之后通过将晶片切断,使各半导体元件(集成电路)单片化,从而得到半导体装置。
然而,半导体装置多作为用于驱动例如水晶振荡器或MEMS(MicroElectro Mechanical Systems)结构体、各种电子部件结构体等的驱动装置而被广泛利用。
这样的结构体和驱动装置(半导体装置),多被广泛用于例如移动电话等的便携式产品中,因此强烈期望其小型化。
因此,考虑使这样的结构体和驱动该结构体的半导体装置一体化,作为电子部件,由此实现结构体和半导体装置的集合体(电子部件)的小型化。
尤其对半导体装置来说,若采用应用了所述晶片级CSP的半导体装置,则可以进一步实现小型化。
但是,在应用了所述晶片级CSP的半导体装置中,成为如下的结构,即:只能假想向安装有半导体装置的电路基板等连接,作为连接用端子的外部连接端子仅用于向电路基板等的安装。
因此,现状是:使该半导体装置和所述结构体一体化来形成电子部件,在其构成上是极其困难的。
发明内容
本发明鉴于上述情况,其目的在于,提供特别可以与各种结构体一体化且可以实现由此得到的电子部件的小型化并应用了晶片级CSP的半导体装置、其制造方法,和具有该半导体装置的电子部件、电路基板以及电子设备。
本发明的半导体装置,包括:具有有源面的半导体基板;设置于所述有源面一侧的第一电极;外部连接端子,其设置于所述有源面一侧,并与所述第一电极电连接;和设置于所述半导体基板的有源面一侧的连接用端子,所述外部连接端子用于与安装所述半导体装置的电路基板的连接,所述连接用端子被用于电连接所述半导体装置、和配置在所述半导体基板的与所述有源面相反面侧并被所述半导体装置驱动的功能结构体。
根据该半导体装置,由于与外部连接端子独立地设有连接用端子,所以使用该连接用端子,可以进行例如与其他功能结构体(与连接外部连接端子的功能结构体不同的功能结构体)的机械连接或电连接。由此,可以使半导体装置和功能结构体一体化来形成电子部件,可以实现其小型化。
而且,在所述半导体装置中,优选具备重新配置布线,其电连接所述第一电极和所述外部连接端子,并设置于所述有源面一侧。
这样一来,可以自由(任意)设计外部连接端子的位置和其排列。
并且,在所述半导体装置中,优选具备第二电极,其与所述连接用端子电连接,并设置于所述半导体基板的有源面一侧。
这样一来,可以使用连接用端子来实现半导体装置的电处理。
而且,通过使用连接用端子来进行与其他功能结构体的电连接,例如也可以使该半导体装置作为所述功能结构体的驱动用元件而发挥作用。
并且,在所述半导体装置中,优选所述连接用端子在进行电气检查或调整时使用。
这样一来,可以使用所述连接用端子来进行例如电气检查、或通过修整(trimming)实现的半导体装置的功能检查或功能调整。
而且,在所述半导体装置中,优选所述连接用端子,是用于对与所述外部连接端子连接的部件不同的部件进行电连接的端子。
这样一来,通过使用连接用端子进行与其他功能结构体的电连接,可以使该半导体装置作为所述功能结构体的驱动用元件而发挥作用。
并且,在所述半导体装置中,优选具备在所述半导体基板和所述外部连接端子之间设置的应力缓和层,所述外部连接端子经由布线与所述第一电极连接。
这样一来,通过经由布线来电连接第一电极和外部连接端子,会在该半导体装置中形成重新配置布线,因此,扩大了外部连接端子的大小与形状、配置等的自由度。
而且,由于设有应力缓和层,所以,提高了经由外部连接端子来连接半导体装置和外部设备的可靠性。
并且,在所述半导体装置中,优选具备密封所述连接用端子的密封树脂。
若在使用连接用端子进行了电气检查或调整之后,通过密封树脂来密封连接用端子,则在之后无法使用连接用端子进行调整等。
由此,可以提高检查或调整后的半导体装置的可靠性。
而且,若在将连接用端子用于与其他功能结构体之间的电连接后,通过密封树脂进行密封,则可以防止该连接用端子难以预料的短路,进而也可以提高该连接用端子的连接强度。
而且,在所述半导体装置中,优选所述连接用端子形成为柱状。
这样一来,柱状的连接用端子作为例如使下层的导电部和上层的导电部导通的上下导通部件而发挥作用,从而提高了重新配置布线在半导体装置整体的自由度。
本发明的半导体装置的制造方法,包括:准备具有有源面的半导体基板的工序;在所述半导体基板的有源面一侧形成第一电极的工序;将与所述第一电极电连接的外部连接端子,形成在所述半导体基板的有源面一侧的工序,所述外部连接端子用于与安装所述半导体装置的电路基板的连接;和在所述半导体基板的有源面一侧形成用于电连接所述半导体装置、和配置在所述半导体基板的与所述有源面相反面侧并被所述半导体装置驱动的功能结构体的连接用端子的工序。
根据该半导体装置的制造方法,由于在半导体基板的有源面一侧与外部连接端子独立地设置了连接用端子,所以,通过该制造方法而得到的半导体装置,可以使用连接用端子进行例如与其他功能结构体的机械连接或电连接。
由此,可以使功能结构体与半导体装置一体化来形成电子部件,实现了电子部件的小型化。
而且,在所述半导体装置的制造方法中,优选通过在半导体基板的有源面一侧形成第二电极,来电连接所述连接用端子和所述第二电极。
这样一来,所得到的半导体装置可以通过使用连接用端子实现电处理。
并且,通过使用连接用端子进行与其他功能结构体的电连接,也可以使该半导体装置例如作为所述功能结构体的驱动用元件而发挥作用。
而且,在所述半导体装置的制造方法中,优选包括:将多个所述半导体装置形成在一个基板上的工序;和切断所述基板,将多个半导体装置的每一个单片化的工序。
这样一来,可以高效率地制造多个半导体装置,因此,可实现半导体装置的低成本化。
并且,在所述半导体装置的制造方法中,优选包括:在设置了所述连接用端子之后,使用所述连接用端子进行检查或调整、或者进行连接的工序;和之后通过密封树脂来密封所述连接用端子的工序。
若在将连接用端子用于电气检查或调整之后,通过密封树脂来密封连接用端子,则在之后无法使用连接用端子进行调整等。
由此,可提高检查或调整后半导体装置的可靠性。
而且,若在将连接用端子用于与其他功能结构体之间的电连接后,通过密封树脂进行密封,则可以防止该连接用端子难以预料的短路,进而也可以提高该连接用端子的连接强度。
本发明的电子部件具备半导体装置,所述半导体装置具有:半导体基板;设置于所述半导体基板的有源面一侧的第一电极;设置于所述有源面一侧并与所述第一电极电连接且用于与安装所述半导体装置的电路基板的连接的外部连接端子;和设置于所述半导体基板的有源面一侧的连接用端子,该电子设备还具备:功能结构体,其配置于所述半导体装置的所述半导体基板的与所述有源面相反的面侧,且被所述半导体装置驱动;和导电连接部,其将所述功能结构体与所述连接用端子电连接。
根据该电子部件,通过利用连接用端子、并使用导电连接部来连接半导体装置和功能结构体,所以,半导体装置和功能结构体被一体化而构成电子部件,因此,可以实现电子部件的小型化。
并且,尤其优选所述导电连接部通过引线接合形成。
这样一来,可以简便地得到半导体装置和功能结构体的立体连接结构。
而且,在所述电子部件中,优选所述外部连接端子的顶点高度比所述导电连接部的顶点高度高。
这样一来,在使用外部连接端子连接电子部件和外部设备等时,可以防止由导线带来的干涉,能够良好地进行连接。
并且,在所述电子部件中,优选具备密封所述导电连接部的密封树脂。
这样一来,由于通过密封树脂保护了导电连接部,所以,提高了电子部件的可靠性,成为有利于批量生产电子部件的结构。
本发明的电路基板,安装有所述电子部件。
根据该电路基板,由于安装有实现了小型化的电子部件,所以,可相应地实现高密度安装。因此,可以实现高功能化。
本发明的电子设备,安装有所述电子部件。
根据该电子设备,由于安装有实现了小型化的电子部件,所以,可相应地实现高密度安装。因此,可以实现高功能化。
附图说明
图1是表示本发明的半导体装置的一实施方式的侧剖面图。
图2是模式表示图1的半导体装置的俯视图。
图3A~图3C是用于说明图1的半导体装置的制造方法的图。
图4是用于说明图1的半导体装置的制造方法的图。
图5是表示本发明的电子部件的一实施方式的立体图。
图6是表示本发明的半导体装置的其他实施方式的侧剖面图。
图7是表示搭载有本发明电子部件的电子设备的一个例子的图。
具体实施方式
下面详细说明本发明。
(半导体装置)
图1以及图2是表示本发明的半导体装置的一实施方式的图,在这些图中,符号1是晶片级CSP(W-CSP)结构的半导体装置。
另外,图1的侧剖面图表示图2的模式俯视图的A-A线向视剖面图。
如图1所示,半导体装置1包括:形成有集成电路(未图示)的硅基板(半导体基板)10,所述集成电路包括晶体管、存储元件等的半导体元件;第一电极11,其设置在该硅基板10的有源面10a一侧,即形成有所述集成电路一侧;外部连接端子12,其设置在所述有源面10a一侧,并与所述第一电极11电连接;和连接用端子13,其设置在所述有源面10a一侧。
第一电极11是与硅基板10的所述集成电路直接导通而形成的部件,例如如图2所示,在矩形的硅基板10的周边部排列设有多个。
而且,如图1所示,在所述有源面10a上形成有由钝化膜构成的第一绝缘层14。
在第一绝缘层14中,在所述第一电极11上形成有开口部分14a。
通过这样构成,第一电极11在所述开口部分14a内向外侧露出。
在所述第一绝缘层14上,在避开所述第一电极11和后述的第二电极的位置、在本实施方式中的硅基板10的中央部处,形成有由绝缘树脂构成的应力缓和层15。
并且,布线16在所述绝缘层14的开口部分14a内与所述第一电极11连接。
该布线16用于进行所述集成电路的电极重新配置,如图2所示,其形成为从配置在硅基板10的周边部的第一电极11向中央部侧延伸,进而如图1所示,形成为迂回至应力缓和层15上。
由于该布线16在硅基板10的第一电极11和后述的外部连接端子12之间进行布线,所以一般被称作重新配置布线。
这样的重新配置布线是用于使大多被微细设计的硅基板10的电极11的位置、和在用户处进行板安装所使用的稀疏间距(rough pitch)的外部连接端子12的物理位置错开来进行配置的重要部件。
另外,在硅基板10的有源面10a一侧形成有第二绝缘层17,其覆盖布线16与应力缓和层15、第一绝缘层14且由阻焊剂(solder resist)构成,具有耐热性。
在第二绝缘层17中,在所述应力缓和层15上、且在所述布线16上形成有开口部分17a。
通过这样的构成,布线16处于在所述开口部分17a内露出于外侧的状态。
而且,在该开口部分17a内露出的布线16上,配置有所述外部连接端子12。
该外部连接端子12由例如焊锡球形成为凸块状,如图1中的双点划线所示,与作为外部设备的印刷布线板(电路基板)P电连接。
以这样的构成为基础,形成在硅基板10的集成电路(半导体元件)经由第一电极11、作为重新配置布线的布线16、外部连接端子12,与印刷布线板P电连接。
另外,如图2所示,除了所述第一电极11之外,在形成于硅基板10的所述集成电路上还形成有第二电极18。
该第二电极18,是用于驱动例如和所述印刷布线板P不同的其他功能结构体而输出输出信号,或者,为了用电来进行所述集成电路的各种功能检查或功能调整而利用的电极。
另外,在本实施方式中,与所述第一电极11的情况同样,重新配置布线19与该第二电极18连接,露出于外部的所述连接用端子13与该重新配置布线19连接。
连接用端子13是用于进行电或机械连接的焊盘状部位。
尤其在所述第二电极18是用于驱动功能结构体而输出输出信号的电极时,优选作为本实施方式的半导体装置1对与所述印刷布线板P不同的其他功能结构体连接的端子。
而且,如上所述,在所述第二电极18是为了用电进行所述集成电路的各种功能检查或功能调整的电极时,连接用端子13优选在与检测或调整用的探测器等电连接时使用。
并且,该连接用端子13例如在进行了所述集成电路的各种功能检查或功能调整后,如图1中的双点划线所示,通过环氧树脂等密封树脂20来进行密封。
这样,暂时用于功能检查或功能调整的连接用端子此后将与外部环境隔离(绝缘)。
由此,可以杜绝发生半导体元件可靠性降低的情况。
另外,所述第一电极11、第二电极18、连接用端子13由钛(Ti)、氮化钛(TiN)、铝(Al)、铜(Cu)、或包含这些的合金等形成。
尤其对于连接用端子13来说,为了提高例如和所述探测器的电接触性,或提高引线接合时的接合性,优选在其表面实施镀镍(Ni)、金(Au)。
这样一来,尤其可防止因生锈而导致的接触性、接合性的降低。
而且,也可以实施镀焊锡、预涂焊锡等的外表面处理。
并且,布线16以及重新配置布线19由金(Au)、铜(Cu)、银(Ag)、钛(Ti)、钨(W)、钛钨(TiW)、氮化钛(TiN)、镍(Ni)、镍钒(NiV)、铬(Cr)、铝(Al)、钯(Pd)等形成。
另外,作为这些布线16以及重新配置布线19的结构,可以是由所述材料形成的单层结构,也可以是组合了多种材料的层叠结构。
而且,由于这些布线16以及重新配置布线19通常由同一工序形成,所以,会成为相互相同的材料。
并且,作为用于形成第一绝缘层14与第二绝缘层17的树脂,例如可采用:聚酰亚胺树脂、硅改性聚酰亚胺树脂、环氧树脂、硅改性环氧树脂、丙烯酸树脂、酚醛树脂、BCB(benzocyclobutene)、PBO(polybenzoxazole)等。
另外,第一绝缘层14也可以使用二氧化硅(SiO2)、氮化硅(Si3N4)等无机绝缘材料形成。
(半导体装置的制造方法)
接着,参照图3,对所述构成的半导体装置1的制造方法进行说明。
另外,在本实施方式中,如图4所示,在一片硅晶片(基板)100上,一并形成多个半导体装置1,然后将硅晶片100切断(dicing),使多个半导体装置1分别单片化,从而得到半导体装置1。
在图3A~图3C中,为了使说明简单,仅表示1个半导体装置1的形成。
首先,如图3A所示,在硅基板10的有源面10a上的成为所述集成电路导电部的位置,形成第一电极11、第二电极18(在图3A中未示出,参照图2)。
接着,覆盖第一电极11以及第二电极18,在硅基板10上形成第一绝缘层14,进而覆盖该第一绝缘层14来形成树脂层(未图示)。
接着,通过公知的光刻法以及蚀刻法对所述树脂层进行图案形成,在规定形状、即除了所述第一电极11和第二电极18正上位置以外的硅基板10的中央部,形成应力缓和层15。
进而,通过公知的光刻法以及蚀刻法,除去覆盖第一电极11以及第二电极18的位置的绝缘材料,形成开口部分14a。
由此,在这些开口部分14a内使第一电极11以及第二电极18露出。
接着,如图3B所示,形成与第一电极11连接的布线16,形成与第二电极18连接的重新配置布线19。
这些布线16以及重新配置布线19的形成方法包括:在所述开口部分14a内以在第一电极11以及第二电极18导通的方式成膜导电材料,例如以TiW、Cu的顺序通过溅射法成膜TiW、Cu,以布线形状进行了图案形成之后,在所得到的图案上采用镀覆法层叠Cu等的工序。
而且,通过以焊盘形状预先对某一部分进行图案形成,从而形成连接用端子,所述某一部分尤其是指重新配置布线19的前端侧,具体而言是图2所示的重新配置布线19的位于和第二电极18相反位置的部分。
然后,尤其是对于该连接用端子部来说,通过对其表面实施镀镍(Ni)、金(Au),来提高电接触性,或者提高引线接合时的接合性。
由此,形成了本发明的连接用端子13。
另外,也可以对连接用端子13实施镀焊锡、预涂焊锡等外表面处理。
接着,形成覆盖所述布线16、重新配置布线19以及连接用端子13的第二绝缘层17。
进而,通过公知的光刻法以及蚀刻法,除去覆盖某一部分的绝缘材料,形成开口部分17a,所述某一部分是指布线16的一部分,具体而言是布线16的位于和第一电极11相反的位置的部分。
由此,在所述开口部分17a内使布线16露出。
并且,与此同时,也除去覆盖连接用端子13的绝缘材料,形成开口部分17b,由此,在所述开口部分17b内使连接用端子13露出。
之后,如图3C所示,在开口部分17a内露出的布线16上,配置例如由无铅焊锡构成的焊锡球,来形成外部连接端子12。
另外,该外部连接端子12的形成方法,也可以替代配置焊锡球来形成的方法,而在布线16上印刷焊膏,形成外部连接端子12。
然后,如图4所示,通过切断装置110将硅晶片(基板)100切断(dicing)成每个半导体装置1,使多个半导体装置1分别单片化,由此得到半导体装置1。
这里,对如上所述而得到的半导体装置1来说,尤其在所述连接用端子13被用作检查或调整的情况下,具体而言,在为了用电进行所述集成电路的各种功能检查或功能调整而采用第二电极18的情况下,利用该连接用端子13来进行所述集成电路的功能检查或功能调整。
更具体而言,通过进行IC探测器检查、或与该探测器检查同时进行的修整(fuse cut)等,来检查集成电路的功能,或调整其功能。
另外,在所述连接用端子13仅用于集成电路的功能检查或功能调整的情况下,当这些功能检查或功能调整结束后,如上所述,通过密封树脂20密封连接用端子13。
这样,尤其在将本发明的连接用端子13用于集成电路的功能检查或功能调整时,可以确保半导体装置1的品质稳定性,提高其可靠性。
具体而言,为了将外部连接端子12作为用户安装用的端子,一般需要增大其端子间距。
因此,由于设计上制约,有时会变得不能从集成电路(IC)的电极引出全部端子作为外部连接端子。
对此,在本实施方式中,由于通过与外部连接端子12独立地设置连接用端子13,利用其进行集成电路的功能检查或功能调整,所以,减少了与外部连接端子12相关的设计上的制约,可以提高设计自由度。
即,在本发明中,连接用端子13不会干涉外部连接端子12的位置,因此,如果是不会有损设计自由度的位置,如上所述,也可通过重新配置布线19从第二电极18迂回至任意位置来进行配置。
并且,连接用端子13可以配置在该重新配置布线19上的任意位置,当然,也可以不使用重新配置布线19,而直接配置在第二电极18上。
而且,如上所述,连接用端子13也可以是直接将重新配置布线19的一部分直接形成在连接用端子13上的端子。
并且,也可以通过焊盘等与重新配置布线19或第二电极18单独地形成连接用端子13。
另外,在通过调整用的端子或数据写入用的端子等、集成电路的功能,对用户不进行开放的情况下,在本实施方式中,尤其在功能检查或功能调整结束后,通过用密封树脂20来密封连接用端子13,之后可以作到无法采用连接用端子13进行调整等。
因此,可以原样地保持检查或调整结束时的状态,由此,如上所述,可确保半导体装置1的品质稳定性,提高可靠性。
而且,如上所述而得到的连接用端子13,其全部可以用作集成电路的功能检查或功能调整,但也可以是仅一部分的连接用端子13用作集成电路的功能检查或功能调整,而余下的连接用端子13与所述印刷布线板P之外的其他功能结构体连接。
并且,也可以是全部的连接用端子13用作与其他的功能结构体连接。
(电子部件)
下面,对采用所述半导体装置1而构成的本发明电子部件进行说明。
本发明电子部件的结构是将半导体装置1和功能结构体一体化而构成的。
图5是表示本发明电子部件的一实施方式的图,图5中的符号30是电子部件。
电子部件30具有所述的半导体装置1和功能结构体31而构成。
作为功能结构体31没有特别限定,可采用各种结构。
具体而言,可采用水晶振荡器或压电振子、压电音叉、弹性表面声波元件(SAW(Surface Acoustic Wave)元件)、MEMS结构体、与半导体装置1不同的半导体装置、其他各种电子部件结构体等。
而且,半导体装置1特别作为用于驱动这样的功能结构体31的驱动装置而使用。
具体而言,所述半导体装置1中的第二电极18,在本实施方式中是输出用于驱动功能结构体31的输出信号的电极,与第二电极18连接的连接用端子13,与功能结构体31一侧的连接端子(未图示)电连接。
本发明的电子部件30中,在功能结构体31的上表面搭载有半导体装置1,并通过粘接剂等进行固定。
半导体装置1按照其有源面10a朝向外侧的方式搭载于功能结构体31上,由此,功能结构体31接合于半导体装置1的与有源面10a相反的面。
这样的构成中,在功能结构体31的上表面以及半导体装置1的上表面,连接用端子13和功能结构体31的连接端子通过导电连接部连接。
作为导电连接部,由于可简便地采用由金导线32进行的引线接合,所以优选。
另外,并不限定于此,也可以例如采用引线的焊接、梁式引线、TAB等其他公知的安装技术。
由于在半导体装置1的有源面10a一侧,实施所述的由金导线32进行的引线接合,所以如图5所示,该引线接合形成在半导体装置1的与外部连接端子12相同的面上。
当在印刷布线板P安装电子部件30时,由于经由外部连接端子12安装在印刷布线板P上,所以金导线32朝向印刷布线板P。
因此,在本实施方式中,使该金导线32的高度(引线接合高度),具体而言,金导线32的顶点高度(从有源面10a至金导线32的顶点的距离)比外部连接端子12的高度(从有源面10a至外部连接端子12的顶点的距离)足够低,以使尤其在安装时金导线32不会与印刷布线板P抵接。
这样一来,在经由外部连接端子12将电子部件30与印刷布线板P(外部设备)连接时,金导线32不会干涉印刷布线板P。
因此,不会导致外部连接端子12和金导线32的短路等,可以良好地进行连接。
另外,在对半导体装置1的连接用端子13和功能结构体31一侧的连接端子进行引线接合之后,如图5中的双点划线所示,优选通过密封树脂33来密封连接用端子13。
这样一来,可以提高金导线32对连接用端子13的连接强度。
进而,由于通过树脂覆盖连接用端子13以及金导线32,所以,可减少尤其由后面的工序给连接部结构带来的损害,能够显著提高连接可靠性。
而且,在制造这样的电子部件30时,也可以在通过切断将半导体装置1单片化之前,不对各半导体装置1形成由焊锡球构成的外部连接端子12而将半导体装置1单片化,当在与功能结构体31之间进行了引线接合之后,形成外部连接端子12。
如上所述,在本实施方式的半导体装置1中,由于与外部连接端子12独立地设置连接用端子13,所以,通过使用该连接用端子13进行与功能结构体31的机械连接或电连接,可以使该半导体装置1和功能结构体31一体化来形成电子部件30。
由此,可以实现电子部件30的小型化。
并且,由于在硅基板10和外部连接端子12之间设有应力缓和层15,所以,例如在经由外部连接端子12来连接半导体装置1和印刷布线板P等外部设备时,即使在外部连接端子12产生因连接时的压力或热而引起的应力,也可通过应力缓和层15来缓和吸收应力,由此,可以防止断线等不良情况的发生。
因此,可提高外部连接端子12和印刷布线板P等外部设备之间的连接可靠性。
由于本实施方式的电子部件30,利用连接用端子13并通过引线接合来连接半导体装置1和功能结构体31,所以,仅通过使用现有的技术便能容易地将半导体装置1和功能结构体31一体化,由此,可形成三维结构的电子部件。
因此,可以谋求集合体的足够小型化,并可实现其廉价化。
另外,本发明并不限定于所述实施方式,在不脱离本发明的主旨范围内可进行各种变更。
例如,在图5所示的实施方式中,虽然将连接用端子13作为电连接,应用了引线接合,但除此以外,也可以将连接用端子13仅用于机械连接。
具体而言,可以与形成在硅基板10的集成电路无关而使用金属等作为电气独立的连接盘来形成连接用端子13,并作为仅以机械连接功能结构体31和硅基板10为目的的引线接合结构,使用连接用端子13。
具体而言,在实现半导体装置1相对于功能结构体31悬浮于空中的悬挂结构的情况下、在难以使用粘接剂的情况下、进而在仅通过粘接剂无法得到足够接合强度的情况等,可以采用通过利用了连接用端子13的引线接合结构而实现的机械连接。
而且,作为连接用端子13的结构,可以取代图1所示的焊盘状结构,而采用图6所示的柱状(post状)结构。
在图6所示的半导体装置40中,连接用端子41例如由铜形成为柱状(post状),为了防止表面氧化、提高接合性,在成为其连接面的上表面实施镀Ni-Au。
另外,该半导体装置40中,还在外部连接端子12和布线16之间,形成在与所述连接用端子41相同的工序中形成的柱42。
由此,外部连接端子12在第二绝缘层17的上表面侧,经由柱42与布线16电连接。
在这样的结构中,柱状的连接用端子41,作为使例如成为下层导电部的第二电极18或重新配置布线19、与根据需要而在上层(第二绝缘层17上)形成的导电部(未图示)导通的上下导通部件发挥作用,因此,可以进一步提高重新配置布线在半导体装置40整体中的自由度。
(电路基板及电子设备)
本发明的电路基板,通过将所述电子部件30安装到例如图1中以双点划线表示的印刷布线板P而构成。
具体而言,电子部件30中的半导体装置1(40)的外部连接端子12,与印刷布线板P的导电部电连接,由此,构成了本发明的一实施方式的电路基板。
根据该电路基板,由于安装有实现了小型化的电子部件30,所以,可以相应地实现高密度安装,因此,可实现高功能化。
而且,本发明的电子设备也通过安装所述电子部件而构成。
具体而言,作为搭载有所述电子部件30的电子设备的一个例子,可以举出图7所示的移动电话300。
在该电子设备中,也安装有实现了小型化的电子部件,所以,可以相应地实现高密度安装,因此,可以实现高功能化。
另外,作为应用了本发明的电子设备,除了移动电话,例如还可以举出IC卡、摄像机、个人计算机、头带式显示器、放映机、传真装置、数码照相机、便携式TV、DSP装置、PDA、电子记事本等。
Claims (18)
1.一种半导体装置,包括:
具有有源面的半导体基板;
设置于所述有源面一侧的第一电极;
外部连接端子,其设置于所述有源面一侧,并与所述第一电极电连接;和
设置于所述半导体基板的有源面一侧的连接用端子,
所述外部连接端子用于与安装所述半导体装置的电路基板的连接,
所述连接用端子被用于电连接所述半导体装置、和配置在所述半导体基板的与所述有源面相反面侧并被所述半导体装置驱动的功能结构体。
2.根据权利要求1所述的半导体装置,其特征在于,
具备重新配置布线,该重新配置布线电连接所述第一电极和所述外部连接端子,并设置于所述有源面一侧。
3.根据权利要求1或2所述的半导体装置,其特征在于,
具备第二电极,该第二电极与所述连接用端子电连接,并设置于所述半导体基板的有源面一侧。
4.根据权利要求1所述的半导体装置,其特征在于,
所述连接用端子在进行电气检查或调整时使用。
5.根据权利要求1所述的半导体装置,其特征在于,
所述连接用端子,是用于对与所述外部连接端子连接的部件不同的部件进行电连接的端子。
6.根据权利要求1所述的半导体装置,其特征在于,
具备在所述半导体基板和所述外部连接端子之间设置的应力缓和层,所述外部连接端子经由布线与所述第一电极连接。
7.根据权利要求1所述的半导体装置,其特征在于,
具备密封所述连接用端子的密封树脂。
8.根据权利要求1所述的半导体装置,其特征在于,
所述连接用端子形成为柱状。
9.一种半导体装置的制造方法,包括:
准备具有有源面的半导体基板的工序;
在所述半导体基板的有源面一侧形成第一电极的工序;
将与所述第一电极电连接的外部连接端子,形成在所述半导体基板的有源面一侧的工序,所述外部连接端子用于与安装所述半导体装置的电路基板的连接;和
在所述半导体基板的有源面一侧形成用于电连接所述半导体装置、和配置在所述半导体基板的与所述有源面相反面侧并被所述半导体装置驱动的功能结构体的连接用端子的工序。
10.根据权利要求9所述的半导体装置的制造方法,其特征在于,
通过在半导体基板的有源面一侧形成第二电极,来电连接所述连接用端子和所述第二电极。
11.根据权利要求9或10所述的半导体装置的制造方法,其特征在于,包括:
将多个所述半导体装置形成在一个基板上的工序;和
切断所述基板,将多个半导体装置的每一个单片化的工序。
12.根据权利要求9所述的半导体装置的制造方法,其特征在于,包括:
在设置了所述连接用端子之后,使用所述连接用端子进行检查或调整、或者进行连接的工序;和
之后,通过密封树脂来密封所述连接用端子的工序。
13.一种电子部件,包括半导体装置、功能结构体和导电连接部,
所述半导体装置具有:
半导体基板;
设置于所述半导体基板的有源面一侧的第一电极;
设置于所述有源面一侧并与所述第一电极电连接且用于与安装所述半导体装置的电路基板的连接的外部连接端子;和
设置于所述半导体基板的有源面一侧的连接用端子;
所述功能结构体配置于所述半导体装置的所述半导体基板的与所述有源面相反的面侧,且被所述半导体装置驱动;和
所述导电连接部将所述功能结构体与所述连接用端子电连接。
14.根据权利要求13所述的电子部件,其特征在于,
所述导电连接部通过引线接合形成。
15.根据权利要求13或14所述的电子部件,其特征在于,
所述外部连接端子的顶点高度比所述导电连接部的顶点高度高。
16.根据权利要求13所述的电子部件,其特征在于,
具备密封所述导电连接部的密封树脂。
17.一种电路基板,安装有权利要求13~16中任意一项所述的电子部件。
18.一种电子设备,安装有权利要求13~16中任意一项所述的电子部件。
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JP2001257307A (ja) | 2000-03-09 | 2001-09-21 | Sharp Corp | 半導体装置 |
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JP2003086733A (ja) | 2001-09-11 | 2003-03-20 | Matsushita Electric Ind Co Ltd | 半導体装置とその製造方法およびそれを用いた電子機器 |
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US7944064B2 (en) * | 2003-05-26 | 2011-05-17 | Casio Computer Co., Ltd. | Semiconductor device having alignment post electrode and method of manufacturing the same |
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