WO2022178842A1 - 薄膜晶体管、显示面板及显示装置 - Google Patents

薄膜晶体管、显示面板及显示装置 Download PDF

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Publication number
WO2022178842A1
WO2022178842A1 PCT/CN2021/078198 CN2021078198W WO2022178842A1 WO 2022178842 A1 WO2022178842 A1 WO 2022178842A1 CN 2021078198 W CN2021078198 W CN 2021078198W WO 2022178842 A1 WO2022178842 A1 WO 2022178842A1
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Prior art keywords
base substrate
orthographic projection
gate
transistor
layer
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PCT/CN2021/078198
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English (en)
French (fr)
Inventor
李栋
陈善韬
张慧娟
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/078198 priority Critical patent/WO2022178842A1/zh
Priority to US17/637,479 priority patent/US20240120422A1/en
Priority to GB2215862.0A priority patent/GB2610946A/en
Priority to CN202180000347.4A priority patent/CN115250639A/zh
Publication of WO2022178842A1 publication Critical patent/WO2022178842A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a thin film transistor, a display panel and a display device.
  • Thin film transistors are generally used as switching devices in various electrical appliances. However, thin film transistors tend to generate leakage current in an off state, so as to apply to the normal operation of electrical appliances.
  • a thin film transistor including: a semiconductor material layer, a first insulating layer, and a gate electrode layer.
  • the semiconductor material layer is located on one side of a base substrate, and the semiconductor material layer includes a first channel portion, a first doped portion, and a second channel portion that are connected in sequence.
  • the first insulating layer is located on a side of the semiconductor material layer away from the base substrate.
  • the gate layer is located on the side of the first insulating layer away from the base substrate, and the gate layer includes: a first gate part and a second gate part.
  • the orthographic projection of the first gate portion on the base substrate covers the orthographic projection of the first channel portion on the base substrate, and the first gate portion is used for receiving gate driving signals;
  • the orthographic projection of the second gate portion on the base substrate covers the orthographic projection of the second channel portion on the base substrate, and the second gate portion is suspended.
  • an orthographic projection of the first channel portion on the base substrate is a rectangle
  • an orthographic projection of the first doping portion on the base substrate is a rectangle
  • the The orthographic projection of the second channel portion on the base substrate is a rectangle
  • the orthographic projection of the first channel portion on the base substrate and the orthographic projection of the first doped portion on the base substrate , the orthographic projection of the second channel portion on the base substrate is sequentially distributed along the first direction
  • the orthographic projection of the first channel portion on the base substrate, the first doping portion is on the The orthographic projection of the base substrate and the orthographic projection of the second channel portion on the base substrate combine to form a rectangle.
  • a dimension of the first channel portion on the base substrate in the orthographic projection in the first direction is S1
  • the second channel portion is on the base substrate
  • the size of the orthographic projection on the first direction is S2; wherein, the value of S1/S2 is 3-15.
  • a dimension of the first doped portion on the orthographic projection of the base substrate in the first direction is L; wherein, the value of S1/L is 3-15.
  • S1 is equal to 2.8-3.2 microns
  • S2 is equal to 0.2-0.8 microns
  • L is equal to 0.2-0.8 microns.
  • the material of the semiconductor material layer is polycrystalline silicon semiconductor.
  • the semiconductor material layer further includes: a second doping part and a third doping part, the second doping part is connected to the first channel part; the third doping part is connected the second channel portion.
  • the thin film transistor further includes a second insulating layer and a source/drain layer, the second insulating layer is located on the side of the gate layer away from the base substrate; wherein the first insulating layer and the second insulating layer are A first via hole penetrating the first insulating layer and the second insulating layer is formed on the layer, and a second via hole penetrating the first insulating layer and the second insulating layer, the first via hole
  • the orthographic projection of the base substrate is located on the orthographic projection of the second doping portion on the base substrate, and the orthographic projection of the second via hole on the base substrate is located on the third doping portion The portion is on the orthographic projection of the base substrate.
  • the source/drain layer is located on the side of the second insulating layer away from the base substrate, the source/drain layer includes: a first conductive part and a second conductive part, and the first conductive part passes through the first via hole
  • the second doping part is connected to form the first electrode of the thin film transistor; the second conductive part is connected to the third doping part through the second via hole, and is used to form the first electrode of the thin film transistor; Diode.
  • the semiconductor material layer further includes: a fourth doping part, a third channel part, and a fourth doping part connected to the first channel part and the second doping part between the doping parts; the third channel part is connected between the second doping part and the fourth doping part.
  • the gate layer further includes: a third gate part, the orthographic projection of the third gate part on the base substrate covers the orthographic projection of the third channel part on the base substrate, the The third gate portion is connected to the first gate portion.
  • the semiconductor material layer further includes: a fourth doping part and a third channel part, and the fourth doping part is connected to the second channel part and the third doping part between the doping parts; the third channel part is connected between the third doping part and the fourth doping part.
  • the gate layer further includes: a third gate part, the orthographic projection of the third gate part on the base substrate covers the orthographic projection of the third channel part on the base substrate, the The third gate portion is connected to the first gate portion.
  • a display panel including at least one of the above-mentioned thin film transistors.
  • At least one of the thin film transistors includes a first transistor
  • the display panel includes a pixel driving circuit
  • the pixel driving circuit includes a driving transistor, the first transistor, and the first transistor
  • the first electrode of the driving transistor is connected to the gate of the driving transistor, and the first transistor forms the thin film transistor.
  • the second electrode of the first transistor is connected to the initial signal terminal, at least one of the thin film transistors further includes a second transistor, the pixel driving circuit further includes a second transistor, and the first transistor further includes a second transistor.
  • the second electrode of the two transistors is connected to the gate of the driving transistor, and the first electrode is connected to the first electrode of the driving transistor.
  • the display panel includes: a base substrate, an active layer, a first conductive layer, and a second conductive layer.
  • the active layer is located on one side of the base substrate, and the active layer includes: a first active part and a second active part, and the first active part is used to form a first channel of the first transistor part; the second active part is used to form the second channel part of the first transistor, the first active part is orthographically projected on the base substrate and the second active part is on the substrate The orthographic projection of the substrate is distributed along the fourth direction.
  • the first conductive layer is located on the side of the active layer away from the base substrate, the first conductive layer includes: a first grid line and a third conductive portion, and the first grid line is on the base substrate
  • the orthographic projection extends along the third direction, and the orthographic projection of the first grid line on the base substrate covers the orthographic projection of the first active part on the base substrate, and part of the first grid line is used for In forming the first gate of the first transistor, the third direction and the fourth direction intersect; the third conductive portion is orthographically projected on the base substrate to cover the second active portion where The orthographic projection of the base substrate is used to form the second gate of the first transistor.
  • the second conductive layer is located on the side of the first conductive layer away from the base substrate, the second conductive layer includes a second grid line, and the second grid line is used to provide the initial signal terminal; wherein, the The orthographic projection of the third conductive portion on the base substrate is located on the side of the orthographic projection of the first grid line on the base substrate away from the orthographic projection of the second grid line on the base substrate.
  • the first transistor is the thin film transistor of claim 8, and the active layer further includes: a third active part, a fourth active part, and a third active part used to form the third channel part of the first transistor; the fourth active part is used to form the fourth doping part of the first transistor, the fourth active part is on the positive side of the base substrate
  • the projection is located on the side of the orthographic projection of the first grid line on the base substrate away from the orthographic projection of the third conductive portion on the base substrate; wherein, the first grid line is on the front side of the base substrate
  • the projection also covers the orthographic projection of the third active part on the base substrate, and part of the first gate line is used to form the third gate of the first transistor;
  • the second electrode of the driving transistor is connected to a first power supply terminal
  • the display panel further includes a third conductive layer, the third conductive layer is located on the side of the second conductive layer away from the base substrate, the third conductive layer includes a power supply line, and the power supply A line is used to provide the first
  • the orthographic projection of the second gate line on the base substrate at least partially overlaps with the orthographic projection of the fourth active portion on the base substrate.
  • the pixel driving circuit further includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the first power supply terminal
  • the active layer further includes: a fifth active part and a sixth active part, the fifth active part is used to form the first channel part of the second transistor; the sixth active part is used to form the The second channel portion of the second transistor;
  • the first conductive layer further includes: a third gate line, a fourth conductive portion, and a fifth conductive portion, the third gate line is located along the orthographic projection of the base substrate.
  • the orthographic projection of the third grid line on the base substrate covers the orthographic projection of the fifth active part on the base substrate, and part of the third grid line is used to form the first gate of the second transistor;
  • the orthographic projection of the fourth conductive part on the base substrate covers the orthographic projection of the sixth active part on the base substrate, for forming the first gate
  • the fifth conductive part is used to form the gate of the driving transistor and the first electrode of the capacitor.
  • the second conductive layer further includes a sixth conductive portion, the orthographic projection of the sixth conductive portion on the base substrate at least partially overlaps with the orthographic projection of the fifth conductive portion on the base substrate, for forming The second electrode of the capacitor, and the sixth conductive part is located on the base substrate orthographic projection of the third grid line on the base substrate and is far from the first grid line on the substrate.
  • the third direction is a row direction
  • the display panel further includes a first pixel driving circuit and a second pixel driving circuit that are arranged adjacently in the row direction
  • the second conductive layer It also includes: a first connection part, and the first connection part is connected to the same power supply line as the driving transistor in the first pixel driving circuit; wherein, the first connection part is orthographically projected on the base substrate to be connected to the power supply line.
  • the orthographic projection of the first gate of the second transistor in the second pixel driving circuit on the base substrate at least partially overlaps.
  • the first grid line, the third grid line, the third conductive portion, and the fourth conductive portion are formed in the same layer by an optical proximity correction mask technology.
  • a display device wherein the display device includes the above-mentioned display panel.
  • FIG. 1 is a top view of the disclosed thin film transistor in an exemplary embodiment
  • Fig. 2 is the sectional view of the position of dotted line A in Fig. 1;
  • FIG. 3 is a schematic structural diagram of another exemplary embodiment of the disclosed thin film transistor
  • FIG. 4 is a top view of another exemplary embodiment of the disclosed thin film transistor
  • Fig. 5 is the sectional view of the position of dotted line B in Fig. 4;
  • FIG. 6 is a top view of another exemplary embodiment of the disclosed thin film transistor
  • Fig. 7 is a sectional view of the position of dotted line C in Fig. 6;
  • FIG. 8 is a schematic structural diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 9 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 8;
  • FIG. 10 is a structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • Fig. 11 is the structural layout of the active layer in Fig. 10;
  • Fig. 12 is the structural layout of the first conductive layer in Fig. 10;
  • Fig. 13 is the structural layout of the second conductive layer in Fig. 10;
  • Fig. 14 is the structural layout of the third conductive layer in Fig. 10;
  • Fig. 15 is the structural layout of the active layer and the first conductive layer in Fig. 10;
  • FIG. 16 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in FIG. 10;
  • FIG. 17 is a partial structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 18 is a partial structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 19 is a partial cross-sectional view at the dotted line A in Figure 10;
  • FIG. 20 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • 21 is a schematic diagram of a partial structure of a mask in the optical proximity correction mask technology of the present disclosure.
  • FIG. 22 is a graph showing the relationship between the drain current of the second transistor and the gate-source voltage difference in the display panel of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a top view of an exemplary embodiment of the thin film transistor disclosed in the disclosure
  • FIG. 2 is a cross-sectional view at the position of dotted line A in FIG. 1 .
  • FIG. 1 only shows the structural layout of the semiconductor material layer in the thin film transistor.
  • the thin film transistor may include: a semiconductor material layer, a first insulating layer 3, and a gate layer.
  • the semiconductor material layer is located on one side of a base substrate, and the semiconductor material layer may include a first channel portion 21 , a first doped portion 23 , and a second channel portion 22 connected in sequence.
  • the first insulating layer 3 may be located on the side of the semiconductor material layer away from the base substrate 1 .
  • the gate layer is located on the side of the first insulating layer 3 away from the base substrate 1 .
  • the gate layer may include: a first gate part 41 and a second gate part 42 .
  • the orthographic projection of the first gate portion 41 on the base substrate 1 may cover the orthographic projection of the first channel portion 21 on the base substrate 1 , and the first gate portion 41 is used for receiving a gate driving signal;
  • the orthographic projection of the second gate portion 42 on the base substrate 1 may cover the orthographic projection of the second channel portion 22 on the base substrate 1 , and the second The grid part is suspended.
  • the floating arrangement of the second gate portion can be understood as that when the thin film transistor is placed or operated independently, the second gate portion is not electrically connected to any conductive structure.
  • the first gate part 41 When the thin film transistor is in operation, only the first gate part 41 is connected to the control signal terminal, and the second gate part 42 is not connected to any signal terminal.
  • the first gate part 41 receives the turn-on signal, and the first channel part 21 and the second channel part 22 can generate a conductive channel under the action of the electric field of the first gate part 41 .
  • the voltage of the second gate portion 42 can be changed under the coupling action of the first gate portion 41 , so that the second channel portion 22 can further enhance the conduction of its conductive channel under the action of the electric field of the second gate portion 42 . ability.
  • the second gate portion 42 will affect the electric field between the source and the drain of the thin film transistor, and the effect includes: the second gate portion 42 induces an electric field between the source and drain of the thin film transistor.
  • the internal electric field opposite to the source-drain electric field, that is, the second gate portion 42 reduces the electric field between the source and drain of the thin film transistor, thereby reducing the leakage current between the source and the drain.
  • the orthographic projection of the second gate portion on the base substrate may coincide with the orthographic projection of the second channel portion on the base substrate.
  • the orthographic projection of the first gate portion on the base substrate may coincide with the orthographic projection of the first channel portion on the base substrate.
  • the thin film transistor may be an N-type transistor or a P-type transistor, and this exemplary embodiment may be described by taking a P-type transistor as an example.
  • the material of the semiconductor material layer may be a polysilicon semiconductor, wherein the first doping portion 23 may be a polysilicon conductor formed by doping ions of a polysilicon semiconductor, and the first channel portion 21 and the second channel portion 22 may be non-conductive.
  • Doped polycrystalline silicon semiconductor can all be polycrystalline silicon conductors formed by doping ions with polycrystalline silicon semiconductors, and all the channel parts can be undoped polycrystalline silicon semiconductors.
  • the thin film transistor may be a low temperature polysilicon transistor.
  • low temperature polysilicon transistors have higher carrier mobility and reaction speed.
  • the difficult process difficulty of low temperature polysilicon transistors is that they have large turn-off leakage currents.
  • the thin film transistor provided by the present disclosure can be a low temperature polysilicon transistor, and the low temperature polysilicon transistor can overcome the technical difficulty of large leakage current.
  • the semiconductor material layer may also be formed of other materials, for example, the semiconductor material layer may be formed of a metal oxide semiconductor, for example, the semiconductor material layer may be formed of indium gallium zinc oxide.
  • the orthographic projection of the first channel portion 21 on the base substrate 1 may be a rectangle, and the first doping portion 23 is on the substrate
  • the orthographic projection of the substrate 1 may be a rectangle, the orthographic projection of the second channel portion 22 on the base substrate 1 may be a rectangle; the orthographic projection of the first channel portion 21 on the base substrate 1,
  • the orthographic projection of the first doping portion 23 on the base substrate 1 and the orthographic projection of the second channel portion 22 on the base substrate 1 are sequentially distributed along the first direction X; and the first channel
  • the orthographic projection of the portion 21 on the base substrate 1 , the orthographic projection of the first doping portion 23 on the base substrate 1 , and the orthographic projection of the second channel portion 22 on the base substrate 1 Projections can be combined to form rectangles.
  • the orthographic projection of the first channel portion 21 on the base substrate 1 and the orthographic projection of the first doping portion 23 on the base substrate 1 , and the orthographic projection of the second channel portion 22 on the base substrate 1 may also be other shapes, for example, the orthographic projection of the first channel portion 21 on the base substrate 1, the first The orthographic projection of a doping portion 23 on the base substrate 1 and the orthographic projection of the second channel portion 22 on the base substrate 1 may be trapezoidal or the like.
  • the pattern formed by the orthographic combination of the base substrate 1 may also be in other shapes, which all belong to the protection scope of the present disclosure.
  • the absolute value of the voltage is larger.
  • the dimension of the first channel portion 21 on the base substrate 1 in the orthographic projection of the first direction X is S1
  • the second channel portion 22 is on the substrate
  • the size of the orthographic projection of the substrate 1 on the first direction X is S2; wherein, the value of S1/S2 may be 3-15.
  • the size of the first doped portion on the orthographic projection of the base substrate in the first direction is L; wherein, the value of S1/L may be 3-15.
  • the size of the second channel portion 22 on the base substrate 1 is orthographically projected on the first direction X
  • the thin film transistor has lower leakage current and closer threshold voltage than the structure without the second channel portion and the second gate portion.
  • S1 may be equal to 2.8-3.2 microns, for example, S1 may be equal to 2.8 microns, 3 microns, 3.2 microns;
  • S2 may be equal to 0.2-0.8 microns, for example, S2 may be equal to 0.2 microns, 0.3 microns , 0.5 microns, 0.8 microns;
  • L may be equal to 0.2-0.8 microns, for example, L may be equal to 0.2 microns, 0.3 microns, 0.5 microns, 0.8 microns.
  • S2 may be equal to L, for example, both S2 and L may be equal to 0.5 microns.
  • the semiconductor material layer may further include: a second doping part 24 and a third doping part 25 , and the second doping part 24 may be connected to the first doping part 24 .
  • the channel portion 21 ; the third doping portion 25 can be connected to the second channel portion 22 .
  • the thin film transistor may further include a second insulating layer 5 and a source/drain layer, and the second insulating layer 5 is located on the side of the gate layer away from the base substrate 1 .
  • the first insulating layer 3 and the second insulating layer 5 are formed with first vias 51 penetrating the first insulating layer and the second insulating layer, and the first insulating layer and The second via hole 52 of the second insulating layer, the orthographic projection of the first via hole 51 on the base substrate may be located on the orthographic projection of the second doping portion 24 on the base substrate 1, The orthographic projection of the second via hole 52 on the base substrate may be located on the orthographic projection of the third doping portion 25 on the base substrate.
  • the source/drain layer may be located on the side of the second insulating layer 5 away from the base substrate, and the source/drain layer may include: a first conductive part 61 and a second conductive part 62 , and the first conductive part 61 may
  • the second doping part 24 is connected through the first via hole 51 to form the first electrode of the thin film transistor; the second conductive part 62 can be connected to the third doping part 24 through the second via hole 52
  • the miscellaneous part 25 is used to form the second electrode of the thin film transistor.
  • FIG. 3 it is a schematic structural diagram of another exemplary embodiment of the thin film transistor of the present disclosure.
  • a buffer layer 7 may be provided on one side of the base substrate 1 , and the thin film transistor may be provided on a side of the buffer layer 7 away from the base substrate 1 .
  • FIG. 4 is a top view of another exemplary embodiment of the thin film transistor of the present disclosure
  • FIG. 5 is a cross-sectional view of the dotted line B in FIG. 4
  • FIG. 4 only shows the structure layout of the semiconductor material layer in the thin film transistor.
  • the semiconductor material layer may further include: a fourth doping part 26 and a third channel part 27 , and the fourth doping part 26 may be connected between the first channel part 21 and the second doping part 24 .
  • the third channel portion 27 may be connected between the second doping portion 24 and the fourth doping portion 26 .
  • the gate layer may further include: a third gate portion 43 , and the orthographic projection of the third gate portion 43 on the base substrate may cover the orthographic projection of the third channel portion on the base substrate. Projection, the third grid portion 43 may be electrically connected to the first grid portion 41 .
  • the first gate part 41 and the third gate part 43 can be connected to the control signal terminal at the same time.
  • the third channel portion 27 can further reduce the leakage current when the thin film transistor is turned off.
  • FIG. 6 is a top view of another exemplary embodiment of the thin film transistor of the present disclosure
  • FIG. 7 is a cross-sectional view at the position of dotted line C in FIG. 6
  • FIG. 6 only shows the structure layout of the semiconductor material layer in the thin film transistor.
  • the semiconductor material layer may further include: a fourth doping part 26 and a third channel part 27 , and the fourth doping part 26 is connected between the second channel part 22 and the third doping part 25 ;
  • the third channel portion 27 may be connected between the third doping portion 25 and the fourth doping portion 26 .
  • the gate layer may further include: a third gate portion 43, and the orthographic projection of the third gate portion 43 on the base substrate may cover the third channel portion 27 on the base substrate.
  • the third grid portion 43 may be electrically connected to the first grid portion 41 .
  • the first gate part 41 and the third gate part 43 can be connected to the control signal terminal at the same time.
  • the third channel portion 27 can further reduce the leakage current when the thin film transistor is turned off.
  • the present exemplary embodiment also provides a display panel including at least one of the above-mentioned thin film transistors.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the second pole of the first transistor T1 is connected to the node N, the first pole is connected to the initial signal terminal Vinit, and the gate is connected to the reset signal terminal Re;
  • the first pole of the second transistor T2 is connected to the first pole of the driving transistor T3, and the second pole is connected
  • the gate is connected to the gate driving signal terminal Gate;
  • the gate of the driving transistor T3 is connected to the node N;
  • the first pole of the fourth transistor T4 is connected to the data signal terminal Da, and the second pole is connected to the second pole of the driving transistor T3,
  • the gate is connected to the gate driving signal terminal Gate;
  • the first pole of the fifth transistor T5 is connected to the first power supply signal terminal VDD, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the sixth transistor The first pole of T6 is connected to the first pole of the driving transistor T3, the gate is connected to the enable signal terminal EM;
  • the first pole of the seventh transistor T7 is connected to the
  • the pixel driving circuit may be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power terminal VSS.
  • the transistors T1-T7 may all be P-type transistors.
  • FIG. 9 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 8 .
  • Gate represents the timing of the gate driving signal terminal Gate
  • Re represents the timing of the reset signal terminal Re
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.
  • the reset signal terminal Re outputs a low level signal
  • the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal terminal Vinit inputs the initial signal to the node N and the second pole of the sixth transistor T6.
  • the gate driving signal terminal Gate outputs a low level signal
  • the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da outputs a driving signal to write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the output current I ( ⁇ WCox/2L)(Vdata+Vth ⁇ Vdd ⁇ Vth) 2 of the driving transistor in the pixel driving circuit of the present disclosure.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the node N in the pixel driving circuit is likely to leak electricity through the first transistor T1 and the second transistor T2, thereby affecting normal display.
  • the first transistor T1 and the second transistor T2 in the pixel driving circuit can adopt the structure of the above-mentioned thin film transistor, so that the leakage current of the node N through the first transistor T1 and the second transistor T2 can be reduced.
  • the transistors in the pixel driving circuit may be low temperature polysilicon transistors. Low-temperature polysilicon transistors have high carrier mobility, which is beneficial for realizing display panels with high resolution, high reaction speed, high pixel density, and high aperture ratio.
  • the above-mentioned thin film transistor can also be applied to other circuit structures in the display panel, for example, the above-mentioned thin film transistor can also be applied to the gate driving circuit in the display panel.
  • the pixel driving circuit in the display panel may also have other circuit structures, and correspondingly, the above-mentioned thin film transistor may be applied to the transistor connected to the gate of the driving transistor.
  • the driving transistor may refer to a transistor in the pixel driving circuit that provides a driving current to the light-emitting unit according to a data signal.
  • the display panel may include a base substrate, an active layer, a first conductive layer, a second conductive layer, and a third conductive layer that are stacked in sequence, wherein the active layer is disposed on the bottom of the base substrate.
  • the first conductive layer is disposed on the side of the active layer away from the base substrate
  • the second conductive layer is disposed on the side of the first conductive layer away from the base substrate
  • the second conductive layer is disposed on the side of the first conductive layer away from the substrate
  • the third conductive layer is disposed on the side of the second conductive layer away from the base substrate. As shown in FIGS. 10-16 , FIG.
  • FIG. 10 is a structural layout of an exemplary embodiment of a display panel of the present disclosure
  • FIG. 11 is a structural layout of the active layer in FIG. 10
  • FIG. 12 is a structural layout of the first conductive layer in FIG. 10 Layout
  • Fig. 13 is the structural layout of the second conductive layer in Fig. 10
  • Fig. 14 is the structural layout of the third conductive layer in Fig. 10
  • Fig. 15 is the structural layout of the active layer and the first conductive layer in Fig. 10, Fig. 16 It is a structural layout of the active layer, the first conductive layer and the second conductive layer in FIG. 10 .
  • the active layer may include: a first active part 71 , a second active part 72 , a third active part 73 , a fourth active part 74 , and a fifth active part part 75 , sixth active part 76 , seventh active part 77 , eighth active part 78 , ninth active part 79 , tenth active part 710 , and eleventh active part 711 .
  • the first active part 71 can be used to form the first channel part of the first transistor T1; the second active part 72 can be used to form the second channel part of the first transistor T1.
  • the orthographic projection of the first active part 71 on the base substrate and the orthographic projection of the second active part 72 on the base substrate may be distributed along the fourth direction Y.
  • the third active part 73 can be used to form the third channel part of the first transistor T1; the fourth active part 74 can be used to form the fourth doping part of the first transistor T1.
  • the fifth active part 75 can be used to form the first channel part of the second transistor T2; the sixth active part 76 can be used to form the second channel part of the second transistor T2.
  • the seventh active part 77 may be used to form the channel part of the seventh transistor T7.
  • the eighth active part 78 can be used to form the channel part of the fifth transistor T5
  • the ninth active part 79 can be used to form the channel part of the fourth transistor T4
  • the tenth active part 710 can be used to form the driving transistor
  • the channel portion of T3 and the eleventh transistor T11 may be used to form the channel portion of the sixth transistor T6.
  • the first conductive layer may include a first gate line Re, a third conductive part 13 , a third gate line Gate, a fourth conductive part 14 , a fifth gate line EM, a fifth Conductive part 15 .
  • the first gate line Re is used to provide the reset signal terminal Re in FIG.
  • the first gate line Re may extend along the third direction X on the orthographic projection of the base substrate, and the first gate line Re
  • the orthographic projection on the base substrate may cover the orthographic projection of the first active portion 71 on the base substrate, and part of the first gate line Re may be used to form the first gate line of the first transistor T1
  • the third direction X and the fourth direction Y may intersect, for example, the third direction X and the fourth direction Y are perpendicular.
  • the orthographic projection of the first grid line Re on the base substrate may also cover the orthographic projection of the third active portion 73 on the base substrate, and part of the first grid line Re may be used to form the the third gate of the first transistor T1.
  • the third gate line Gate may be used to provide the gate driving signal terminal Gate in FIG. 8 , the third gate line Gate may extend along the third direction X on the orthographic projection of the base substrate, and the third gate line Gate may extend along the third direction X.
  • the orthographic projection of the gate line Gate on the base substrate may cover the orthographic projection of the fifth active portion 75 on the base substrate, and part of the third gate line Gate may be used to form the second transistor T2 of the first gate.
  • the orthographic projection of the third conductive portion 13 on the base substrate may cover the orthographic projection of the second active portion 72 on the base substrate, and the third conductive portion 13 may be used to form the first transistor T1. second gate.
  • the orthographic projection of the fourth conductive portion 14 on the base substrate may cover the orthographic projection of the sixth active portion 76 on the base substrate, and the fourth conductive portion 14 may be used to form the second transistor The second gate of T2.
  • the fifth conductive portion 15 may be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C.
  • the gate of the seventh transistor T7 may share part of the structure of the first gate line Re in the previous pixel row.
  • the second conductive layer may include: a sixth conductive portion 56 , a first connection portion 55 , and a second gate line Vinit.
  • the orthographic projection of the sixth conductive portion 56 on the base substrate may at least partially overlap with the orthographic projection of the fifth conductive portion 15 on the base substrate, and the sixth conductive portion 56 may be used to form the first portion of the capacitor C.
  • the sixth conductive portion 56 may be provided with an opening 561 .
  • the second gate line Vinit may be used to provide the initial signal terminal Vinit in FIG. 8 , and the second gate line Vinit may extend along the third direction X on the orthographic projection of the base substrate.
  • the second transistor T2 may be a double-gate structure, that is, the second transistor T2 includes a second gate for forming the second gate.
  • the second transistor T2 may further include a gate electrode 121 and a gate electrode 122.
  • the second transistor T2 includes two channel portions corresponding to the gate electrode 121 and the gate electrode 122, respectively.
  • the gate 121 and the gate 122 may be located in the first conductive layer, and the two channel portions corresponding to the gate 121 and the gate 122 may be located in the active layer.
  • the second transistor T2 of the double gate structure may have a smaller leakage current.
  • the first transistor T1 may further include another gate 17 arranged in suspension.
  • the first transistor T1 includes a The semiconductor channel portion corresponding to the gate 17 may be located in the active layer, and the orthographic projection of the semiconductor channel portion on the base substrate may coincide with the orthographic projection of the gate 17 on the base substrate.
  • the first transistor T1 may be provided with two floating gates, so that the first transistor T1 has a smaller leakage current.
  • the second gate of the transistor may also be located in other conductive layers, for example, the fourth conductive portion 14 serving as the second gate of the second transistor T2 may be located in the second conductive layer.
  • the second gate electrodes of the transistors may also be located in the other conductive layers.
  • the second gate of the transistor may be located on any one of the above-mentioned conductive layers. .
  • the light-shielding metal layer may be located on the side of the active layer close to the base substrate, and is used to shield the channel portion of the transistor from light.
  • the transistor may further include a plurality of floating gates, and the orthographic projection of the plurality of floating gates on the base substrate may coincide with the orthographic projection of the second channel of the transistor on the base substrate.
  • the floating gate of the transistor may adopt a double-layer structure, that is, the plurality of floating gates may include two conductive parts, and the two conductive parts may be respectively disposed on both sides of the second channel part of the transistor in the stacking direction or on one of the two conductive parts. side.
  • the orthographic projections of the plurality of floating gates of the transistor on the substrate substrate may also be located at different positions.
  • the transistor may further include a plurality of semiconductor channel portions corresponding to the floating gates, and the semiconductor channel portions are located on the substrate.
  • the orthographic projection of the substrate may be coincident with the orthographic projection of the corresponding floating gate on the substrate.
  • the orthographic projection of the floating gate on the base substrate may be located on one or both sides of the normal gate of the transistor on the orthographic projection of the base substrate, wherein the normal gate of the transistor may refer to the gate receiving the gate driving signal.
  • one of the first transistor T1 and the second transistor T2 may be a metal oxide transistor, and the other may be a low temperature polysilicon transistor. Metal oxide transistors have less leakage current.
  • the display panel may include a first active layer, a first gate layer, a second active layer, and a second gate layer that are stacked in sequence.
  • the first active layer can be formed of polycrystalline silicon, and part of the first active layer can be used as the channel portion of the low temperature polycrystalline silicon transistor;
  • the second active layer can be formed of metal oxide (eg, indium gallium zinc oxide IGZO) , part of the second active layer can be used as the channel part of the metal oxide transistor;
  • part of the first gate layer can be used to form the gate of the low temperature polysilicon transistor, part of the first gate layer can be used to form the gate of the metal oxide transistor Bottom gate, part of the second gate layer is used to form the top gate of the metal oxide transistor.
  • the floating gate of the low temperature polysilicon transistor can be formed by one or more of the conductorized part of the second active layer, part of the first gate layer, and part of the second gate layer.
  • the third conductive layer may include a data line Da, a power line VDD, a second connection portion 32 and a third connection portion 33 .
  • the data line Da may be used to provide the data signal terminal Da in FIG. 8 , and the orthographic projection of the data line Da on the base substrate may extend along the fourth direction Y.
  • the power supply line VDD may be used to provide the first power supply terminal VDD in FIG. 8 , and the orthographic projection of the power supply line VDD on the base substrate may extend along the fourth direction Y.
  • the data line Da is connected to the ninth active part 79 through the via hole 91 to connect the data signal terminal and the first pole of the fourth transistor T4.
  • the power line VDD may be connected to the eighth active part 78 through the via hole 92 to connect the first power terminal and the first pole of the fifth transistor T5.
  • the power supply line VDD is also connected to the sixth conductive portion 56 through the via hole 93 to connect the second electrode portion of the capacitor C and the first power supply terminal.
  • the power line VDD is also connected to the first connection part 55 through the via hole 94 .
  • the second connection part 32 may be connected to the second active part 72 through the via hole 95 and the second gate line Vinit through the via hole 96 to connect the second electrode of the first transistor T1 and the initial signal terminal.
  • the third connection part 33 may be connected to the fifth conductive part 15 through the via hole 97 and the sixth active part 76 through the via hole 98 to connect the second electrode of the second transistor T2 and the gate of the driving transistor T3.
  • the orthographic projection of the via hole 97 on the base substrate may be located within the orthographic projection of the opening 561 on the base substrate.
  • the orthographic projection of the third conductive portion 13 on the base substrate may be located at the first gate line Re on the base substrate and away from the second gate line Vinit at the orthographic projection. one side of the base substrate which is orthographically projected.
  • this setting can reserve sufficient layout space for the third conductive part 13;
  • the second gate line Vinit reduces the voltage change of the third conductive portion 13 with the first gate line Re, thereby reducing the conduction degree of the first transistor T1.
  • the third conductive portion 13 is disposed away from the second gate line Vinit, which can reduce the voltage stabilization effect of the second gate line Vinit on the third conductive portion 13, thereby reducing the effect of the second gate line Vinit on the degree of conduction of the first transistor. influences.
  • the orthographic projection of the third conductive portion 13 on the base substrate may also be located near the second gate line Re on the orthographic projection of the base substrate.
  • the gate line Vinit is on the side of the orthographic projection of the base substrate, which all belong to the protection scope of the present disclosure.
  • the fourth active portion 74 will be coupled with the first gate line Re, and the voltage of the fourth active portion 74 will change with the change of the potential of the first gate line Re, As a result, the fourth active part 74 leaks electricity to the source/drain of the first transistor T1.
  • the orthographic projection of the fourth active portion 74 on the base substrate may be located at the orthographic projection of the first gate line Re on the base substrate away from the third conductive portion 13 . one side of the base substrate which is orthographically projected.
  • the orthographic projection of the second gate line Vinit on the base substrate may at least partially overlap with the orthographic projection of the fourth active portion 74 on the base substrate.
  • the second gate line Vinit can stabilize the fourth active portion 74, thereby preventing the fourth active portion 74 from leaking electricity to the source/drain of the first transistor T1.
  • the orthographic projection of the first active part 71 on the base substrate may be located at the orthographic projection of the third active part 73 on the base substrate away from the power supply line VDD is on the side of the orthographic projection of the base substrate.
  • this arrangement can reserve sufficient layout space for the third conductive portion 13;
  • the conductive portion 13 changes with the voltage of the first gate line Re, thereby reducing the degree of conduction of the first transistor T1.
  • the third conductive portion 13 is disposed away from the power supply line VDD, which can reduce the voltage stabilization effect of the power supply line VDD on the third conductive portion 13, thereby reducing the influence of the power supply line VDD on the conduction degree of the first transistor.
  • the orthographic projection of the first active portion on the base substrate may also be located close to the orthographic projection of the third active portion 73 on the base substrate.
  • the power supply line VDD is on the side of the orthographic projection of the base substrate, which all belong to the protection scope of the present disclosure.
  • the orthographic projection of the sixth conductive portion 56 on the base substrate may be located at the third gate line Gate on the base substrate and away from the first gate line Re on the orthographic projection of the first gate line Re.
  • the side of the orthographic projection of the base substrate; wherein, the fourth conductive portion 14 may be located on the orthographic projection of the base substrate and the third gate line Gate on the orthographic projection of the base substrate and the first gate line Re is between the orthographic projections of the base substrate.
  • this arrangement can reserve sufficient layout space for the fourth conductive portion 14; on the other hand, since the sixth conductive portion 56 is connected to the power supply line VDD, the sixth conductive portion 56 will The variation of the voltage of the fourth conductive portion 14 with the third gate line Gate is reduced, thereby reducing the degree of conduction of the second transistor T2.
  • the fourth conductive portion 14 is disposed away from the sixth conductive portion 56 , which can reduce the voltage stabilization effect of the sixth conductive portion 56 on the fourth conductive portion 14 , thereby reducing the conduction of the sixth conductive portion 56 to the second transistor. The influence of the degree of communication.
  • the fourth conductive portion 14 may be located on the orthographic projection of the base substrate, and the third gate line Gate may be located close to the sixth gate on the orthographic projection of the base substrate The conductive portion 56 is between the orthographic projections of the base substrate.
  • the display panel may further include a buffer layer 111 , a first insulating layer 112 , a second insulating layer 113 , and a dielectric layer 114 .
  • the base substrate 1, the active layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the dielectric layer, and the third conductive layer are stacked in sequence.
  • the insulating layer may be a silicon oxide layer
  • the dielectric layer may be a silicon nitride layer.
  • the material of the buffer layer can be silicon nitride or silicon oxide.
  • the material of the active layer may be polysilicon.
  • the first conductive layer, the second conductive layer, and the third conductive layer can all be formed by at least one metal layer.
  • the base substrate may be formed of an insulating material, for example, the base substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide layer that are arranged in sequence (PI) layer, second silicon dioxide layer.
  • the second transistor T2 may further include another floating gate located on the side of the buffer layer 111 facing the base substrate 1 , and the floating gate may be projected on the base substrate 1 with the fourth conductive portion 14 on the base substrate 1 . Orthographic coincidence.
  • the display panel can further reduce the leakage current of the first transistor T1 and the second transistor T2 by locally thinning the thickness of the first insulating layer 112 .
  • the orthographic projection of the thinned portion on the base substrate may coincide with the orthographic projection of the floating gate (eg, the fourth conductive portion 14 ) on the base substrate.
  • FIG. 20 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the third direction X may be a row direction, and the display panel may include a first pixel driving circuit 81 and a second pixel driving circuit 82 arranged adjacently in the row direction.
  • the first connection part 55 is connected to the same power supply line VDD as the driving transistor in the first pixel driving circuit 01 .
  • the orthographic projection of the first connection portion 55 on the base substrate may at least partially overlap with the orthographic projection of the first gate of the second transistor T2 in the second pixel driving circuit 82 on the base substrate.
  • the first connection portion 55 can play a signal shielding role for the gate of the second transistor T2.
  • the first conductive layer may be formed through a patterning process (including photolithography, development, and etching).
  • a patterning process including photolithography, development, and etching.
  • the pattern projected by the mask onto the photoresist changes, such as the change of the line width, the rounding of the corner, and the shortening of the line length.
  • the pattern formed by the first conductive layer is different from the preset pattern.
  • the first conductive layer may be formed by an Optical Proximity Correction (OPC, Optical Proximity Correction) technique, that is, the first gate line Re, the third gate line Gate, the third conductive portion 13 , the The four conductive parts 14 can be formed by one patterning process using the optical proximity correction mask technology.
  • OPC Optical Proximity Correction
  • the optical proximity correction mask technology pre-compensates the shape of the mask so that the pattern projected by the mask onto the photoresist is the same as the preset image.
  • FIG. 21 it is a schematic diagram of a partial structure of a mask in the optical proximity correction mask technology of the present disclosure.
  • the region 2 may represent the position of the partial structure of the active layer
  • the position of the shielding portion 901 may be used to form the third gate line
  • the position of the shielding portion 902 may be used to form the fourth conductive portion 14 .
  • the mask has pre-compensated the shielding parts 901 and 902 , so that the mask can form the third grid line and the fourth conductive part shown in FIG. 10 , wherein the fourth conductive part 14
  • the orthographic projection on the base substrate may be a rectangle, and the size of the fourth conductive portion 14 on the base substrate on the orthographic projection of the first direction X may be equal to the size of the sixth active portion 76 on the base substrate orthographic projection on the first direction X size of.
  • the active layer may be doped by using the first conductive layer as a mask, that is, the active layer covered by the first conductive layer may be doped. Portions may form polysilicon semiconductors, and portions of the active layer not covered by the first conductive layer form doped polysilicon conductors.
  • the relationship between the drain current of the second transistor and the gate-source voltage difference in the display panel of the present disclosure is shown.
  • the abscissa represents the gate-source voltage difference of the second transistor, and the ordinate represents the drain current of the second transistor.
  • Curves 101 , 102 and 103 respectively represent the leakage current curves of the second transistor with different structures and sizes.
  • the curve 101 represents the leakage current of the second transistor in the conventional technology.
  • the second transistor is not provided with the second gate and the second channel portion, wherein the length and width of the channel portion of the second transistor can be both 3 ⁇ m.
  • Curve 102 represents the addition of a second gate and a second channel structure on the basis of the second transistor shown in curve 101.
  • the structure of the second transistor may be as shown in Figures 1 and 2, wherein the first transistor in the second transistor
  • the dimension S2 of the channel portion on the base substrate in the orthographic projection on the first direction is 0.2 ⁇ m
  • the dimension L of the first doping portion on the base substrate on the orthographic projection on the first direction is 0.3 microns.
  • Curve 103 represents the addition of a second gate and a second channel structure on the basis of the second transistor shown in curve 101.
  • the structure of the second transistor may be as shown in Figures 1 and 2, wherein the first transistor in the second transistor
  • the dimension S2 of the channel portion on the base substrate in the orthographic projection of the first direction is 0.5 ⁇ m
  • the dimension L of the first doping portion on the base substrate in the orthographic projection of the first direction is 0.5 microns.
  • the orthographic projection of the first channel portion in the second transistor on the base substrate in the first direction S2 is 0.5 ⁇ m
  • the orthographic projection of the first doped portion on the base substrate when the dimension L in the first direction is 0.5 ⁇ m, the second transistor has a smaller leakage current, and the second transistor corresponding to curve 103 and the second transistor corresponding to curve 101 have similar threshold voltages.
  • the second transistor corresponding to the curve 103 can reduce the leakage current in the turn-off phase by an order of magnitude.
  • the present exemplary embodiment also provides a display device including the above-mentioned display panel.
  • the display device may be a display device such as a mobile phone, a tablet computer, or the like.

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Abstract

本公开涉及显示技术领域，提出一种薄膜晶体管、显示面板及显示装置。该薄膜晶体管包括：半导体材料层、第一绝缘层（3）、栅极层。半导体材料层位于一衬底基板（1）的一侧，半导体材料层包括依次连接的第一沟道部（21）、第一掺杂部（23）、第二沟道部（22）；第一绝缘层位于半导体材料层背离衬底基板的一侧；栅极层位于第一绝缘层背离半导体材料层的一侧，栅极层包括：第一栅极部（41）、第二栅极部（42），第一栅极部在衬底基板的正投影与第一沟道部在衬底基板的正投影重合，且第一栅极部用于接收栅极驱动信号；第二栅极部在衬底基板的正投影与第二沟道部在衬底基板的正投影重合，且第二栅极部悬浮设置。该薄膜晶体管具有较小的漏电流。

Description

薄膜晶体管、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管、显示面板及显示装置。
背景技术
薄膜晶体管通常作为开关器件应用于各种电器中，然而薄膜晶体管容易在关断状态下产生漏电流，从而应用电器的正常运行。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种薄膜晶体管，该薄膜晶体管包括：半导体材料层、第一绝缘层、栅极层。半导体材料层位于一衬底基板的一侧，所述半导体材料层包括依次连接的第一沟道部、第一掺杂部、第二沟道部。第一绝缘层位于所述半导体材料层背离所述衬底基板的一侧。栅极层，位于所述第一绝缘层背离所述衬底基板的一侧，所述栅极层包括：第一栅极部、第二栅极部。所述第一栅极部在所述衬底基板的正投影覆盖所述第一沟道部在所述衬底基板的正投影，且所述第一栅极部用于接收栅极驱动信号；所述第二栅极部在所述衬底基板的正投影覆盖所述第二沟道部在所述衬底基板的正投影，且所述第二栅极部悬浮设置。
本公开一种示例性实施例中，所述第一沟道部在所述衬底基板的正投影为矩形，所述第一掺杂部在所述衬底基板的正投影为矩形，所述第二沟道部在所述衬底基板的正投影为矩形；所述第一沟道部在所述衬底基板的正投影、所述第一掺杂部在所述衬底基板的正投影、第二沟道部在所述衬底基板的正投影沿第一方向依次分布；且所述第一沟道部在所述衬底基板的正投影、所述第一掺杂部在所述衬底基板的正投影、以及所述第二沟道部在所述衬底基板的正投影组合形成矩形。
本公开一种示例性实施例中，所述第一沟道部在所述衬底基板正投影在所述第一方向上的尺寸为S1，所述第二沟道部在所述衬底基板正投影在所述第一方向上的尺寸为S2；其中，S1/S2的值为3-15。
本公开一种示例性实施例中，所述第一掺杂部在所述衬底基板正投影在所述第一方向上的尺寸为L；其中，S1/L的值为3-15。
本公开一种示例性实施例中，S1等于2.8-3.2微米，S2等于0.2-0.8微米，L等于0.2-0.8 微米。
本公开一种示例性实施例中，所述半导体材料层的材料为多晶硅半导体。
本公开一种示例性实施例中，所述半导体材料层还包括：第二掺杂部、第三掺杂部，第二掺杂部连接所述第一沟道部；第三掺杂部连接所述第二沟道部。所述薄膜晶体管还包括第二绝缘层、源/漏层，第二绝缘层位于所述栅极层背离所述衬底基板的一侧；其中，所述第一绝缘层和所述第二绝缘层上形成有贯穿所述第一绝缘层和所述第二绝缘层的第一过孔，以及贯穿所述第一绝缘层和所述第二绝缘层第二过孔，所述第一过孔在所述衬底基板的正投影位于所述第二掺杂部在所述衬底基板的正投影上，所述第二过孔在所述衬底基板的正投影位于所述第三掺杂部在所述衬底基板的正投影上。源/漏层位于所述第二绝缘层背离所述衬底基板的一侧，所述源/漏层包括：第一导电部、第二导电部，第一导电部通过所述第一过孔连接所述第二掺杂部，用于形成所述薄膜晶体管的第一极；第二导电部通过所述第二过孔连接所述第三掺杂部，用于形成所述薄膜晶体管的第二极。
本公开一种示例性实施例中，所述半导体材料层还包括：第四掺杂部、第三沟道部，第四掺杂部，接于所述第一沟道部和所述第二掺杂部之间；第三沟道部连接于所述第二掺杂部和所述第四掺杂部之间。所述栅极层还包括：第三栅极部，所述第三栅极部在所述衬底基板的正投影覆盖所述第三沟道部在所述衬底基板的正投影，所述第三栅极部与所述第一栅极部连接。
本公开一种示例性实施例中，所述半导体材料层还包括：第四掺杂部、第三沟道部，第四掺杂部连接于所述第二沟道部和所述第三掺杂部之间；第三沟道部连接于所述第三掺杂部和所述第四掺杂部之间。所述栅极层还包括：第三栅极部，所述第三栅极部在所述衬底基板的正投影覆盖所述第三沟道部在所述衬底基板的正投影，所述第三栅极部与所述第一栅极部连接。
根据本公开的一个方面，提供一种显示面板，该显示面板包括至少一个上述的薄膜晶体管。
本公开一种示例性实施例中，至少一个所述薄膜晶体管包括第一晶体管，所述显示面板包括像素驱动电路，所述像素驱动电路包括驱动晶体管、所述第一晶体管，所述第一晶体管的第一极连接所述驱动晶体管的栅极，所述第一晶体管形成所述薄膜晶体管。
本公开一种示例性实施例中，所述第一晶体管的第二极连接初始信号端，至少一个所述薄膜晶体管还包括第二晶体管，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第二极连接所述驱动晶体管的栅极，第一极连接所述驱动晶体管的第一极。
本公开一种示例性实施例中，所述显示面板包括：衬底基板、有源层、第一导电层、第二导电层。有源层位于所述衬底基板的一侧，所述有源层包括：第一有源部、第二有源部，第一有源部用于形成所述第一晶体管的第一沟道部；第二有源部用于形成所述第一晶体管的第二沟道部，所述第一有源部在所述衬底基板正投影和所述第二有源部在所述衬底基板正投影沿第四方向分布。第一导电层位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括：第一栅线、第三导电部，所述第一栅线在所述衬底基板正投影沿第三方向延伸，且所述第一栅线在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影，部分所述第一栅线用于形成所述第一晶体管的第一栅极，所述第三方向和所述第四方向相交；所述第三导电部在所述衬底基板正投影覆盖所述第二有源部在所述衬底基板正投影，用于形成所述第一晶体管的第二栅极。第二导电层位于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括第二栅线，第二栅线用于提供所述初始信号端；其中，所述第三导电部在所述衬底基板的正投影位于所述第一栅线在所述衬底基板正投影远离所述第二栅线在所述衬底基板正投影的一侧。
本公开一种示例性实施例中，所述第一晶体管为权利要求8所述的薄膜晶体管，所述有源层还包括：第三有源部、第四有源部，第三有源部用于形成所述第一晶体管的第三沟道部；第四有源部用于形成所述第一晶体管的第四掺杂部，所述第四有源部在所述衬底基板的正投影位于所述第一栅线在所述衬底基板正投影远离所述第三导电部在所述衬底基板正投影的一侧；其中，所述第一栅线在所述衬底基板正投影还覆盖所述第三有源部在所述衬底基板的正投影，部分所述第一栅线用于形成所述第一晶体管的第三栅极；所述驱动晶体管的第二极连接第一电源端，所述显示面板还包括第三导电层，所述第三导电层位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括电源线，电源线用于提供所述第一电源端，所述电源线在所述衬底基板的正投影沿所述第四方向延伸，且所述第一有源部在所述衬底基板的正投影位于所述第三有源部在所述衬底基板正投影远离所述电源线在所述衬底基板正投影的一侧。
本公开一种示例性实施例中，所述第二栅线在所述衬底基板正投影与所述第四有源部在所述衬底基板正投影至少部分重合。
本公开一种示例性实施例中，所述像素驱动电路还包括电容，所述电容的第一电极连接于所述驱动晶体管栅极，所述电容的第二电极连接所述第一电源端，所述有源层还包括：第五有源部、第六有源部，第五有源部用于形成所述第二晶体管的第一沟道部；第六有源部用于形成所述第二晶体管的第二沟道部；所述第一导电层还包括：第三栅线、第四导电 部、第五导电部，所述第三栅线在所述衬底基板正投影沿所述第三方向延伸，且所述第三栅线在所述衬底基板的正投影覆盖所述第五有源部在所述衬底基板的正投影，部分所述第三栅线用于形成所述第二晶体管的第一栅极；所述第四导电部在所述衬底基板的正投影覆盖所述第六有源部在所述衬底基板的正投影，用于形成所述第二晶体管的第二栅极；第五导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极。所述第二导电层还包括第六导电部，所述第六导电部在所述衬底基板正投影与所述第五导电部在所述衬底基板的正投影至少部分重合，用于形成所述电容的第二电极，且所述第六导电部在所述衬底基板正投影位于所述第三栅线在所述衬底基板正投影远离所述第一栅线在所述衬底基板正投影的一侧；其中，所述第四导电部在所述衬底基板正投影位于所述第三栅线在所述衬底基板正投影和所述第一栅线在所述衬底基板正投影之间。
本公开一种示例性实施例中，所述第三方向为行方向，所述显示面板还包括在行方向上相邻设置的第一像素驱动电路和第二像素驱动电路，所述第二导电层还包括：第一连接部，第一连接部与所述第一像素驱动电路中的驱动晶体管连接同一所述电源线；其中，所述第一连接部在所述衬底基板正投影与所述第二像素驱动电路中第二晶体管第一栅极在所述衬底基板正投影至少部分重合。
本公开一种示例性实施例中，所述第一栅线、第三栅线、第三导电部、第四导电部通过光学临近修正掩膜技术同层成型。
根据本公开的一个方面，提供一种显示装置，其中，该显示装置包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开薄膜晶体管一种示例性实施例中的俯视图；
图2为图1中虚线A位置的剖视图；
图3为本公开薄膜晶体管另一种示例性实施例的结构示意图；
图4为本公开薄膜晶体管另一种示例性实施例中的俯视图；
图5为图4中虚线B位置的剖视图；
图6为本公开薄膜晶体管另一种示例性实施例中的俯视图；
图7为图6中虚线C位置的剖视图；
图8为本公开显示面板一种示例性实施例中像素驱动电路的结构示意图；
图9为图8中像素驱动电路一种驱动方法中各节点的时序图；
图10为本公开显示面板一种示例性实施例的结构版图；
图11为图10中有源层的结构版图；
图12为图10中第一导电层的结构版图；
图13为图10中第二导电层的结构版图；
图14为图10中第三导电层的结构版图；
图15为图10中有源层和第一导电层的结构版图；
图16为图10中有源层、第一导电层、第二导电层的结构版图；
图17为本公开显示面板另一种示例性实施例的部分结构版图；
图18为本公开显示面板另一种示例性实施例的部分结构版图；
图19为图10中虚线A处的部分剖视图；
图20为本公开显示面板另一种示例性实施例的结构示意图；
图21为本公开光学临近修正掩膜技术中掩膜版的部分结构示意图；
图22为本公开显示面板中第二晶体管漏电流与栅源电压差的关系曲线。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本示例性实施例首先提供一种薄膜晶体管，如图1、2所示，图1为本公开薄膜晶体管一种示例性实施例中的俯视图，图2为图1中虚线A位置的剖视图。其中，图1仅示出了薄膜晶体管中半导体材料层的结构版图。该薄膜晶体管可以包括：半导体材料层、第一绝缘层3、栅极层。半导体材料层位于一衬底基板的1一侧，所述半导体材料层可以包括依次连接的第一沟道部21、第一掺杂部23、第二沟道部22。第一绝缘层3可以位于所述 半导体材料层背离所述衬底基板1的一侧。栅极层位于所述第一绝缘层3背离所述衬底基板1的一侧。所述栅极层可以包括：第一栅极部41、第二栅极部42。所述第一栅极部41在所述衬底基板1的正投影可以覆盖所述第一沟道部21在所述衬底基板1的正投影，且所述第一栅极部41用于接收栅极驱动信号；所述第二栅极部42在所述衬底基板1的正投影可以覆盖所述第二沟道部22在所述衬底基板1的正投影，且所述第二栅极部悬浮设置。其中，第二栅极部悬浮设置可以理解为，该薄膜晶体管独立放置或工作时，第二栅极部均不与任何导电结构电连接。
该薄膜晶体管工作时，仅第一栅极部41连接控制信号端，第二栅极部42不连接任何信号端。当该薄膜晶体管需要导通时，第一栅极部41接收导通信号，第一沟道部21和第二沟道部22可以在第一栅极部41的电场作用下产生导电沟道。此外，第二栅极部42可以在第一栅极部41耦合作用下，电压发生变化，从而第二沟道部22可以在第二栅极部42电场作用下进一步加强其导电沟道的导电能力。当该薄膜晶体管需要关断时，在第一沟道部21和第二沟道部22的双重作用下，该薄膜晶体管的漏电流较小。此外，当该薄膜晶体管关断时，第二栅极部42会影响该薄膜晶体管源漏极之间的电场，该影响作用包括：第二栅极部42会在源漏极电场中感应出与源漏极电场相反的内部电场，即该第二栅极部42会降低薄膜晶体管源漏极之间的电场，从而降低源漏极之间的漏电流。
本示例性实施例中，第二栅极部在衬底基板的正投影可以与第二沟道部在衬底基板的正投影重合。第一栅极部在衬底基板的正投影可以与第一沟道部在衬底基板的正投影重合。
本示例性实施例中，薄膜晶体管可以为N型晶体管，也可以为P型晶体管，本示例性实施例可以以P型晶体管为例进行说明。所述半导体材料层的材料可以为多晶硅半导体，其中，第一掺杂部23可以为由多晶硅半导体掺杂离子后形成的多晶硅导体，第一沟道部21、第二沟道部22可以为未掺杂的多晶硅半导体。此外，在下文中提及的掺杂部均可以为由多晶硅半导体掺杂离子后形成的多晶硅导体，沟道部均可以为未掺杂的多晶硅半导体。该薄膜晶体管可以为低温多晶硅晶体管。相关技术中，低温多晶硅晶体管具有较高的载流子迁移率和反应速度，然而，低温多晶硅晶体管难以克服的工艺难点在于其具有较大的关断漏电流。本公开提供的薄膜晶体管可以为低温多晶硅晶体管，该低温多晶硅晶体管可以克服其漏电流较大的技术难点。应该理解的是，在其他示例性实施例中，半导体材料层还可以由其他材料形成，例如，半导体材料层可以由金属氧化物半导体形成，例如，半导体材料层可以由铟镓锌氧化物形成。
本示例性实施例中，如图1、2所示，所述第一沟道部21在所述衬底基板1的正投影可以为矩形，所述第一掺杂部23在所述衬底基板1的正投影可以为矩形，所述第二沟道部22在所述衬底基板1的正投影可以为矩形；所述第一沟道部21在所述衬底基板1的正投影、所述第一掺杂部23在所述衬底基板1的正投影、第二沟道部22在所述衬底基板1的正投影沿第一方向X依次分布；且所述第一沟道部21在所述衬底基板1的正投影、所述第一掺杂部23在所述衬底基板1的正投影、以及所述第二沟道部22在所述衬底基板1 的正投影可以组合形成矩形。应该理解的是，在其他示例性实施例中，所述第一沟道部21在所述衬底基板1的正投影、所述第一掺杂部23在所述衬底基板1的正投影、以及所述第二沟道部22在所述衬底基板1的正投影还可以为其他形状，例如，所述第一沟道部21在所述衬底基板1的正投影、所述第一掺杂部23在所述衬底基板1的正投影、所述第二沟道部22在所述衬底基板1的正投影可以为梯形等。所述第一沟道部21在所述衬底基板1的正投影、所述第一掺杂部23在所述衬底基板1的正投影、以及所述第二沟道部22在所述衬底基板1的正投影组合形成的图案也可以为其他形状，这些都属于本公开的保护范围。
本示例性实施例中，第二沟道部22在所述衬底基板1正投影在所述第一方向X上的尺寸越大，该薄膜晶体管关断时的漏电流越小，且其阈值电压的绝对值越大。第一掺杂部在所述衬底基板正投影在所述第一方向X上的尺寸越大，该薄膜晶体管关断时的漏电流越小，且其阈值电压的绝对值越大。本示例性实施例中，所述第一沟道部21在所述衬底基板1正投影在所述第一方向X上的尺寸为S1，所述第二沟道部22在所述衬底基板1正投影在所述第一方向X上的尺寸为S2；其中，S1/S2的值可以为3-15。所述第一掺杂部在所述衬底基板正投影在所述第一方向上的尺寸为L；其中，S1/L的值可以为3-15。当第一掺杂部在所述衬底基板正投影在所述第一方向上的尺寸、所述第二沟道部22在所述衬底基板1正投影在所述第一方向X上的尺寸为上述值时，该薄膜晶体管相对比于未设置第二沟道部和第二栅极部的结构具有较低的漏电流和较相近的阈值电压。具体的，本示例性实施例中，S1可以等于2.8-3.2微米，例如，S1可以等于2.8微米、3微米、3.2微米；S2可以等于0.2-0.8微米，例如，S2可以等于0.2微米、0.3微米、0.5微米、0.8微米；L可以等于0.2-0.8微米，例如，L可以等于0.2微米、0.3微米、0.5微米、0.8微米。其中，S2可以等于L，例如，S2和L可以均等于0.5微米。
本示例性实施例中，如图1、2所示，所述半导体材料层还可以包括：第二掺杂部24、第三掺杂部25，第二掺杂部24可以连接所述第一沟道部21；第三掺杂部25可以连接所述第二沟道部22。所述薄膜晶体管还可以包括第二绝缘层5、源/漏层，第二绝缘层5位于所述栅极层背离所述衬底基板1的一侧。其中，所述第一绝缘层3和所述第二绝缘层5上形成有贯穿所述第一绝缘层和所述第二绝缘层的第一过孔51，以及贯穿所述第一绝缘层和所述第二绝缘层第二过孔52，所述第一过孔51在所述衬底基板的正投影可以位于所述第二掺杂部24在所述衬底基板1的正投影上，所述第二过孔52在所述衬底基板的正投影可以位于所述第三掺杂部25在所述衬底基板的正投影上。源/漏层可以位于所述第二绝缘层5背离所述衬底基板的一侧，所述源/漏层可以包括：第一导电部61、第二导电部62，第一导电部61可以通过所述第一过孔51连接所述第二掺杂部24，用于形成所述薄膜晶体管的第一极；第二导电部62可以通过所述第二过孔52连接所述第三掺杂部25，用于形成所述薄膜晶体管的第二极。
本示例性实施例中，如图3所示，为本公开薄膜晶体管另一种示例性实施例的结构示 意图。衬底基板1的一侧可以设置有缓冲层7，该薄膜晶体管可以设置于缓冲层7背离衬底基板1的一侧。
本示例性实施例中，如图4、5所示，图4为本公开薄膜晶体管另一种示例性实施例中的俯视图，图5为图4中虚线B位置的剖视图。其中，图4仅示出了薄膜晶体管中半导体材料层的结构版图。所述半导体材料层还可以包括：第四掺杂部26、第三沟道部27，第四掺杂部26可以接于所述第一沟道部21和所述第二掺杂部24之间；第三沟道部27可以连接于所述第二掺杂部24和所述第四掺杂部26之间。所述栅极层还可以包括：第三栅极部43，所述第三栅极部43在所述衬底基板的正投影可以覆盖所述第三沟道部在所述衬底基板的正投影，所述第三栅极部43可以与所述第一栅极部41电连接。
该薄膜晶体管在工作时，第一栅极部41和第三栅极部43可以同时连接控制信号端。其中，第三沟道部27可以进一步降低该薄膜晶体管关断时的漏电流。
本示例性实施例中，如图6、7所示，图6为本公开薄膜晶体管另一种示例性实施例中的俯视图，图7为图6中虚线C位置的剖视图。其中，图6仅示出了薄膜晶体管中半导体材料层的结构版图。所述半导体材料层还可以包括：第四掺杂部26、第三沟道部27，第四掺杂部26连接于所述第二沟道部22和所述第三掺杂部25之间；第三沟道部27可以连接于所述第三掺杂部25和所述第四掺杂部26之间。所述栅极层还可以包括：第三栅极部43，所述第三栅极部43在所述衬底基板的正投影可以覆盖所述第三沟道部27在所述衬底基板的正投影，所述第三栅极部43可以与所述第一栅极部41电连接。
该薄膜晶体管在工作时，第一栅极部41和第三栅极部43可以同时连接控制信号端。其中，第三沟道部27可以进一步降低该薄膜晶体管关断时的漏电流。
本示例性实施例还提供一种显示面板，该显示面板包括至少一个上述的薄膜晶体管。
如图8所示，为本公开显示面板一种示例性实施例中像素驱动电路的结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第二极连接节点N，第一极连接初始信号端Vinit，栅极连接复位信号端Re；第二晶体管T2第一极连接驱动晶体管T3的第一极，第二极连接节点N；栅极连接栅极驱动信号端Gate；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第二极，栅极连接栅极驱动信号端Gate；第五晶体管T5的第一极连接第一电源信号端VDD，第二极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第七晶体管T7的第一极连接初始信号端Vinit，第二极连接第六晶体管T6的第二极，栅极连接复位信号端Re；电容C的第一电极连接驱动晶体管T3的栅极，第二电极连接第一电源信号端VDD。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，晶体管T1-T7可以均为P型晶体管。
如图9所示，为图8中像素驱动电路一种驱动方法中各节点的时序图。其中，Gate表示栅极驱动信号端Gate的时序，Re表示复位信号端Re的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：复位信号端Re输出低电平信号，第一晶体管T1、第七晶体管T7导通，初始信号端Vinit向节点N，第六晶体管T6的第二极输入初始信号。在补偿阶段t2：栅极驱动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth，其中Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压。发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
在发光阶段，像素驱动电路中的节点N容易通过第一晶体管T1和第二晶体管T2漏电，从而影响正常显示。该像素驱动电路中的第一晶体管T1和第二晶体管T2可以采用上述的薄膜晶体管的结构，从而可以降低节点N通过第一晶体管T1和第二晶体管T2的漏电流。此外，该像素驱动电路中的晶体管可以为低温多晶硅晶体管。低温多晶硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。
应该理解的是，在其他示例性实施例中，上述薄膜晶体管还可以应用于显示面板中的其他电路结构，例如，上述薄膜晶体管还可以应用于显示面板中的栅极驱动电路。该显示面板中像素驱动电路还可以为其他电路结构，相应的，上述薄膜晶体管可以应用于与驱动晶体管栅极连接的晶体管。其中，驱动晶体管可以指，像素驱动电路中根据数据信号向发光单元提供驱动电流的晶体管。
本示例性实施例中，该显示面板可以包括依次层叠设置的衬底基板、有源层、第一导电层、第二导电层、第三导电层，其中，有源层设置于衬底基板的一侧，第一导电层设置于有源层背离衬底基板的一侧，第二导电层设置于第一导电层背离衬底基板的一侧，第二导电层设置于第一导电层背离衬底基板的一侧，第三导电层设置于第二导电层背离衬底基板的一侧。如图10-16所示，图10为本公开显示面板一种示例性实施例的结构版图，图11为图10中有源层的结构版图，图12为图10中第一导电层的结构版图，图13为图10中第二导电层的结构版图，图14为图10中第三导电层的结构版图，图15为图10中有源层和第一导电层的结构版图，图16为图10中有源层、第一导电层、第二导电层的结构版图。
如图10、11、15、16所示，有源层可以包括：第一有源部71、第二有源部72、第三 有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77、第八有源部78、第九有源部79、第十有源部710、第十一有源部711。其中，第一有源部71可以用于形成所述第一晶体管T1的第一沟道部；第二有源部72可以用于形成所述第一晶体管T1的第二沟道部。第一有源部71在所述衬底基板正投影和所述第二有源部72在所述衬底基板正投影可以沿第四方向Y分布。第三有源部73可以用于形成所述第一晶体管T1的第三沟道部；第四有源部74可以用于形成所述第一晶体管T1的第四掺杂部。第五有源部75可以用于形成所述第二晶体管T2的第一沟道部；第六有源部76可以用于形成所述第二晶体管T2的第二沟道部。第七有源部77可以用于形成第七晶体管T7的沟道部。第八有源部78可以用于形成第五晶体管T5的沟道部，第九有源部79可以用于形成第四晶体管T4的沟道部，第十有源部710可以用于形成驱动晶体管T3的沟道部，第十一晶体管T11可以用于形成第六晶体管T6的沟道部。
如图10、12、15、16所示，第一导电层可以包括第一栅线Re、第三导电部13、第三栅线Gate、第四导电部14、第五栅线EM、第五导电部15。其中，第一栅线Re用于提供图8中的复位信号端Re，所述第一栅线Re在所述衬底基板正投影可以沿第三方向X延伸，且所述第一栅线Re在所述衬底基板的正投影可以覆盖所述第一有源部71在所述衬底基板的正投影，部分所述第一栅线Re可以用于形成所述第一晶体管T1的第一栅极，所述第三方向X和所述第四方向Y可以相交，例如，第三方向X和第四方向Y垂直。所述第一栅线Re在所述衬底基板正投影还可以覆盖所述第三有源部73在所述衬底基板的正投影，部分所述第一栅线Re可以用于形成所述第一晶体管T1的第三栅极。所述第三栅线Gate可以用于提供图8中的栅极驱动信号端Gate，第三栅线Gate在所述衬底基板正投影可以沿所述第三方向X延伸，且所述第三栅线Gate在所述衬底基板的正投影可以覆盖所述第五有源部75在所述衬底基板的正投影，部分所述第三栅线Gate可以用于形成所述第二晶体管T2的第一栅极。所述第三导电部13在所述衬底基板正投影可以覆盖所述第二有源部72在所述衬底基板正投影，第三导电部13可以用于形成所述第一晶体管T1的第二栅极。所述第四导电部14在所述衬底基板的正投影可以覆盖所述第六有源部76在所述衬底基板的正投影，第四导电部14可以用于形成所述第二晶体管T2的第二栅极。第五导电部15可以用于形成所述驱动晶体管T3的栅极和所述电容C的第一电极。其中，如图10、12、15、16所示，第七晶体管T7的栅极可以共用上一像素行中第一栅线Re的部分结构。
如图10、13、16所示，第二导电层可以包括：第六导电部56、第一连接部55、第二栅线Vinit。所述第六导电部56在所述衬底基板正投影可以与所述第五导电部15在所述衬底基板的正投影至少部分重合，第六导电部56可以用于形成电容C的第二电极。第六导电部56上可以设置有开口561。第二栅线Vinit可以用于提供图8中的初始信号端Vinit，第二栅线Vinit在所述衬底基板正投影可以沿所述第三方向X延伸。
如图17所示，为本公开显示面板另一种示例性实施例的部分结构版图，其中，第二晶体管T2可以为双栅结构，即第二晶体管T2除了包括用于形成其第二栅极的第四导电部 14以外，第二晶体管T2还可以包括栅极121和栅极122，相应的，第二晶体管T2包括有分别与栅极121和栅极122对应的两个沟道部。栅极121和栅极122可以位于第一导电层，与栅极121、栅极122对应的两个沟道部可以位于有源层。双栅结构的第二晶体管T2可以具有更小的漏电流。
如图18所示，为本公开显示面板另一种示例性实施例的部分结构版图，第一晶体管T1还可以包括悬浮设置的另一栅极17，相应的，第一晶体管T1包括有与该栅极17对应的半导体沟道部，该半导体沟道部可以位于有源层，且该半导体沟道部在衬底基板的正投影可以与栅极17在衬底基板的正投影重合。如图18所示，第一晶体管T1中可以设置有两个悬浮栅极，从而该第一晶体管T1具有更小的漏电流。
应该理解的是，在其他示例性实施例中，晶体管的第二栅极还可以位于其他导电层，例如，作为第二晶体管T2第二栅极的第四导电部14可以位于第二导电层。此外，在其他示例性实施例中，当显示面板包括其他导电层，晶体管的第二栅极也可以位于其他导电层。例如，当显示面板包括多层栅极层、多层源/漏层、遮光金属层、阳极层中的一层或多层时，晶体管的第二栅极可以位于上述导电层中的任意一层。其中，遮光金属层可以为位于有源层靠近衬底基板的一侧，用于对晶体管的沟道部进行遮光。在其他示例性实施例中，晶体管还可以包括多个悬浮栅极，该多个悬浮栅极在衬底基板正投影可以与晶体管第二沟道在衬底基板正投影重合。例如，晶体管的悬浮栅极可以采用双层结构，即多个悬浮栅极可以包括两个导电部，且该两个导电部可以分别设置于晶体管第二沟道部在层叠方向的两侧或一侧。此外，晶体管的多个悬浮栅极在衬底基板的正投影还可以位于不同位置，相应的，晶体管还可以包括与悬浮栅极对应设置的多个半导体沟道部，半导体沟道部在衬底基板正投影可以和与其对应的悬浮栅极在衬底基板正投影重合。悬浮栅极在衬底基板的正投影可以位于晶体管正常栅极在衬底基板正投影的一侧或两侧，其中，晶体管的正常栅极可以指接收栅极驱动信号的栅极。
应该理解的是，在其他示例性实施例中，第一晶体管T1和第二晶体管T2中的一个可以为金属氧化物晶体管，另一个可以为低温多晶硅晶体管。金属氧化物晶体管具有较小的漏电流。显示面板可以包括依次层叠设置的第一有源层、第一栅极层、第二有源层、第二栅极层。其中，第一有源层可以由多晶体硅形成，部分第一有源层可以作为低温多晶硅晶体管的沟道部；第二有源层可以有金属氧化物(例如，氧化铟镓锌IGZO)形成，部分第二有源层可以作为金属氧化物晶体管的沟道部；部分第一栅极层可以用于形成低温多晶硅晶体管的栅极，部分第一栅极层可以用于形成金属氧化物晶体管的底栅，部分第二栅极层用于形成金属氧化物晶体管的顶栅。其中，低温多晶硅晶体管的悬浮栅极可以由导体化后的部分第二有源层、部分第一栅极层、部分第二栅极层中的一种或多种形成。
如图10、14所示，第三导电层可以包括数据线Da、电源线VDD、第二连接部32、第三连接部33。其中，数据线Da可以用于提供图8中的数据信号端Da，数据线Da在衬底基板的正投影可以沿第四方向Y延伸。电源线VDD可以用于提供图8中的第一电源端 VDD，电源线VDD在衬底基板的正投影可以沿第四方向Y延伸。其中，数据线Da通过过孔91与第九有源部79连接，以连接数据信号端和第四晶体管T4的第一极。电源线VDD可以通过过孔92连接第八有源部78，以连接第一电源端和第五晶体管T5的第一极。电源线VDD还通过过孔93连接第六导电部56，以连接电容C的第二电极部和第一电源端。电源线VDD还通过过孔94连接第一连接部55。第二连接部32可以通过过孔95连接第二有源部72，通过过孔96连接第二栅线Vinit，以连接第一晶体管T1的第二极和初始信号端。第三连接部33可以通过过孔97连接第五导电部15，通过过孔98连接第六有源部76，以连接第二晶体管T2的第二极和驱动晶体管T3的栅极。其中，过孔97在衬底基板的正投影可以位于开口561在衬底基板正投影以内。
如图10、15、16所示，第三导电部13在所述衬底基板的正投影可以位于所述第一栅线Re在所述衬底基板正投影远离所述第二栅线Vinit在所述衬底基板正投影的一侧。一方面，该设置可以给第三导电部13预留充分的布图空间；另一方面，第二栅线Vinit可以输出稳定电压的初始信号，第二栅线Vinit对第三导电部13具有稳压作用，在第一晶体管T1需要导通时，第二栅线Vinit会降低第三导电部13随第一栅线Re的电压变化，从而降低第一晶体管T1的导通程度。本实施例将第三导电部13远离第二栅线Vinit设置，可以降低第二栅线Vinit对第三导电部13的稳压作用，从而降低第二栅线Vinit对第一晶体管导通程度的影响。应该理解的是，在其他示例性实施例中，第三导电部13在所述衬底基板的正投影还可以位于所述第一栅线Re在所述衬底基板正投影靠近所述第二栅线Vinit在所述衬底基板正投影的一侧，这些都属于本公开的保护范围。
如图10、11、15、16所示，第四有源部74会与第一栅线Re发生耦合作用，第四有源部74的电压会随第一栅线Re的电位变化而变化，从而导致第四有源部74向第一晶体管T1的源/漏极漏电。本示例性实施例中，所述第四有源部74在所述衬底基板的正投影可以位于所述第一栅线Re在所述衬底基板正投影远离所述第三导电部13在所述衬底基板正投影的一侧。所述第二栅线Vinit在所述衬底基板正投影可以与所述第四有源部74在所述衬底基板正投影至少部分重合。第二栅线Vinit可以对第四有源部74起到稳压作用，从而避免第四有源部74向第一晶体管T1的源/漏极漏电。
如图10、11、14所示，所述第一有源部71在所述衬底基板的正投影可以位于所述第三有源部73在所述衬底基板正投影远离所述电源线VDD在所述衬底基板正投影的一侧。一方面，该设置可以给第三导电部13预留充分的布图空间；另一方面，由于电源线VDD可以输出稳定电压，在第一晶体管T1需要导通时，电源线VDD会降低第三导电部13随第一栅线Re的电压变化，从而降低第一晶体管T1的导通程度。本示例性实施例中，第三导电部13远离电源线VDD设置，可以降低电源线VDD对第三导电部13的稳压作用，从而降低电源线VDD对第一晶体管导通程度的影响。应该理解的是，在其他示例性实施例中，所述第一有源部在所述衬底基板的正投影还可以位于所述第三有源部73在所述衬底基板正投影靠近所述电源线VDD在所述衬底基板正投影的一侧，这些都属于本公开的保 护范围。
本示例性实施例中，所述第六导电部56在所述衬底基板正投影可以位于所述第三栅线Gate在所述衬底基板正投影远离所述第一栅线Re在所述衬底基板正投影的一侧；其中，所述第四导电部14在所述衬底基板正投影可以位于所述第三栅线Gate在所述衬底基板正投影和所述第一栅线Re在所述衬底基板正投影之间。一方面，该设置可以给第四导电部14预留充分的布图空间；另一方面，由于第六导电部56连接电源线VDD，在第二晶体管T2导通阶段，第六导电部56会降低第四导电部14随第三栅线Gate的电压变化，从而降低第二晶体管T2的导通程度。本示例性实施例中，第四导电部14远离第六导电部56设置，可以降低第六导电部56对第四导电部14的稳压作用，从而降低第六导电部56对第二晶体管导通程度的影响。应该理解的是，在其他示例性实施例中，所述第四导电部14在所述衬底基板正投影可以位于所述第三栅线Gate在所述衬底基板正投影靠近所述第六导电部56在所述衬底基板正投影之间。
如图19所示，为图10中虚线A处的部分剖视图。该显示面板还可以包括缓冲层111、第一绝缘层112、第二绝缘层113、介电层114。其中，衬底基板1、有源层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、介电层、第三导电层依次层叠设置。其中，绝缘层可以为氧化硅层，介电层可以为氮化硅层。缓冲层的材料可以为氮化硅或氧化硅。有源层的材料可以为多晶硅。第一导电层、第二导电层、第三导电层均可以通过至少一层金属层形成。衬底基板可以通过绝缘材料形成，例如，衬底基板可以包括依次设置的第一聚酰亚胺(PI)层、第一氧化硅(SiO)层、非晶硅层、第二聚酰亚胺(PI)层、第二氧化硅层。其中，第二晶体管T2还可以包括位于缓冲层111面向衬底基板1一侧的另一悬浮栅极，该悬浮栅极在衬底基板1正投影可以与第四导电部14在衬底基板1正投影重合。该显示面板还可以通过局部减薄第一绝缘层112的厚度进一步降低第一晶体管T1、第二晶体管T2的漏电流。其中，该减薄部分在衬底基板正投影可以与悬浮栅极(例如，第四导电部14)在衬底基板正投影重合。
本示例性实施例中，如图20所示，为本公开显示面板另一种示例性实施例的结构示意图。所述第三方向X可以为行方向，所述显示面板可以包括在行方向上相邻设置的第一像素驱动电路81和第二像素驱动电路82。其中，第一连接部55与所述第一像素驱动电路01中的驱动晶体管连接同一所述电源线VDD。该第一连接部55在所述衬底基板正投影可以与所述第二像素驱动电路82中第二晶体管T2第一栅极在所述衬底基板正投影至少部分重合。其中，第一连接部55可以对第二晶体管T2的栅极起到信号屏蔽作用。
本示例性实施例中，第一导电层可以通过构图工艺(包括光刻、显影、刻蚀)形成。然而，在光刻工艺中，由于光的衍射效应，导致掩膜版投影至光刻胶上面的图形有所变化，如线宽的变化，转角的圆化，线长的缩短等。从而造成第一导电层形成的图案与预设图案不同。本示例性实施例中，第一导电层可以通过光学临近修正掩膜技术(OPC，Optical Proximity Correction)成型，即所述第一栅线Re、第三栅线Gate、第三导电部13、第四导 电部14可以利用光学临近修正掩膜技术通过一次构图工艺成型。光学临近修正掩膜技术是通过对掩膜版的形状进行预补偿，以使掩膜版投影至光刻胶上面的图形与预设图像相同。如图21所示，为本公开光学临近修正掩膜技术中掩膜版的部分结构示意图。其中，区域2可以表示有源层部分结构所在位置，遮挡部901所在位置可以用于形成第三栅线，遮挡部902所在位置可以用于形成第四导电部14。如图21所示，该掩膜版对遮挡部901、902进行了预补偿，从而该掩膜版能够形成图10所示的第三栅线和第四导电部，其中，第四导电部14在衬底基板正投影可以为矩形，且第四导电部14在衬底基板正投影在第一方向X上的尺寸可以等于第六有源部76在衬底基板正投影在第一方向X上的尺寸。
此外，需要说明的是，本示例性实施例提供的显示面板在制作过程中，可以通过第一导电层作为掩膜对有源层进行掺杂，即有源层中被第一导电层覆盖的部分可以形成多晶硅半导体，有源层中未被第一导电层覆盖的部分形成掺杂的多晶硅导体。
如图22所示，为本公开显示面板中第二晶体管漏电流与栅源电压差的关系曲线。其中，横坐标表示第二晶体管的栅源电压差，纵坐标表示第二晶体管的漏电流。曲线101、102、103分别表示第二晶体管在不同结构和尺寸下的漏电流曲线。曲线101表示常规技术中第二晶体管的漏电流，该第二晶体管不设置第二栅极和第二沟道部，其中，该第二晶体管沟道部的长宽均可以为3微米。曲线102表示在曲线101所示第二晶体管基础上增加第二栅极和第二沟道部结构，该第二晶体管的结构可以如图1、2所示，其中，该第二晶体管中第一沟道部在所述衬底基板正投影在所述第一方向上的尺寸S2为0.2微米，第一掺杂部在所述衬底基板正投影在所述第一方向上的尺寸L为0.3微米。曲线103表示在曲线101所示第二晶体管基础上增加第二栅极和第二沟道部结构，该第二晶体管的结构可以如图1、2所示，其中，该第二晶体管中第一沟道部在所述衬底基板正投影在所述第一方向上的尺寸S2为0.5微米，第一掺杂部在所述衬底基板正投影在所述第一方向上的尺寸L为0.5微米。如图22所示，当第二晶体管中第一沟道部在所述衬底基板正投影在所述第一方向上尺寸S2为0.5微米，第一掺杂部在所述衬底基板正投影在所述第一方向上的尺寸L为0.5微米时，第二晶体管具有较小的漏电流，且曲线103对应第二晶体管与曲线101对应第二晶体管具有相近的阈值电压。相比较于曲线101，曲线103对应的第二晶体管可以将关断阶段的漏电流降低一个数量级。
本示例性实施例还提供一种显示装置，该显示装置包括上述的显示面板。该显示装置可以为手机、平板电脑等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可 以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (19)

  1. 一种薄膜晶体管，其中，包括：
    半导体材料层，位于一衬底基板的一侧，所述半导体材料层包括依次连接的第一沟道部、第一掺杂部、第二沟道部；
    第一绝缘层，位于所述半导体材料层背离所述衬底基板的一侧；
    栅极层，位于所述第一绝缘层背离所述衬底基板的一侧，所述栅极层包括：
    第一栅极部，所述第一栅极部在所述衬底基板的正投影覆盖所述第一沟道部在所述衬底基板的正投影，且所述第一栅极部用于接收栅极驱动信号；
    第二栅极部，所述第二栅极部在所述衬底基板的正投影覆盖所述第二沟道部在所述衬底基板的正投影，且所述第二栅极部悬浮设置。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一沟道部在所述衬底基板的正投影为矩形，所述第一掺杂部在所述衬底基板的正投影为矩形，所述第二沟道部在所述衬底基板的正投影为矩形；
    所述第一沟道部在所述衬底基板的正投影、所述第一掺杂部在所述衬底基板的正投影、第二沟道部在所述衬底基板的正投影沿第一方向依次分布。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述第一沟道部在所述衬底基板正投影在所述第一方向上的尺寸为S1，所述第二沟道部在所述衬底基板正投影在所述第一方向上的尺寸为S2；
    其中，S1/S2的值为3-15。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述第一掺杂部在所述衬底基板正投影在所述第一方向上的尺寸为L；
    其中，S1/L的值为3-15。
  5. 根据权利要求4所述的薄膜晶体管，其中，S1等于2.8-3.2微米，S2等于0.2-0.8微米，L等于0.2-0.8微米。
  6. 根据权利要求1所述的薄膜晶体管，其中，所述半导体材料层的材料为多晶硅半导体。
  7. 根据权利要求1-6任一项所述的薄膜晶体管，其中，所述半导体材料层还包括：
    第二掺杂部，连接所述第一沟道部；
    第三掺杂部，连接所述第二沟道部；
    所述薄膜晶体管还包括：
    第二绝缘层，位于所述栅极层背离所述衬底基板的一侧；
    其中，所述第一绝缘层和所述第二绝缘层上形成有贯穿所述第一绝缘层和所述第二绝缘层的第一过孔，以及贯穿所述第一绝缘层和所述第二绝缘层第二过孔；
    所述第一过孔在所述衬底基板的正投影位于所述第二掺杂部在所述衬底基板的正投影上，所述第二过孔在所述衬底基板的正投影位于所述第三掺杂部在所述衬底基板的正投影上；
    源/漏层，位于所述第二绝缘层背离所述衬底基板的一侧，所述源/漏层包括：
    第一导电部，通过所述第一过孔连接所述第二掺杂部，用于形成所述薄膜晶体管的第一极；
    第二导电部，通过所述第二过孔连接所述第三掺杂部，用于形成所述薄膜晶体管的第二极。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述半导体材料层还包括：
    第四掺杂部，连接于所述第一沟道部和所述第二掺杂部之间；
    第三沟道部，连接于所述第二掺杂部和所述第四掺杂部之间；
    所述栅极层还包括：
    第三栅极部，所述第三栅极部在所述衬底基板的正投影覆盖所述第三沟道部在所述衬底基板的正投影，所述第三栅极部与所述第一栅极部连接。
  9. 根据权利要求7所述的薄膜晶体管，其中，所述半导体材料层还包括：
    第四掺杂部，连接于所述第二沟道部和所述第三掺杂部之间；
    第三沟道部，连接于所述第三掺杂部和所述第四掺杂部之间；
    所述栅极层还包括：
    第三栅极部，所述第三栅极部在所述衬底基板的正投影覆盖所述第三沟道部在所述衬底基板的正投影，所述第三栅极部与所述第一栅极部连接。
  10. 一种显示面板，其中，包括至少一个权利要求1-9任一项所述的薄膜晶体管。
  11. 根据权利要求10所述的显示面板，其中，至少一个所述薄膜晶体管包括第一晶体管，所述显示面板包括像素驱动电路，所述像素驱动电路包括驱动晶体管、所述第一晶体管，所述第一晶体管的第一极连接所述驱动晶体管的栅极，所述第一晶体管形成所述薄膜晶体管。
  12. 根据权利要求11所述的显示面板，其中，所述第一晶体管的第二极连接初始信号端，至少一个所述薄膜晶体管还包括第二晶体管，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第二极连接所述驱动晶体管的栅极，第一极连接所述驱动晶体管的第一极。
  13. 根据权利要求12所述的显示面板，其中，所述显示面板包括：
    衬底基板；
    有源层，位于所述衬底基板的一侧，所述有源层包括：
    第一有源部，用于形成所述第一晶体管的第一沟道部；
    第二有源部，用于形成所述第一晶体管的第二沟道部，所述第一有源部在所述衬底基板正投影和所述第二有源部在所述衬底基板正投影沿第四方向分布；
    第一导电层，位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括：
    第一栅线，所述第一栅线在所述衬底基板正投影沿第三方向延伸，且所述第一栅线在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影，部分所述第一栅线用于形成所述第一晶体管的第一栅极，所述第三方向和所述第四方向相交；
    第三导电部，所述第三导电部在所述衬底基板正投影覆盖所述第二有源部在所述衬底基板正投影，用于形成所述第一晶体管的第二栅极；
    第二导电层，位于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括：
    第二栅线，用于提供所述初始信号端；
    其中，所述第三导电部在所述衬底基板的正投影位于所述第一栅线在所述衬底基板正投影远离所述第二栅线在所述衬底基板正投影的一侧。
  14. 根据权利要求13所述的显示面板，其中，所述第一晶体管为权利要求8所述的薄膜晶体管，所述有源层还包括：
    第三有源部，用于形成所述第一晶体管的第三沟道部；
    第四有源部，用于形成所述第一晶体管的第四掺杂部，所述第四有源部在所述衬底基板的正投影位于所述第一栅线在所述衬底基板正投影远离所述第三导电部在所述衬底基板正投影的一侧；
    其中，所述第一栅线在所述衬底基板正投影还覆盖所述第三有源部在所述衬底基板的正投影，部分所述第一栅线用于形成所述第一晶体管的第三栅极；
    所述驱动晶体管的第二极连接第一电源端，所述显示面板还包括第三导电层，所述第三导电层位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：
    电源线，用于提供所述第一电源端，所述电源线在所述衬底基板的正投影沿所述第四方向延伸，且所述第一有源部在所述衬底基板的正投影位于所述第三有源部在所述衬底基板正投影远离所述电源线在所述衬底基板正投影的一侧。
  15. 根据权利要求14所述的显示面板，其中，所述第二栅线在所述衬底基板正投影与所述第四有源部在所述衬底基板正投影至少部分重合。
  16. 根据权利要求14所述的显示面板，其中，所述像素驱动电路还包括电容，所述电容的第一电极连接于所述驱动晶体管栅极，所述电容的第二电极连接所述第一电源端，所述有源层还包括：
    第五有源部，用于形成所述第二晶体管的第一沟道部；
    第六有源部，用于形成所述第二晶体管的第二沟道部；
    所述第一导电层包括：
    第三栅线，所述第三栅线在所述衬底基板正投影沿所述第三方向延伸，且所述第三栅线在所述衬底基板的正投影覆盖所述第五有源部在所述衬底基板的正投影，部分所述第三栅线用于形成所述第二晶体管的第一栅极；
    第四导电部，所述第四导电部在所述衬底基板的正投影覆盖所述第六有源部在所述衬底基板的正投影，用于形成所述第二晶体管的第二栅极；
    第五导电部，用于形成所述驱动晶体管的栅极和所述电容的第一电极；
    所述第二导电层还包括：
    第六导电部，所述第六导电部在所述衬底基板正投影与所述第五导电部在所述衬底基板的正投影至少部分重合，用于形成所述电容的第二电极，且所述第六导电部在所述衬底基板正投影位于所述第三栅线在所述衬底基板正投影远离所述第一栅线在所述衬底基板正投影的一侧；
    其中，所述第四导电部在所述衬底基板正投影位于所述第三栅线在所述衬底基板正投影和所述第一栅线在所述衬底基板正投影之间。
  17. 根据权利要求16所述的显示面板，其中，所述第三方向为行方向，所述显示面板还包括在行方向上相邻设置的第一像素驱动电路和第二像素驱动电路，所述第二导电层还包括：
    第一连接部，与所述第一像素驱动电路中的驱动晶体管连接同一所述电源线；
    其中，所述第一连接部在所述衬底基板正投影与所述第二像素驱动电路中第二晶体管第一栅极在所述衬底基板正投影至少部分重合。
  18. 根据权利要求16所述的显示面板，其中，所述第一栅线、第三栅线、第三导电部、第四导电部通过光学临近修正掩膜技术同层成型。
  19. 一种显示装置，其中，包括权利要求10-18任一项所述的显示面板。
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CN108122930A (zh) * 2016-11-30 2018-06-05 乐金显示有限公司 薄膜晶体管和使用该薄膜晶体管的显示面板

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CN108122930A (zh) * 2016-11-30 2018-06-05 乐金显示有限公司 薄膜晶体管和使用该薄膜晶体管的显示面板

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